18 Filter math accelerator (FMAC)

18.1 FMAC introduction

The filter math accelerator unit performs arithmetic operations on vectors. It comprises a multiplier/accumulator (MAC) unit, together with address generation logic which allows it to index vector elements held in local memory.

The unit includes support for circular buffers on input and output, which allows digital filters to be implemented. Both finite and infinite impulse response filters can be realized.

The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing up the processor for other tasks. In many cases it can accelerate such calculations compared to a software implementation, resulting in a speed-up of time critical tasks.

18.2 FMAC main features

$16 \times 16$ -bit multiplier

24 + 2-bit accumulator with addition and subtraction

16-bit input and output data

$256 \times 16$ -bit local memory

Up to three areas can be defined in memory for data buffers (two input, one output), defined by programmable base address pointers and associated size registers

Input and output buffers can be circular

Filter functions: FIR, IIR (direct form 1)

Vector functions: Dot product, convolution, correlation

AHB slave interface

DMA read and write data channels

18.3 FMAC functional description

18.3.1 General description

The FMAC is shown in Figure 41. a set of pointers. These pointers can be loaded, incremented, decremented or reset by the internal hardware. The pointer and MAC operations are controlled by a built-in sequencer in order to execute the requested operation.

The unit is built around a fixed point multiplier and accumulator (MAC). The MAC can take two 16-bit input signed values from memory, multiply them together and add them to the contents of the accumulator. The address of the input values in memory is determined using

To calculate a dot product, the two input vectors are loaded into the local memory by the processor or DMA controller, and the requested operation is selected and started. Each pair of input vector elements is fetched from memory, multiplied together and accumulated. When all the vector elements have been processed, the contents of the accumulator are stored in the local memory, from where they can be read out by the processor or DMA.

The finite impulse response (FIR) filter operation (also known as convolution) consists in repeatedly calculating the dot product of the coefficient vector and a vector of input samples, the latter being shifted by one sample delay, with the least recent sample being discarded and a new sample added, at each repetition.

The infinite impulse response (IIR) filter operation is the convolution of the feedback coefficients with the previous output samples, added to the result of the FIR convolution.

A more detailed description of the filter operations is given in Section 18.3.6: Filter functions.

18.3.2 Local memory and buffers

The unit contains a

256 \times 16

-bit read/write memory which is used for local storage:

Input values (the elements of the input vectors) are stored in two buffers, X1 and X2.

Output values (the results of the operations) are stored in another buffer, Y.

The locations and sizes of the buffers are designated as follows:

x1_base: the base address of the X1 buffer

x2_base: the base address of the X2 buffer

y_base: the base address of the $Y$ buffer

x1_buf_size: the number of 16-bit addresses allocated to the X1 buffer

x2_buf_size: the number of 16-bit addresses allocated to the X2 buffer

y_buf_size: the number of 16-bit addresses allocated to the Y buffer.

These parameters are programmed in the corresponding registers when configuring the unit.

The CPU (or DMA controller) can initialize the contents of each buffer using the Initialization functions (Section 18.3.5: Initialization functions) and writing to the write data register. The data is transferred to the location within the target buffer indicated by a write pointer. After each new write, the write pointer is incremented. When the write pointer reaches the end of the allocated buffer space, it wraps back to the base address. This feature is used to load the elements of a vector prior to an operation, or to initialize a filter and load filter coefficients.

Buffer configuration

The buffer sizes and base address offsets must be configured in the X1, X2 and Y buffer configuration registers. For each function, the required buffer size is specified in the function description in Section 18.3.6: Filter functions. The base addresses can be chosen anywhere in internal memory, provided that all buffers fit within the internal memory address range (0x00 to 0xFF), that is, base address + buffer size must be less than 256.

There is no constraint on the size and location of the buffers (they can overlap or even coincide exactly). For filter functions it is recommended not to overlap buffers as this can lead to erroneous behavior.

When circular buffer operation is required, an optional "headroom", d, can be added to the buffer size. Furthermore, a watermark level can be set, to regulate the CPU or DMA activity. The value of

d

and the watermark level must be chosen according to the application performance requirements. For maximum throughput, the input buffer must never go empty, so d must be somewhat greater than the watermark level, allowing for any interrupt or DMA latency. On the other hand, if the input data can not be provided as fast as the unit can process them, the buffer can be allowed to empty waiting for the next data to be written, so

d

can be equal to the watermark level (to ensure that no overflow occurs on the input).

18.3.3 Input buffers

The X1 and X2 buffers are used to store data for input to the MAC. Each multiplication takes a value from the X1 buffer and a value from the X2 buffer and multiplies them together. A pointer in the control unit generates the read address offset (relative to the buffer base address) for each value. The pointers are managed by hardware according to the current function. loaded, except if the contents of the buffer do not change from one operation to the next. For filter functions, the X2 buffer is used to store the filter coefficients.

Figure 43. Circular input buffer

The X2 buffer can only be used in vector mode (that is not circular), and needs to be pre-

When operating as a circular buffer, the space allocated to the buffer (x1_buf_size) must generally be bigger than the number of elements in use for the current calculation, so that there are always new values available in the buffer. Figure 43 illustrates the layout of the buffer for a filter operation. While calculating an output sample

y [n]

,the unit uses a set of

N + 1

input samples,

x [n - N]

x [n]

. When this is finished,the unit starts the calculation of

y [n + 1]

,using the set of input samples

x [n - N + 1]

x [n + 1]

. The least-recent input sample,

x [n -

NJ

,drops out of the input set,and a new sample,

x [n + 1]

,is added to it.

The processor,or DMA controller,must ensure that the new sample

x [n + 1]

is available in the buffer space when required. If not, the buffer is flagged as empty, which stalls the execution of the unit until a new sample is added. No underflow condition is signaled on the X1 buffer.

Note: If the flow of samples is controlled by a timer or other peripheral such as an ADC, the buffer regularly goes empty, since the filter processes each new sample faster than the source can provide it. This is an essential feature of filter operation.

If the number of free spaces in the buffer is less than the watermark threshold programmed in the FULL_WM bitfield of the FMAC_X1BUFCFG register, the buffer is flagged as full. As long as the full flag is not set, interrupts are generated, if enabled, to request more data for the buffer. The watermark allows several data to be transferred under one interrupt, without danger of overflow. Nevertheless, if an overflow does occur, the OVFL error flag is set and the write data is ignored. The write pointer is not incremented in the event of an overflow.

The operation of the X1 buffer during a filtering operation is illustrated in Figure 44. This example shows an 8-tap FIR filter with a watermark set to four.

Figure 44. Circular input buffer operation

18.3.4 Output buffer

The Y (output) buffer is used to store the output of an accumulation. Each new output value is stored in the buffer until it is read by the processor or DMA controller. Each time a read access is made to the read data register, the read data is fetched from the address indicated by the read pointer. This pointer is incremented after each read, and wraps back to the base address when it reaches the end of the allocated

Y

buffer space.

The Y buffer can also operate as a circular buffer. If the address for the next output value is the same as that indicated by the read pointer (an unread sample), then the buffer is flagged as full and execution stalled until the sample is read.

In the case of IIR filters, the Y buffer is used to store the set of M previous output samples,

y [n - M]

y [n - 1]

,used for calculating the next output sample

y [n]

. Each time a new sample is added to the set, the least recent sample y[n-M] drops out.

If the number of unread data in the buffer is less than the watermark threshold programmed in the EMPTY_WM bitfield of the FMAC_YBUFCFG register, the buffer is flagged as empty. As long as the empty flag is not set, interrupts or DMA requests are generated, if enabled, to request reads from the buffer. The watermark allows several data to be transferred under one interrupt, without danger of underflow. Nevertheless, if an underflow does occur, the UNFL error flag is set. In this case, the read pointer is not incremented and the read operation returns the content of the memory at the read pointer address.

The operation of the Y buffer in circular mode is illustrated in Figure 46. This example shows a 7-tap IIR filter with a watermark set to four.

18.3.5 Initialization functions

The following functions initialize the FMAC unit. They are triggered by writing the appropriate value in the FUNC bitfield of the FMAC_PARAM register, with the START bit set. The

P

and

Q

bitfields must also contain the appropriate parameter values for each function as detailed below. The

R

bitfield is not used. When the function completes,the START bit is automatically reset by hardware.

During initialization, it is recommended that the DMA requests and interrupts be disabled. The transfer of data into the FMAC memory can be done by software or by memory-to-memory DMA transfers, since no flow control is required.

Load X1 buffer

This function pre-loads the X1 buffer with N values, starting from the address in X1_BASE. Successive writes to the FMAC_WDATA register load the write data into the X1 buffer and increment the write address. The write pointer points to the address X1_BASE + N when the function completes.

The function can be used to pre-load the buffer with the elements of a vector, or to initialize the input storage elements of a filter.

Parameters

The parameter $P$ contains the number of values, $N$ ,to be loaded into the $X 1$ buffer.

The parameters $Q$ and $R$ are not used.

The function completes when

N

writes have been performed to the FMAC_WDATA register.

Load X2 buffer

This function pre-loads the X2 buffer with N + M values, starting from the address in X2_BASE. Successive writes to the FMAC_WDATA register load the write data into the X2 buffer and increment the write address.

The function can be used to pre-load the buffer with the elements of a vector, or the coefficients of a filter. In the case of an IIR, the N feed-forward and M feed-back coefficients are concatenated and loaded together into the X2 buffer. The total number of coefficients is equal to

N + M

. For an FIR,there are no feedback coefficients,so

M = 0

Parameters

The parameter $P$ contains the number of values, $N$ ,to be loaded into the $X 2$ buffer starting from address X2_BASE.

The parameter Q contains the number of values, M, to be loaded into the X2 buffer starting from address X2_BASE + N.

The parameter $R$ is not used.

The function completes when

N + M

writes have been performed to the FMAC_WDATA register.

Load Y buffer

This function pre-loads the Y buffer with N values, starting from the address in Y_BASE. Successive writes to the FMAC_WDATA register load the write data into the

Y

buffer and increment the write address. The read pointer points to the address Y_BASE + N when the function completes.

The function can be used to pre-load the feedback storage elements of an IIR filter.

Parameters

The parameter $P$ contains the number of values to be loaded into the $Y$ buffer.

The parameters $Q$ and $R$ are not used.

The function completes when

N

writes have been performed to the FMAC_WDATA register.

18.3.6 Filter functions

The following filter functions are supported by the FMAC unit. These functions are triggered by writing the corresponding value in the FUNC bitfield of the FMAC_PARAM register with the START bit set. The P, Q and R bitfields must also contain the appropriate parameter values for each function as detailed below. The filter functions continue to run until the START bit is reset by software.

Convolution (FIR filter)

\underset{―}{Y} = {\underset{―}{B}}^{*} \underset{―}{X}

y_{n} = 2^{R} \cdot \sum_{k = 0}^{N} b_{k} x_{n - k}

This function performs a convolution of a vector

\underset{―}{B}

of length

N + 1

and a vector

\underset{―}{X}

of indefinite length. The elements of

\underset{―}{Y}

for incrementing values of

n

are calculated as the dot product,

y_{n} = \underset{―}{B} . {\underset{―}{X}}_{n}

,where

{\underset{―}{X}}_{n} = [x_{n - N}, \dots, x_{n}]

is composed of the

N + 1

elements of

\underset{―}{X}

at indexes

n - N

to n.

This function corresponds to a finite impulse response (FIR) filter,where vector

\underset{―}{B}

contains the filter coefficients and vector

\underset{―}{X}

the sampled data.

The structure of the filter (direct form) is shown in Figure 47. coefficient vector

\underset{―}{B}

Figure 47. FIR filter structure

Note that the cross correlation vector can be calculated by reversing the order of the

Input:

X1 buffer contains the elements of vector $\underset{―}{X}$ . It is a circular buffer of length $N + 1 + d$ .

X2 buffer contains the elements of vector $\underset{―}{B}$ . It is a fixed buffer of length $N + 1$ .

Output:

$Y$ buffer contains the output values, $y_{n}$ . It is a circular buffer of length $d$ .

Parameters:

The parameter $P$ contains the length, $N + 1$ ,of the coefficient vector $\underset{―}{B}$ in the range [2:127].

The parameter $R$ contains the gain to be applied to the accumulator output. The value output to the $Y$ buffer is multiplied by $2^{R}$ ,where $R$ is in the range $[0.7]$

The parameter $Q$ is not used.

The function completes when the START bit in the FMAC_PARAM register is reset by software.

IIR filter

\underset{―}{Y} = {\underset{―}{B}}^{*} \underset{―}{X} + {\underset{―}{A}}^{*} \underset{―}{Y}

y_{n} = 2^{R} \cdot (\sum_{k = 0}^{N} b_{k} x_{n - k} + \sum_{k = 1}^{M} a_{k} y_{n - k})

This function implements an infinite impulse response (IIR) filter. The filter output vector

\underset{―}{Y}

is the convolution of a coefficient vector

\underset{―}{B}

of length

N + 1

and a vector

\underset{―}{X}

of indefinite length, plus the convolution of the delayed output vector

\underset{―}{Y}

with a second coefficient vector

\underset{―}{A}

,of length

M

. The elements of

\underset{―}{Y}

for incrementing values of

n

are calculated as

y_{n} = \underset{―}{B} \cdot {\underset{―}{X}}_{n} +

{\underset{―}{Y}}_{n - 1}

,where

{\underset{―}{X}}_{n} = [x_{n - N}, \dots, x_{n}]

comprises the

N + 1

elements of

\underset{―}{X}

at indexes

n - N

n

,while

{\underset{―}{Y}}_{n - 1} = [y_{n - M}, \dots, y_{n - 1}]

comprises the

M

elements of

\underset{―}{Y}

at indexes

n - M

n - 1

. The structure of the filter (direct form 1) is shown in Figure 48.

Input:

X1 buffer contains the elements of vector $\underset{―}{X}$ . It is a circular buffer of length $N + 1 + d$ .

X2 buffer contains the elements of coefficient vectors $\underset{―}{B}$ and $\underset{―}{A}$ concatenated $(b_{0}, b_{1}, b_{2} \dots, b_{N}, a_{1}, a_{2}, \dots, a_{M})$ . It is a fixed buffer of length $M + N + 1$ .

Output:

$Y$ buffer contains the output values, $y_{n}$ . It is a circular buffer of length $M + d$ .

Parameters

The parameter $P$ contains the length, $N + 1$ ,of the coefficient vector $\underset{―}{B}$ in the range [2:64].

The parameter $Q$ contains the length, $M$ ,of the coefficient vector $\underset{―}{A}$ in the range [1:63].

The parameter $R$ contains the gain to be applied to the accumulator output. The value output to the $Y$ buffer is multiplied by $2^{R}$ ,where $R$ is in the range $[0 : 7]$ . The function completes when the START bit in the FMAC_PARAM register is reset by software.

18.3.7 Fixed point representation

The FMAC operates in fixed point signed integer format. Input and output values are q1.15.

In q1.15 format, numbers are represented by one sign bit and 15 fractional bits (binary decimal places). The numeric range is therefore -1 (0x8000) to

1 - 2^{- 15}

(0x7FFF).

The accumulator has 26 bits, of which 22 are fractional and 4 are integer/sign (q4.22). This allows it to support partial accumulation sums in the range -8 (0x2000000) to +7.99999976 (0x1FFFFFF). A programmable gain from 0dB to

42 dB

in steps of

6 dB

can be applied at the output of the accumulator.

Note that the content of the accumulator is not saturated if the numeric range is exceeded. Partial sums whose value is greater than +7.99999976 or less than -8 , wrap but this is harmless provided subsequent accumulations undo the wrapping. Nevertheless, the SAT flag in the FMAC_SR register is set if wrapping occurs, and generates an interrupt if the SATIEN bit is set in the FMAC_CR register. This helps in debugging the filter.

The data output by the accumulator can optionally be saturated, after application of the programmable gain, by setting the CLIPEN bit in the FMAC_CR register. If this bit is set, then any value which exceeds the numeric range of the q1.75 output,is set to

1 - 2^{- 15}

or -1, according to the sign. If clipping is not enabled, the unused accumulator bits after applying the gain is simply truncated.

18.3.8 Implementing FIR filters with the FMAC

The FMAC supports FIR filters of length N, where N is the number of taps or coefficients. The minimum local memory requirement for a FIR filter of length

N

2 N + 1

N coefficients

N input samples

1 output sample

Since the local memory size is 256 , the maximum value for

N

is 127 .

If maximum throughput is required, it may be necessary to allocate a small amount of extra space,

d 1

and

d 2

,to the input and output sample buffers respectively,to ensure that the filter never stalls waiting for a new input sample, or waiting for the output sample to be read. In this case,the local memory requirement is

2 N + d 1 + d 2

The buffers must be configured as follows:

X1_BUF_SIZE = N + d1;

X2_BUF_SIZE = N;

Y_BUF_SIZE = d2 (or 1 if no extra space is required)

The buffer base addresses can be allocated anywhere, but the X2 buffer must not overlap with the others, or else the coefficients are overwritten. An example configuration is:

X2_BASE $= 0$ ;

X1_BASE = N;

Y_BASE $= 2 N + d 1$

However,if the memory space is limited,the

X 1

and

Y

buffer areas can be overlapped,such that each output sample takes the place of the oldest input sample, which is no longer required:

X2_BASE $= 0$ ;

X1_BASE = N;

Y_BASE $= N$

In this case, Y_BUF_SIZE = X1_BUF_SIZE = N + d1, so that the buffers remain in sync.

Note:

The FULL_WM bitfield of X1 buffer configuration register must be programmed with a value less than or equal to

\log_{2} (d 1)

,otherwise the buffer is flagged full before

N

input samples have been written, and no more samples are requested. Similarly, the EMPTY_WM bitfield of the

Y

buffer configuration register must be less than or equal to

\log_{2} (d 2)

The filter coefficients must be pre-loaded into the X2 buffer, using the Load X2 Buffer function. The X1 buffer can optionally be pre-loaded with any number of samples up to a maximum of

N

. There is no point in pre-loading the

Y

buffer,since for the FIR filter there is no feedback path.

After configuring and initializing the buffers, the FMAC_CR register must be programmed according to the method used for writing and reading data to and from the FMAC memory.

Three methods are supported:

Polling: No DMA request or Interrupt request is generated. Software must check that the X1_FULL flag is low before writing to WDATA, or that the Y_EMPTY flag is low before reading from RDATA.

Interrupt: The interrupt request is asserted while the X1_FULL flag is low, for writes, or when the Y_EMPTY flag is low, for reads.

DMA: DMA requests are asserted on the DMA write channel while the X1_FULL flag is low, and on the read channel while the Y_EMPTY flag is low.

Different methods can be used for read and for write. However it is not recommended to use both interrupts and DMA requests for the same operation

^{(a)}

. The valid combinations are listed in Table 117.

Table 117. Valid combinations for read and write methods

WIEN	RIEN	DMAWEN	DMAREN	Write	Read
0	0	0	0	Polling	Polling
0	1	0	0	Polling	Interrupt
1	0	0	0	Interrupt	Polling
1	1	0	0	Interrupt	Interrupt
0	0	0	1	Polling	DMA
0	0	1	0	DMA	Polling
0	0	1	1	DMA	DMA
0	1	1	0	DMA	Interrupt
1	0	0	1	Interrupt	DMA

a. If both interrupts and DMA requests are enabled then only DMA must perform the transfer.

The filter is started by writing to the FMAC_PARAM register with the following bitfield values:

FUNC = 8 (FIR filter);

$P = N$ (number of coefficients);

$Q =$ "Don't care";

$R = Gain$ ;

START = 1;

If less than

N + d - 2^{FULL_WM}

values have been pre-loaded in the X1 buffer,the X1FULL flag remains low. If the WIEN bit is set in the FMAC_CR register, then the interrupt request is asserted immediately to request the processor to write

2^{FULL_WM}

additional samples into the buffer, via the FMAC_WDATA register. It remains asserted until the X1FULL flag goes high in the FMAC_SR register. The interrupt service routine must check the X1FULL flag after every

2^{FULL_WM}

writes to the FMAC_WDATA register,and repeat the transfer until the flag goes high. Similarly, if the DMAWEN bit is set in the FMAC_CR register, DMA write channel requests are generated until the X1FULL flag goes high.

The filter calculates the first output sample when at least

N

samples have been written into the X1 buffer (including any pre-loaded samples).

When 2EMPTY_WM output samples have been written into the Y buffer, the YEMPTY flag in the FMAC_SR register goes low. If the RIEN bit is set in the FMAC_CR register, the interrupt request is asserted to request the processor to read

2^{EMPT / Y} - WM

samples from the buffer, via the FMAC_RDATA register. It remains asserted until the YEMPTY flag goes high. The interrupt service routine must check the YEMPTY flag after every

2^{EMPTY_WM}

reads from the FMAC_RDATA register, and repeat the transfer until the flag goes high. If the DMAREN bit is set in the FMAC_CR, DMA read channel requests are generated until the YEMPTY flag goes high.

The filter continues to operate in this fashion until it is stopped by the software resetting the START bit.

18.3.9 Implementing IIR filters with the FMAC

The FMAC supports IIR filters of length N, where N is the number of feed-forward taps or coefficients. The number of feedback coefficients, M, can be any value from 1 to N-1. Only direct form 1 implementations can be realized, so filters designed for other forms need to be converted.

The minimum memory requirement for an IIR filter with N feed-forward coefficients and M feed-back coefficients is

2 N + 2 M

$N + M$ coefficients

N input samples

M output samples

M = N - 1

,then the maximum filter length that can be implemented is

N = 64

As for the FIR, for maximum throughput, a small amount of additional space, d1 and d2, is allowed in the input and output buffer size respectively, making the total memory requirement

2 M + 2 N + d 1 + d 2

The buffers must be configured as follows:

X1_BUF_SIZE = N + d1;

X2_BUF_SIZE = N + M;

Y_BUF_SIZE = M + d2;

The buffer base addresses can be allocated anywhere, but must not overlap. An example configuration is given below:

X2_BASE = 0;

X1_BASE = N + M;

Y_BASE $= 2 N + M + d 1$ ;

Note:

The FULL_WM bitfield of X1 buffer configuration register must be programmed with a value less than or equal to

\log_{2} (d 1)

,otherwise the buffer is flagged full before

N

input samples have been written, and no more samples are requested. Similarly, the EMPTY_WM bitfield of the

Y

buffer configuration register must be less than or equal to

\log_{2} (d 2)

The filter coefficients (N feed-forward followed by M feedback) must be pre-loaded into the X2 buffer, using the Load X2 Buffer function. The X1 buffer can optionally be pre-loaded with any number of samples up to a maximum of

N

. The

Y

buffer can optionally be pre-loaded with any number of values up to a maximum of M. This has the effect of initializing the feedback delay line.

After configuring the buffers, the FMAC_CR register must be programmed in the same way as for the FIR filter (see Section 18.3.8: Implementing FIR filters with the FMAC).

The filter is started by writing to the FMAC_PARAM register with the following bitfield values:

FUNC = 9 (IIR filter);

$P = N$ (number of feed-forward coefficients);

$Q = M$ (number of feed-back coefficients);

$R = Gain$ ;

START = 1;

If less than

N + d - 2^{FULL_WM}

2^{FULL WM}

2^{FULL_WM}

The filter calculates the first output sample when at least

N

samples have been written into the X1 buffer (including any pre-loaded samples). The first sample is calculated using the first

N

samples in the

X 1

buffer,and the first

M

samples in the

Y

buffer (whether or not they are preloaded. The first output sample is written into the

Y

buffer at

Y_B A S E + M

When

2^{EMPTY_WM}

new output samples have been written into the Y buffer,the YEMPTY flag in the FMAC_SR register goes low. If the RIEN bit is set in the FMAC_CR register, the interrupt request is asserted to request the processor to read

2^{EMPTY_WM}

samples from the buffer, via the FMAC_RDATA register. It remains asserted until the YEMPTY flag goes high. The interrupt service routine must check the YEMPTY flag after every

2^{EMPTY_WM}

reads from the FMAC_RDATA register, and repeat the transfer until the flag goes high. If the DMAREN bit is set in the FMAC_CR, DMA read channel requests are generated until the YEMPTY flag goes high

The filter continues to operate in this fashion until it is stopped by the software resetting the START bit.

18.3.11 Examples of filter operation

Figure 50. Filtering example 1

The example in Figure 50 illustrates the beginning of a filter operation. The filter has four taps

(P = 4)

. The

X 1

buffer size is six and the

Y

buffer size is two. The FULL_WM and EMPTY_WM bitfields are both set to 0 . Prior to starting the filter, the X1 buffer has been preloaded with four samples,

x [0 : 3]

as in Figure 49. So the filter starts calculating the first output sample, y[0], immediately after the START bit is set. Since the X1FULL flag is not set (due to two uninitialized spaces in the X1 buffer), the interrupt is asserted straight away, to request new data. The processor writes two new samples,

x [4]

and

x [5]

,to the FMAC_WDATA register, which are transferred to the empty locations in the X1 buffer.

In the mean time, the FMAC finishes calculating the first output sample, y[0], and writes it into the

Y

buffer,causing the

Y_

EMPTY flag to go low. At the same time,the

x [0]

sample is discarded, as it is no longer required, freeing up its location in memory (at X1_BASE). The FMAC can immediately start work on the second output sample, y[1], since all the required input samples

x [1 : 5]

are present in the

X 1

buffer.

Since the Y_EMPTY flag is low, the interrupt remains active after the processor finishes writing

x [5]

. The processor reads

y [0]

from the FMAC_RDATA register,freeing up its location in the Y buffer. There are now no samples in the output buffer since y[1] is still being calculated, so the Y_EMPTY flag goes high. Nevertheless, the interrupt remains active, because there is still free space in the X1 buffer, which the processor next fills with x[6], and so on.

Note: In this example, the processor can fill the input buffer more quickly than the FMAC can process them,so the

X 1

_full flag regularly goes active. However,it struggles to read the

Y

buffer fast enough,so the FMAC stalls regularly waiting for space to be freed up in the

Y

buffer. This means the filter is not executing at maximum throughput. The reason is that the filter length is small and the processor relatively slow,in this example. So increasing the Y buffer size would not help.

Figure 51. Filtering example 2

The example in Figure 51 illustrates the beginning of the same filter operation, but this time the filter has six taps

(P = 6)

. The

X 1

buffer size is six and the

Y

buffer size is two. The FULL_WM and EMPTY_WM bitfields are both set to 0 . Prior to starting the filter, the X1 buffer has been pre-loaded with four samples,

x [0 : 3]

as in Figure 49. Because there are not enough samples in the input buffer, the X1FULL flag is not set, so the interrupt is asserted straight away, to request new data. The FMAC is stalled.

The processor writes two new samples,

x [4]

and

x [5]

,to the FMAC_WDATA register,which are transferred to the empty locations in the X1 buffer. As soon as there are six unused samples in the X1 buffer, the X1_FULL flag goes active (since the buffer size is six), causing the interrupt to go inactive. The FMAC starts calculating the first output sample, y[0]. Since this requires all six input samples,there are no free spaces in the

X 1

buffer and so the X1_FULL flag remains active. Only when the FMAC finishes calculating

y [0]

and writes it into the

Y

buffer,can

x [0]

be discarded,freeing up a space in the

X 1

buffer,and deasserting X1_FULL. At the same time, the Y_EMPTY flag goes inactive. Both these flag states cause the interrupt to be asserted, requesting the processor to write a new input sample, first of all, and then read the output sample just calculated. The FMAC remains stalled until a new input sample is written.

In this example, the processor has to wait for the FMAC to finish calculating the current output sample,before it can write a new input sample,and therefore the

X 1

buffer regularly goes empty, stalling the FMAC. This can be avoided by allowing some extra space in the input buffer.

18.3.12 Filter design tips

The FMAC architecture imposes some constraints detailed below, on the design of digital filters.

Implementation of direct form 2, or transposed forms, is not efficient. Filters which have been designed for such forms must be converted to direct form 1.

Cascaded filters must either be combined into a single stage, or implemented as separate filters. In the latter case, multiple sets of filter coefficients can be pre-loaded into the memory, one set per stage, and only the X2_BASE address changed to select which set is used. The most efficient method of implementing a multi-stage filter is to pre-load a large $X 1$ buffer with input samples,run the IIR filter function on it using the first stage coefficients, and store the output samples back in memory. Then change the X2_BASE pointer to point to the 2nd stage coefficients, and reload the input buffer with the output of the first stage (with a gain if required), before running the IIR function again. The procedure is repeated for all stages. Once the final stage samples have been transferred back into system memory, the input buffer can be loaded with the next set of input samples,and a new round of calculations started. Note that the $N$ sample input buffer of each stage must be pre-loaded first of all with the $N - 1$ last inputs from the previous round, plus one new sample, in order to keep continuity between each round. Similarly, the output buffer of each stage must be loaded with the last M samples from the previous round, for the same reason.

The use of direct form 1 for IIR designs can lead to large positive or negative partial sums in the accumulator, if for example a large step occurs on the input, or some of the filter coefficients’ absolute values are $> 1$ . Since the accumulator is limited to 26 bits,the biggest value that it can handle without wrapping (changing sign) is 0x1FFFFFF positive or 0x2000000 negative. This corresponds to 3.99999988 and -4 respectively in q3.23 fixed point format. Wrapping does not represent a problem provided the wrapping is "undone" before the end of the accumulation. However this is not always the case when a filter is starting up and can lead to unexpected results. Consider pre-loading the output buffer with suitable values to avoid this.

The IIR filter has feed-forward (numerator) coefficients $[b_{0}, b_{1}, \dots, b_{N - 1}]$ ,and feed-back (denominator) coefficients $[1, a_{1}, \dots, a_{M}]$ . Many IIR filters require some of the denominator coefficients to have an absolute value greater than 1 to achieve a steep roll-off in the frequency response. Given that the coefficients are coded in fixed point q1.15 format, this is not possible. Nevertheless, by scaling the denominator coefficients by a factor $2^{- R}$ ,such that $2^{- R} \cdot [1, a_{1}, \dots, a_{M}]$ are all less than 1,such filters can be implemented. However an inverse gain of $2^{R}$ must be applied at the output of the accumulator to compensate the scaling. This has an adverse effect on the signal-to-noise ratio.

18.4 FMAC registers

18.4.1 FMAC X1 buffer configuration register (FMAC_X1BUFCFG)

Address offset: 0x00

Reset value: 0x00000000

Access: word access

This register can only be modified if START = 0 in the FMAC_PARAM register.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.		FULL_WM[1:0]	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
						rw	rw

Bits 31:26 Reserved, must be kept at reset value.

Bits 25:24 FULL_WM[1:0]: Watermark for buffer full flag

Defines the threshold for setting the X1 buffer full flag when operating in circular mode. The flag is set if the number of free spaces in the buffer is less than

2^{FULL WM}

0 : Threshold

= 1

1: Threshold

= 2

2: Threshold

= 4

3: Threshold

= 8

Setting a threshold greater than 1 allows several data to be transferred into the buffer under one interrupt.

Threshold must be set to 1 if DMA write requests are enabled (DMAWEN = 1 in FMAC_CR register).

Bits 23:16 Reserved, must be kept at reset value.

Bits 15:8 X1_BUF_SIZE[7:0]: Allocated size of X1 buffer in 16-bit words

The minimum buffer size is the number of feed-forward taps in the filter (+ the watermark threshold - 1).

Bits 7:0 X1_BASE[7:0]: Base address of X1 buffer

18.4.2 FMAC X2 buffer configuration register (FMAC_X2BUFCFG)

Address offset: 0x04

Reset value: 0x00000000

Access: word access

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:8 X2_BUF_SIZE[7:0]: Size of X2 buffer in 16-bit words

This bitfield can not be modified when a function is ongoing (START = 1).

Bits 7:0 X2_BASE[7:0]: Base address of X2 buffer

The X2 buffer base address can be modified while START=1, for example to change

coefficient values. The filter must be stalled when doing this, since changing the coefficients

while a calculation is ongoing affects the result.

18.4.3 FMAC Y buffer configuration register (FMAC_YBUFCFG)

Address offset: 0x08

Reset value: 0x00000000

Access: word access

This register can only be modified if START = 0 in the FMAC_PARAM register.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	EMPTYWM[1:0]		Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
						rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Y_BUF_SIZE[7:0]								Y_BASE[7:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:26 Reserved, must be kept at reset value.

Bits 25:24 EMPTY_WM[1:0]: Watermark for buffer empty flag

Defines the threshold for setting the Y buffer empty flag when operating in circular mode.

The flag is set if the number of unread values in the buffer is less than

2^{EMPTY_WM}

0 : Threshold

= 1

1: Threshold

= 2

2: Threshold

= 4

3: Threshold

= 8

Setting a threshold greater than 1 allows several data to be transferred from the buffer under one interrupt.

Threshold must be set to 1 if DMA read requests are enabled (DMAREN = 1 in FMAC_CR register).

Bits 23:16 Reserved, must be kept at reset value.

Bits 15:8 Y_BUF_SIZE[7:0]: Size of Y buffer in 16-bit words

For FIR filters, the minimum buffer size is 1 (+ the watermark threshold). For IIR filters the minimum buffer size is the number of feedback taps (+ the watermark threshold).

Bits 7:0 Y_BASE[7:0]: Base address of

Y

buffer

18.4.4 FMAC parameter register (FMAC_PARAM)

Address offset: 0x0C

Reset value: 0x00000000

Access: word access

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
START	FUNC[6:0]							R[7:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Q[7:0]								P[7:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bit 31 START: Enable execution

0 : Stop execution

1: Start execution

Setting this bit triggers the execution of the function selected in the FUNC bitfield. Resetting it by software stops any ongoing function. For initialization functions, this bit is reset by hardware.

Bits 30:24 FUNC[6:0]: Function

0 : Reserved

1: Load X1 buffer

2: Load X2 buffer

3: Load Y buffer

4 to 7: Reserved

8: Convolution (FIR filter)

9: IIR filter (direct form 1)

10 to 127: Reserved

This bitfield can not be modified when a function is ongoing (START = 1)

Bits 23:16 R[7:0]: Input parameter R.

The value of this parameter is dependent on the function.

This bitfield can not be modified when a function is ongoing (START = 1)

Bits 15:8 Q[7:0]: Input parameter Q.

The value of this parameter is dependent on the function.

This bitfield can not be modified when a function is ongoing (START = 1)

Bits 7:0 P[7:0]: Input parameter P.

The value of this parameter is dependent on the function

This bitfield can not be modified when a function is ongoing (START = 1)

18.4.5 FMAC control register (FMAC_CR)

Address offset: 0x10

Reset value: 0x00000000

Access: word access

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 RESET: Reset FMAC unit

This resets the write and read pointers, the internal control logic, the FMAC_SR register and the FMAC_PARAM register, including the START bit if active. Other register settings are not affected. This bit is reset by hardware.

0 : Reset inactive

1: Reset active

Bit 15 CLIPEN: Enable clipping

0: Clipping disabled. Values at the output of the accumulator which exceed the q1.15 range, wrap.

1: Clipping enabled. Values at the output of the accumulator which exceed the q1.15 range are saturated to the maximum positive or negative value

(+ 1 or -1)

according to the sign.

Bits 14:10 Reserved, must be kept at reset value.

Bit 9 DMAWEN: Enable DMA write channel requests

0: Disable. No DMA requests are generated

1: Enable. DMA requests are generated while the X1 buffer is not full.

This bit can only be modified when START= 0 in the FMAC_PARAM register. A read returns

the current state of the bit.

Bit 8 DMAREN: Enable DMA read channel requests

0: Disable. No DMA requests are generated

1: Enable. DMA requests are generated while the

Y

buffer is not empty.

This bit can only be modified when START

= 0

in the FMAC_PARAM register. A read returns

the current state of the bit.

Bits 7:5 Reserved, must be kept at reset value.

Bit 4 SATIEN: Enable saturation error interrupts

0: Disabled. No interrupts are generated upon saturation detection.

1: Enabled. An interrupt request is generated if the SAT flag is set

This bit is set and cleared by software. A read returns the current state of the bit.

Bit 3 UNFLIEN: Enable underflow error interrupts

0: Disabled. No interrupts are generated upon underflow detection.

1: Enabled. An interrupt request is generated if the UNFL flag is set

This bit is set and cleared by software. A read returns the current state of the bit.

Bit 2 OVFLIEN: Enable overflow error interrupts

0: Disabled. No interrupts are generated upon overflow detection.

1: Enabled. An interrupt request is generated if the OVFL flag is set

This bit is set and cleared by software. A read returns the current state of the bit.

Bit 1 WIEN: Enable write interrupt

0: Disabled. No write interrupt requests are generated.

1: Enabled. An interrupt request is generated while the X1 buffer FULL flag is not set.

This bit is set and cleared by software. A read returns the current state of the bit.

Bit 0 RIEN: Enable read interrupt

0: Disabled. No read interrupt requests are generated.

1: Enabled. An interrupt request is generated while the Y buffer EMPTY flag is not set.

This bit is set and cleared by software. A read returns the current state of the bit.

18.4.6 FMAC status register (FMAC_SR)

Address offset: 0x14

Reset value: 0x00000001

Access: word access

Res.

SAT

UNFL

OVFL

Res.

X1 FULL

Y EMPTY

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 SAT: Saturation error flag

Saturation occurs when the result of an accumulation exceeds the numeric range of the accumulator.

0 : No saturation detected

1: Saturation detected. If the SATIEN bit is set, an interrupt is generated.

This flag is cleared by a reset of the unit.

Bit 9 UNFL: Underflow error flag

An underflow occurs when a read is made from FMAC_RDATA when no valid data is

available in the

Y

buffer.

0 : No underflow detected

1: Underflow detected. If the UNFLIEN bit is set, an interrupt is generated.

This flag is cleared by a reset of the unit.

Bit 8 OVFL: Overflow error flag

An overflow occurs when a write is made to FMAC_WDATA when no free space is available in the X1 buffer.

0 : No overflow detected

1: Overflow detected. If the OVFLIEN bit is set, an interrupt is generated.

This flag is cleared by a reset of the unit.

Bits 7:2 Reserved, must be kept at reset value.

Bit 1 X1FULL: X1 buffer full flag

The buffer is flagged as full if the number of available spaces is less than the FULL_WM threshold. The number of available spaces is the difference between the write pointer and the least recent sample currently in use.

0: X1 buffer not full. If the WIEN bit is set, the interrupt request is asserted until the flag is set. If DMAWEN is set, DMA write channel requests are generated until the flag is set. 1: X1 buffer full.

This flag is set and cleared by hardware, or by a reset.

Note: after the last available space in the X1 buffer is filled there is a delay of 3 clock cycles before the X1FULL flag goes high. To avoid any risk of overflow it is recommended to insert a software delay after writing to the

X 1

buffer before reading the FMAC_SR. Alternatively, a FULL_WM threshold of 2 can be used.

Bit 0 YEMPTY: Y buffer empty flag

The buffer is flagged as empty if the number of unread data is less than the EMPTY_WM threshold. The number of unread data is the difference between the read pointer and the current output destination address.

Y

buffer not empty. If the RIEN bit is set,the interrupt request is asserted until the flag is set. If DMAREN is set, DMA read channel requests are generated until the flag is set.

1: Y buffer empty.

This flag is set and cleared by hardware, or by a reset.

Note: after the last sample is read from the

Y

buffer there is a delay of 3 clock cycles before the YEMPTY flag goes high. To avoid any risk of underflow it is recommended to insert a software delay after reading from the Y buffer before reading the FMAC_SR.

Alternatively, an EMPTY_WM threshold of 2 can be used.

18.4.7 FMAC write data register (FMAC_WDATA)

Address offset: 0x18

Reset value: 0x00000000

Access: word access

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 WDATA[15:0]: Write data

When a write access to this register occurs, the write data are transferred to the address offset indicated by the write pointer. The pointer address is automatically incremented after each write access.

18.4.8 FMAC read data register (FMAC_RDATA)

Address offset: 0x1C

Reset value: 0x00000000

Access: word access

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 RDATA[15:0]: Read data

When a read access to this register occurs,the read data are the contents of the

Y

output buffer at the address offset indicated by the READ pointer. The pointer address is automatically incremented after each read access.

18.4.9 FMAC register map

Table 118.FMAC register map and reset values

Offset	Register name	31	3.0	2Q3	2Q3	27	2623	24	23	22	21	2023	9	8	17	1.	1.5	4	13	12	110	98	76	5	4	3	2	10
0x00	FMAC_X1BUFCFG	品	13	超市		：	：nm 7.7.0.3	1.00	3	：	3	：	SHE	y	g	yé	X1_BUF_SIZE[7:0]						X1_BASE[7:0]
0x00	Reset value						0	0									0	0	0	0	00	00	00	0	0	0	0	00
0x04	FMAC_X2BUFCFG	y	3	3	3.00	3	8锅	1.00	COMP	y y	g	绿色	y4	S	y y	：		X2_BUF_SIZE[7:0]					X2_BASE[7:0]
0x04	Reset value																0	0	0	0	00	00	00	0	0	0	0	00
0x08	FMAC YBUFCFG	3	3	y	好的	a	3WM 人LdW3	(1,001)	:	3	8	3	3	g	3	:					Y_BUF_SIZE[7:0]		Y_BASE[7:0]
0x08	Reset value						0	0									0	0	0	0	00	00	00	0	0	0	0	00
0x0C	FMAC PARAM	SARE	FUNC[6:0]						R[7:0]								Q[7:0]						P[7:0]
0x0C	Reset value	0	0	0	0	0	00	0	0	0	0	0	0	0	0	0	0	0	0	0	00	00	00	0	0	0	0	00
0x10	FMAC_CR	of	of	LUS	8	新中	Leten	COMP	Let	SCON	Let	vi	时	:	3	13838	N3d170	of	沙	：	SO3	N3MVWONEVVWO	Let新	a	NEILVS	Naihyn	NEITHAO	VolumineREE
0x10	Reset value															0	0					00			0	0	0	00
0x14	FMAC_SR	1,000	Life	COMP	1.0	Let	WLet	时	8	B	y)	LUB	STAR	S	好好	小	好的	新华	LUB	B	好的SS	SHAOF	LetLet	3	Laborated	Let	y3	11NHLX人LdW3人
0x14	Reset value																				0	00						01
0x18	FMAC_WDATA	时	SCON	S		S	3STA	千港元	CON	3	3	STA	S	SCON	S	8	WDATA[15:0]
0x1C	Reset value FMAC_RDATA	8	8	：		Wi	3新时	时	B	SCON	La	锅	LUM	8	3	B	0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATA[15:0]
0x1C	Reset value																0000000000000000

19 Flexible static memory controller (FSMC)

19.1 Introduction

The flexible static memory controller (FSMC) includes two memory controllers:

The NOR/PSRAM memory controller

The NAND memory controller

This memory controller is also named flexible memory controller (FMC).

19.2 FMC main features

The FMC functional block makes the interface with: synchronous and asynchronous static memories, and NAND flash memory. Its main purposes are:

to translate AHB transactions into the appropriate external device protocol

to meet the access time requirements of the external memory devices

All external memories share the addresses, data and control signals with the controller. Each external device is accessed by means of a unique chip select. The FMC performs only one access at a time to an external device.

The main features of the FMC controller are the following:

Interface with static-memory mapped devices including:

Static random access memory (SRAM)

NOR flash memory/OneNAND flash memory

PSRAM (4 memory banks)

Ferroelectric RAM (FRAM)

NAND flash memory with ECC hardware to check up to 8 Kbytes of data

Interface with parallel LCD modules, supporting Intel 8080 and Motorola 6800 modes.

Burst mode support for faster access to synchronous devices such as NOR flash memory, PSRAM)

Programmable continuous clock output for asynchronous and synchronous accesses

8-,16-bit wide data bus

Independent chip select control for each memory bank

Independent configuration for each memory bank

Write enable and byte lane select outputs for use with PSRAM, SRAM devices

External asynchronous wait control

Write FIFO with $16 \times 32$ -bit depth

The Write FIFO is common to all memory controllers and consists of:

a Write Data FIFO which stores the AHB data to be written to the memory (up to 32 bits) plus one bit for the AHB transfer (burst or not sequential mode)

a Write Address FIFO which stores the AHB address (up to 28 bits) plus the AHB data size (up to 2 bits). When operating in burst mode, only the start address is stored except when crossing a page boundary (for PSRAM). In this case, the AHB burst is broken into two FIFO entries.

At startup the FMC pins must be configured by the user application. The FMC I/O pins which are not used by the application can be used for other purposes.

The FMC registers that define the external device type and associated characteristics are usually set at boot time and do not change until the next reset or power-up. However, the settings can be changed at any time.

19.3 FMC block diagram

The FMC consists of the following main blocks:

The AHB interface (including the FMC configuration registers)

The NOR flash/PSRAM/SRAM controller

The block diagram is shown in the figure below.

Figure 52. FMC block diagram

19.4 AHB interface

The AHB slave interface allows internal CPUs and other bus master peripherals to access the external memories.

AHB transactions are translated into the external device protocol. In particular, if the selected external memory is 16- or 8-bit wide, 32-bit wide transactions on the AHB are split into consecutive 16- or 8-bit accesses. The FMC chip select (FMC_NEx) does not toggle between the consecutive accesses except in case of Access mode D when the Extended mode is enabled.

The FMC generates an AHB error in the following conditions:

When reading or writing to a FMC bank (Bank 1 to 4) which is not enabled.

When reading or writing to the NOR flash bank while the FACCEN bit is reset in the FMC_BCRx register.

The effect of an AHB error depends on the AHB master which has attempted the R/W access:

If the access has been attempted by the Cortex $^{®}$ -M4 with FPU CPU,a hard fault interrupt is generated.

If the access has been performed by a DMA controller, a DMA transfer error is generated and the corresponding DMA channel is automatically disabled.

The AHB clock (HCLK) is the reference clock for the FMC.

19.4.1 Supported memories and transactions

General transaction rules

The requested AHB transaction data size can be 8-, 16- or 32-bit wide whereas the accessed external device has a fixed data width. This may lead to inconsistent transfers.

Therefore, some simple transaction rules must be followed:

AHB transaction size and memory data size are equal

There is no issue in this case.

AHB transaction size is greater than the memory size:

In this case, the FMC splits the AHB transaction into smaller consecutive memory accesses to meet the external data width. The FMC chip select (FMC_NEx) does not toggle between the consecutive accesses. If the bus turnaround timings is configured to any other value than 0 , the FMC chip select (FMC_NEx) toggles between the consecutive accesses. This feature is required when interfacing with FRAM memory.

AHB transaction size is smaller than the memory size:

The transfer may or not be consistent depending on the type of external device:

Accesses to devices that have the byte select feature (SRAM, ROM, PSRAM)

In this case, the FMC allows read/write transactions and accesses to the right data through its byte lanes NBL[1:0].

Bytes to be written are addressed by NBL[1:0].

All memory bytes are read (NBL[1:0] are driven low during read transaction) and the useless ones are discarded.

Accesses to devices that do not have the byte select feature (NOR and NAND flash memories)

This situation occurs when a byte access is requested to a 16-bit wide flash memory. Since the device cannot be accessed in Byte mode (only 16-bit words can be read/written from/to the flash memory), Write transactions and Read transactions are allowed (the controller reads the entire 16-bit memory word and uses only the required byte).

Wrap support for NOR flash/PSRAM

Wrap burst mode for synchronous memories is not supported. The memories must be configured in Linear burst mode of undefined length.

Configuration registers

The FMC can be configured through a set of registers. Refer to Section 19.6.6, for a detailed description of the NOR flash/PSRAM controller registers. Refer to Section 19.7.7, for a detailed description of the NAND flash registers.

19.5 External device address mapping

From the FMC point of view, the external memory is divided into fixed-size banks of

256 Mbytes each (see Figure 53):

Bank 1 used to address up to 4 NOR flash memory or PSRAM devices. This bank is split into 4 NOR/PSRAM subbanks with 4 dedicated chip selects, as follows:

Bank 1 - NOR/PSRAM 1

Bank 1 - NOR/PSRAM 2

Bank 1 - NOR/PSRAM 3

Bank 1 - NOR/PSRAM 4

Bank 3 used to address NAND flash memory devices.The MPU memory attribute for this space must be reconfigured by software to Device.

For each bank the type of memory to be used can be configured by the user application through the Configuration register.

Figure 53. FMC memory banks

19.5.1 NOR/PSRAM address mapping

HADDR[27:26] bits are used to select one of the four memory banks as shown in Table 119.

Table 119. NOR/PSRAM bank selection

HADDR[27:26](1)	Selected bank
00	Bank 1 - NOR/PSRAM 1
01	Bank 1 - NOR/PSRAM 2

Table 119. NOR/PSRAM bank selection (continued)

HADDR[27:26](1)	Selected bank
10	Bank 1 - NOR/PSRAM 3
11	Bank 1 - NOR/PSRAM 4

HADDR are internal AHB address lines that are translated to external memory.

The HADDR[25:0] bits contain the external memory address. Since HADDR is a byte address whereas the memory is addressed at word level, the address actually issued to the memory varies according to the memory data width, as shown in the following table.

Table 120. NOR/PSRAM External memory address

Memory width(1)	Data address issued to the memory	Maximum memory capacity (bits)
8-bit	HADDR[25:0]	64 Mbytes x 8 = 512 Mbits
16-bit	HADDR[25:1] >> 1	64 Mbytes/2 x 16 = 512 Mbits

In case of a 16-bit external memory width, the FMC internally uses HADDR[25:1] to generate the address for external memory FMC_A[24:0].

Whatever the external memory width, FMC_A[0] must be connected to external memory address A[0].

19.5.2 NAND flash memory address mapping

The NAND bank is divided into memory areas as indicated in Table 121.

Table 121. NAND memory mapping and timing registers

Start address	End address	FMC bank	Memory space	Timing register
0x8800 0000	0x8BFF FFFF	Bank 3 - NAND flash	Attribute	FMC_PATT (0x8C)
0x8000 0000	0x83FF FFFF	Bank 3 - NAND flash	Common	FMC_PMEM (0x88)

For NAND flash memory, the common and attribute memory spaces are subdivided into three sections (see in Table 122 below) located in the lower 256 Kbytes:

Data section (first 64 Kbytes in the common/attribute memory space)

Command section (second 64 Kbytes in the common / attribute memory space)

Address section (next 128 Kbytes in the common / attribute memory space)

Table 122. NAND bank selection

Section name	HADDR[17:16]	Address range
Address section	1X	0x020000-0x03FFFF
Command section	01	0x010000-0x01FFFF
Data section	00	0x000000-0x0FFFF

The application software uses the 3 sections to access the NAND flash memory:

To sending a command to NAND flash memory, the software must write the command value to any memory location in the command section.

To specify the NAND flash address that must be read or written, the software must write the address value to any memory location in the address section. Since an address can be 4 or 5 bytes long (depending on the actual memory size), several consecutive write operations to the address section are required to specify the full address.

To read or write data, the software reads or writes the data from/to any memory location in the data section.

Since the NAND flash memory automatically increments addresses, there is no need to increment the address of the data section to access consecutive memory locations.

19.6 NOR flash/PSRAM controller

The FMC generates the appropriate signal timings to drive the following types of memories:

Asynchronous SRAM, FRAM and ROM

8 bits

– 16 bits

PSRAM (CellularRAM $^{TM}$ )

Asynchronous mode

Burst mode for synchronous accesses

Multiplexed or non-multiplexed

NOR flash memory

Asynchronous mode

Burst mode for synchronous accesses

Multiplexed or non-multiplexed

The FMC outputs a unique chip select signal, NE[4:1], per bank. All the other signals (addresses, data and control) are shared.

The FMC supports a wide range of devices through a programmable timings among which:

Programmable wait states (up to 15)

Programmable bus turnaround cycles (up to 15)

Programmable output enable and write enable delays (up to 15)

Independent read and write timings and protocol to support the widest variety of memories and timings

Programmable continuous clock (FMC_CLK) output.

The FMC Clock (FMC_CLK) is a submultiple of the HCLK clock. It can be delivered to the selected external device either during synchronous accesses only or during asynchronous and synchronous accesses depending on the CCKEN bit configuration in the FMC_BCR1 register:

If the CCLKEN bit is reset, the FMC generates the clock (CLK) only during synchronous accesses (Read/write transactions).

If the CCLKEN bit is set, the FMC generates a continuous clock during asynchronous and synchronous accesses. To generate the FMC_CLK continuous clock, Bank 1 must be configured in Synchronous mode (see Section 19.6.6: NOR/PSRAM controller registers). Since the same clock is used for all synchronous memories, when a continuous output clock is generated and synchronous accesses are performed, the AHB data size has to be the same as the memory data width (MWID) otherwise the FMC_CLK frequency is changed depending on AHB data transaction (refer to Section 19.6.5: Synchronous transactions for FMC_CLK divider ratio formula).

The size of each bank is fixed and equal to 64 Mbytes. Each bank is configured through dedicated registers (see Section 19.6.6: NOR/PSRAM controller registers).

The programmable memory parameters include access times (see Table 123) and support for wait management (for PSRAM and NOR flash accessed in Burst mode).

Table 123. Programmable NOR/PSRAM access parameters

Parameter	Function	Access mode	Unit	Min.	Max.
Address setup	Duration of the address setup phase	Asynchronous	AHB clock cycle (HCLK)	0	15
Address hold	Duration of the address hold phase	Asynchronous, muxed I/Os	AHB clock cycle (HCLK)	1	15
NBL setup	Duration of the byte lanes setup phase	Asynchronous	AHB clock cycle (HCLK)	0	3
Data setup	Duration of the data setup phase	Asynchronous	AHB clock cycle (HCLK)	1	256
Data hold	Duration of the data hold phase	Asynchronous	AHB clock cycle (HCLK)	0	3
Bust turn	Duration of the bus turnaround phase	Asynchronous and synchronous read / write	AHB clock cycle (HCLK)	0	15
Clock divide ratio	Number of AHB clock cycles (HCLK) to build one memory clock cycle (CLK)	Synchronous	AHB clock cycle (HCLK)	2	16
Data latency	Number of clock cycles to issue to the memory before the first data of the burst	Synchronous	Memory clock cycle (CLK)	2	17

19.6.1 External memory interface signals

Table 124, Table 125 and Table 126 list the signals that are typically used to interface with NOR flash memory, SRAM and PSRAM.

Note: The prefix "N" identifies the signals that are active low.

NOR flash memory, non-multiplexed I/Os

Table 124. Non-multiplexed I/O NOR flash memory

FMC signal name	I/O	Function
CLK	O	Clock (for synchronous access)
A[25:0]	0	Address bus

Table 124. Non-multiplexed I/O NOR flash memory (continued)

FMC signal name	I/O	Function
D[15:0]	I/O	Bidirectional data bus
NE[x]	O	Chip select, x = 1..4
NOE	0	Output enable
NWE	0	Write enable
$NL (= NADV)$	0	Latch enable (this signal is called address valid, NADV, by some NOR flash devices
NWAIT	1	NOR flash wait input signal to the FMC

The maximum capacity is 512 Mbits (26 address lines).

NOR flash memory, 16-bit multiplexed I/Os

Table 125. 16-bit multiplexed I/O NOR flash memory

FMC signal name	I/O	Function
CLK	O	Clock (for synchronous access)
A[25:16]	O	Address bus
AD[15:0]	I/O	16-bit multiplexed, bidirectional address/data bus (the 16-bit address A[15:0] and data D[15:0] are multiplexed on the databus
NE[x]	O	Chip select, x = 1..4
NOE	O	Output enable
NWE	O	Write enable
$NL (= NADV)$	0	Latch enable (this signal is called address valid, NADV, by some NOR flash devices)
NWAIT	1	NOR flash wait input signal to the FMC

The maximum capacity is 512 Mbits.

PSRAM/FRAM/SRAM, non-multiplexed I/Os

Table 126. Non-multiplexed I/Os PSRAM/SRAM

FMC signal name	I/O	Function
CLK	O	Clock (only for PSRAM synchronous access)
A[25:0]	O	Address bus
D[15:0]	I/O	Data bidirectional bus
NE[x]	O	Chip select, $x = 1. .4$ (called NCE by PSRAM (CellularRAM $^{TM}$ i.e. CRAM)
NOE	O	Output enable
NWE	O	Write enable
$NL (= NADV)$	O	Address valid only for PSRAM input (memory signal name: NADV)

Table 126. Non-multiplexed I/Os PSRAM/SRAM (continued)

FMC signal name	I/O	Function
NWAIT	1	PSRAM wait input signal to the FMC
NBL[1:0]	O	Byte lane output. Byte 0 and Byte 1 control (upper and lower byte enable)

The maximum capacity is 512 Mbits.

PSRAM, 16-bit multiplexed I/Os

Table 127. 16-Bit multiplexed I/O PSRAM

FMC signal name	I/O	Function
CLK	O	Clock (for synchronous access)
A[25:16]	O	Address bus
AD[15:0]	I/O	16-bit multiplexed, bidirectional address/data bus (the 16-bit address A[15:0] and data D[15:0] are multiplexed on the databus)
NE[x]	O	Chip select, $x = 1. .4$ (called NCE by PSRAM (CellularRAM $^{TM}$ i.e. CRAN
NOE	O	Output enable
NWE	O	Write enable
$NL (= NADV)$	O	Address valid PSRAM input (memory signal name: NADV)
NWAIT	1	PSRAM wait input signal to the FMC
NBL[1:0]	O	Byte lane output. Byte 0 and Byte 1 control (upper and lower byte enable)

The maximum capacity is 512 Mbits (26 address lines).

19.6.2 Supported memories and transactions

Table 128 below shows an example of the supported devices, access modes and transactions when the memory data bus is 16-bit wide for NOR flash memory, PSRAM and SRAM. The transactions not allowed (or not supported) by the FMC are shown in gray in this example.

Table 128. NOR flash/PSRAM: example of supported memories and transactions

Device	Mode	R/W	AHB data size	Memory data size	Allowed/ not allowed	Comments
NOR flash (muxed I/Os and nonmuxed I/Os)	Asynchronous	R	8	16	Y	-
	Asynchronous	W	8	16	N	-
	Asynchronous	R	16	16	Y	-
	Asynchronous	W	16	16	Y	-
	Asynchronous	R	32	16	Y	Split into 2 FMC accesses
	Asynchronous	W	32	16	Y	Split into 2 FMC accesses
	Asynchronous page	R	-	16	N	Mode is not supported
	Synchronous	R	8	16	N	-
	Synchronous	R	16	16	Y	-
	Synchronous	R	32	16	Y	-
PSRAM (multiplexed I/Os and non- multiplexed I/Os)	Asynchronous	R	8	16	Y	-
	Asynchronous	W	8	16	Y	Use of byte lanes NBL[1:0]
	Asynchronous	R	16	16	Y	-
	Asynchronous	W	16	16	Y	-
	Asynchronous	R	32	16	Y	Split into 2 FMC accesses
	Asynchronous	W	32	16	Y	Split into 2 FMC accesses
	Asynchronous page	R	-	16	N	Mode is not supported
	Synchronous	R	8	16	N	-
	Synchronous	R	16	16	Y	-
	Synchronous	R	32	16	Y	-
	Synchronous	W	8	16	Y	Use of byte lanes NBL[1:0]
	Synchronous	W	16/32	16	Y	-
SRAM and ROM	Asynchronous	R	$8 / 16$	16	Y	-
	Asynchronous	W	$8 / 16$	16	Y	Use of byte lanes NBL[1:0]
	Asynchronous	R	32	16	Y	Split into 2 FMC accesses
	Asynchronous	W	32	16	Y	Split into 2 FMC accesses Use of byte lanes NBL[1:0]

19.6.3 General timing rules

Signals synchronization

All controller output signals change on the rising edge of the internal clock (HCLK)

In Synchronous mode (read or write), all output signals change on the rising edge of HCLK. Whatever the CLKDIV value, all outputs change as follows:

NOEL/NWEL/ NEL/NADVL/ NADVH /NBLL/ Address valid outputs change on the falling edge of FMC_CLK clock.

NOEH/ NWEH / NEH/ NOEH/NBLH/ Address invalid outputs change on the rising edge of FMC_CLK clock.

19.6.4 NOR flash/PSRAM controller asynchronous transactions

Asynchronous static memories (NOR flash, PSRAM, SRAM, FRAM)

Signals are synchronized by the internal clock HCLK. This clock is not issued to the memory

The FMC always samples the data before de-asserting the NOE signal. This guarantees that the memory data hold timing constraint is met (minimum Chip Enable high to data transition is usually $0 ns$ )

If the Extended mode is enabled (EXTMOD bit is set in the FMC_BCRx register), up to four extended modes (A, B, C and D) are available. It is possible to mix A, B, C and D modes for read and write operations. For example, read operation can be performed in mode A and write in mode B.

If the Extended mode is disabled (EXTMOD bit is reset in the FMC_BCRx register), the FMC can operate in mode 1 or mode 2 as follows:

Mode 1 is the default mode when SRAM/PSRAM memory type is selected (MTYP $= 0 \times 0$ or $0 \times 01$ in the FMC_BCRx register)

Mode 2 is the default mode when NOR memory type is selected (MTYP = 0x10 in the FMC_BCRx register).

The DATAHLD time at the end of the read and write transactions guarantee the address and data hold time after the NOE/NWE rising edge. The DATAST value must be greater than zero (DATAST > 0).

Table 129. FMC_BCRx bitfields (mode 1)

Bit number	Bit name	Value to set
31:24	Reserved	0x000
23:22	NBLSET[1:0]	As needed
20	CCLKEN	As needed
19	CBURSTRW	0x0 (no effect in Asynchronous mode)
18:16	CPSIZE	0x0 (no effect in Asynchronous mode)
15	ASYNCWAIT	Set to 1 if the memory supports this feature. Otherwise keep at 0.
14	EXTMOD	0x0
13	WAITEN	0x0 (no effect in Asynchronous mode)
12	WREN	As needed
10	Reserved	0x0
9	WAITPOL	Meaningful only if bit 15 is 1
8	BURSTEN	0x0
7	Reserved	0x1
6	FACCEN	Don't care
5:4	MWID	As needed
3:2	MTYP	As needed, exclude 0x2 (NOR flash memory)
1	MUXE	0x0
0	MBKEN	0x1

Table 130. FMC_BTRx bitfields (mode 1)

Bit number	Bit name	Value to set
31:30	DATAHLD	Duration of the data hold phase (DATAHLD HCLK cycles for read accesses, DATAHLD+1 HCLK cycles for write accesses
29:28	ACCMOD	Don't care
27:24	DATLAT	Don't care
23:20	CLKDIV	Don't care
19:16	BUSTURN	Time between NEx high to NEx low (BUSTURN HCLK).
15:8	DATAST	Duration of the second access phase (DATAST HCLK cycles)
7:4	ADDHLD	Don't care
3:0	ADDSET	Duration of the first access phase (ADDSET HCLK cycles). Minimum value for ADDSET is 0.

Table 131. FMC_BCRx bitfields (mode A)

Bit number	Bit name	Value to set
31:24	Reserved	0x000
23:22	NBLSET[1:0]	As needed
20	CCLKEN	As needed
19	CBURSTRW	0x0 (no effect in Asynchronous mode)
18:16	CPSIZE	0x0 (no effect in Asynchronous mode)
15	ASYNCWAIT	Set to 1 if the memory supports this feature. Otherwise keep at 0.
14	EXTMOD	0x1
13	WAITEN	0x0 (no effect in Asynchronous mode)
12	WREN	As needed
11	WAITCFG	Don't care
10	Reserved	0x0
9	WAITPOL	Meaningful only if bit 15 is 1
8	BURSTEN	0x0
7	Reserved	0x1
6	FACCEN	Don't care
5:4	MWID	As needed
3:2	MTYP	As needed, exclude 0x2 (NOR flash memory)
1	MUXEN	0x0
0	MBKEN	0x1

Table 132. FMC_BTRx bitfields (mode A)

Bit number	Bit name	Value to set
31:30	DATAHLD	Duration of the data hold phase (DATAHLD HCLK cycles for read accesses).
29:28	ACCMOD	0x0
27:24	DATLAT	Don't care
23:20	CLKDIV	Don’t care
19:16	BUSTURN	Time between NEx high to NEx low (BUSTURN HCLK).
15:8	DATAST	Duration of the second access phase (DATAST HCLK cycles) for read accesses.
7:4	ADDHLD	Don't care
3:0	ADDSET	Duration of the first access phase (ADDSET HCLK cycles) for read accesses. Minimum value for ADDSET is 0.

Table 134. FMC_BCRx bitfields (mode 2/B)

Bit number	Bit name	Value to set
31:24	Reserved	0x000
23:22	NBLSET[1:0]	Don't care
20	CCLKEN	As needed
19	CBURSTRW	0x0 (no effect in Asynchronous mode)
18:16	CPSIZE	0x0 (no effect in Asynchronous mode)
15	ASYNCWAIT	Set to 1 if the memory supports this feature. Otherwise keep at 0 .
14	EXTMOD	0x1 for mode B, 0x0 for mode 2
13	WAITEN	0x0 (no effect in Asynchronous mode)
12	WREN	As needed
11	WAITCFG	Don't care
10	Reserved	0x0
9	WAITPOL	Meaningful only if bit 15 is 1
8	BURSTEN	0x0
7	Reserved	0x1
6	FACCEN	0x1
5:4	MWID	As needed
3:2	MTYP	0x2 (NOR flash memory)
1	MUXEN	0x0
0	MBKEN	0x1

Table 135. FMC_BTRx bitfields (mode 2/B)

Bit number	Bit name	Value to set
31:30	DATAHLD	Duration of the data hold phase (DATAHLD HCLK cycles for read accesses and DATAHLD+1 HCLK cycles for write accesses when Extended mode is disabled)
29:28	ACCMOD	0x1 if Extended mode is set
27:24	DATLAT	Don't care
23:20	CLKDIV	Don't care
19:16	BUSTURN	Time between NEx high to NEx low (BUSTURN HCLK)
15:8	DATAST	Duration of the access second phase (DATAST HCLK cycles) for read accesses.
7:4	ADDHLD	Don't care
3:0	ADDSET	Duration of the access first phase (ADDSET HCLK cycles) for read accesses. Minimum value for ADDSET is 0.

Table 136. FMC_BWTRx bitfields (mode 2/B)

Bit number	Bit name	Value to set
31:30	DATAHLD	Duration of the data hold phase (DATAHLD+1 HCLK cycles for write accesses).
29:28	ACCMOD	0x1 if Extended mode is set
27:24	DATLAT	Don't care
23:20	CLKDIV	Don't care
19:16	BUSTURN	Time between NEx high to NEx low (BUSTURN HCLK)
15:8	DATAST	Duration of the access second phase (DATAST HCLK cycles) for write accesses.
7:4	ADDHLD	Don’t care
3:0	ADDSET	Duration of the access first phase (ADDSET HCLK cycles) for write accesses. Minimum value for ADDSET is 0.

Note: The FMC_BWTRx register is valid only if the Extended mode is set (mode B), otherwise its content is don't care.

Mode C - NOR flash - OE toggling

Figure 61. Mode C read access waveforms

Table 137. FMC_BCRx bitfields (mode C) (continued)

Bit number	Bit name	Value to set
3:2	MTYP	0x02 (NOR flash memory)
1	MUXEN	0x0
0	MBKEN	0x1

Table 138. FMC_BTRx bitfields (mode C)

Bit number	Bit name	Value to set
31:30	DATAHLD	Duration of the data hold phase (DATAHLD HCLK cycles for read accesses).
29:28	ACCMOD	0x2
27:24	DATLAT	0x0
23:20	CLKDIV	0x0
19:16	BUSTURN	Time between NEx high to NEx low (BUSTURN HCLK).
15:8	DATAST	Duration of the second access phase (DATAST HCLK cycles) for read accesses.
7:4	ADDHLD	Don't care
3:0	ADDSET	Duration of the first access phase (ADDSET HCLK cycles) for read accesses. Minimum value for ADDSET is 0

Table 139. FMC_BWTRx bitfields (mode C)

Bit number	Bit name	Value to set
31:30	DATAHLD	Duration of the data hold phase (DATAHLD+1 HCLK cycles for write accesses).
29:28	ACCMOD	0x2
27:24	DATLAT	Don't care
23:20	CLKDIV	Don't care
19:16	BUSTURN	Time between NEx high to NEx low (BUSTURN HCLK).
15:8	DATAST	Duration of the second access phase (DATAST HCLK cycles) for write accesses.
7:4	ADDHLD	Don't care
3:0	ADDSET	Duration of the first access phase (ADDSET HCLK cycles) for write accesses. Minimum value for ADDSET is 0

Figure 64. Mode D write access waveforms

The differences with mode 1 are the toggling of NOE that goes on toggling after NADV changes and the independent read and write timings.

Table 140. FMC_BCRx bitfields (mode D)

Bit number	Bit name	Value to set
31:24	Reserved	0x000
23:22	NBLSET[1:0]	As needed
20	CCLKEN	As needed
19	CBURSTRW	0x0 (no effect in Asynchronous mode)
18:16	CPSIZE	0x0 (no effect in Asynchronous mode)
15	ASYNCWAIT	Set to 1 if the memory supports this feature. Otherwise keep at 0.
14	EXTMOD	0x1
13	WAITEN	0x0 (no effect in Asynchronous mode)
12	WREN	As needed
11	WAITCFG	Don't care
10	Reserved	0x0
9	WAITPOL	Meaningful only if bit 15 is 1
8	BURSTEN	0x0
7	Reserved	0x1

Table 140. FMC_BCRx bitfields (mode D) (continued)

Bit number	Bit name	Value to set
6	FACCEN	Set according to memory support
5:4	MWID	As needed
3:2	MTYP	As needed
1	MUXEN	0x0
0	MBKEN	0x1

Table 141. FMC_BTRx bitfields (mode D)

Bit number	Bit name	Value to set
31:30	DATAHLD	Duration of the data hold phase (DATAHLD HCLK cycles for read accesses).
29:28	ACCMOD	0x3
27:24	DATLAT	Don't care
23:20	CLKDIV	Don't care
19:16	BUSTURN	Time between NEx high to NEx low (BUSTURN HCLK).
15:8	DATAST	Duration of the second access phase (DATAST HCLK cycles) for read accesses.
7:4	ADDHLD	Duration of the middle phase of the read access (ADDHLD HCLK cycles)
3:0	ADDSET	Duration of the first access phase (ADDSET HCLK cycles) for read accesses. Minimum value for ADDSET is 1.

Table 142. FMC_BWTRx bitfields (mode D)

Bit number	Bit name	Value to set
31:30	DATAHLD	Duration of the data hold phase (DATAHLD+1 HCLK cycles for write accesses).
29:28	ACCMOD	0x3
27:24	DATLAT	Don't care
23:20	CLKDIV	Don't care
19:16	BUSTURN	Time between NEx high to NEx low (BUSTURN HCLK).
15:8	DATAST	Duration of the second access phase (DATAST HCLK cycles).
7:4	ADDHLD	Duration of the middle phase of the write access (ADDHLD HCLK cycles)
3:0	ADDSET	Duration of the first access phase (ADDSET HCLK cycles) for write accesses. Minimum value for ADDSET is 1

Table 143. FMC_BCRx bitfields (Muxed mode) (continued)

Bit number	Bit name	Value to set
5:4	MWID	As needed
3:2	MTYP	0x2 (NOR flash memory) or 0x1(PSRAM)
1	MUXEN	0x1
0	MBKEN	0x1

Table 144. FMC_BTRx bitfields (Muxed mode)

Bit number	Bit name	Value to set
31:30	DATAHLD	Duration of the data hold phase (DATAHLD HCLK cycles for read accesses, DATAHLD+1 HCLK cycles for write accesses
29:28	ACCMOD	0x0
27:24	DATLAT	Don't care
23:20	CLKDIV	Don't care
19:16	BUSTURN	Time between NEx high to NEx low (BUSTURN HCLK).
15:8	DATAST	Duration of the second access phase (DATAST HCLK cycles).
7:4	ADDHLD	Duration of the middle phase of the access (ADDHLD HCLK cycles)
3:0	ADDSET	Duration of the first access phase (ADDSET HCLK cycles). Minimum value for ADDSET is 1.

WAIT management in asynchronous accesses

If the asynchronous memory asserts the WAIT signal to indicate that it is not yet ready to accept or to provide data, the ASYNCWAIT bit has to be set in FMC_BCRx register.

If the WAIT signal is active (high or low depending on the WAITPOL bit), the second access phase (Data setup phase), programmed by the DATAST bits, is extended until WAIT becomes inactive. Unlike the data setup phase, the first access phases (Address setup and Address hold phases), programmed by the ADDSET and ADDHLD bits, are not WAIT sensitive and so they are not prolonged.

The data setup phase must be programmed so that WAIT can be detected 4 HCLK cycles before the end of the memory transaction. The following cases must be considered:

The memory asserts the WAIT signal aligned to NOE/NWE which toggles:

DATAST \geq (4 \times HCLK) + max_wait_assertion_time

The memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling):

max_wait_assertion_time > address_phase + hold_phase

then:

DATAST

\geq (4 \times HCLK) + (max_wait_assertion_time - address_phase - hold_phase)

otherwise

DATAST \geq 4 \times HCLK

where max_wait_assertion_time is the maximum time taken by the memory to assert the WAIT signal once NEx/NOE/NWE is low.

Figure 67 and Figure 68 show the number of HCLK clock cycles that are added to the memory access phase after WAIT is released by the asynchronous memory (independently of the above cases).

Figure 67. Asynchronous wait during a read access waveforms

NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register.

Figure 68. Asynchronous wait during a write access waveforms

NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register.

CellularRAM $^{TM}$ (PSRAM) refresh management

The CellularRAM

^{TM}

does not enable maintaining the chip select signal (NE) low for longer than the

t_{CEM}

timing specified for the memory device. This timing can be programmed in the FMC_PCSCNTR register. It defines the maximum duration of the NE low pulse in HCLK cycles for asynchronous accesses and FMC_CLK cycles for synchronous accesses

19.6.5 Synchronous transactions

The memory clock, FMC_CLK, is a submultiple of HCLK. It depends on the value of CLKDIV and the MWID/AHB data size, following the formula given below:

Whatever MWID size: 16 or 8-bit, the FMC_CLK divider ratio is always defined by the programmed CLKDIV value.

Example:

If CLKDIV=1, MWID = 16 bits, AHB data size=8 bits, FMC_CLK=HCLK/2.

NOR flash memories specify a minimum time from NADV assertion to CLK high. To meet this constraint, the FMC does not issue the clock to the memory during the first internal clock cycle of the synchronous access (before NADV assertion). This guarantees that the rising edge of the memory clock occurs in the middle of the NADV low pulse.

Data latency versus NOR memory latency

The data latency is the number of cycles to wait before sampling the data. The DATLAT value must be consistent with the latency value specified in the NOR flash configuration

Caution: Some NOR flash memories include the NADV Low cycle in the data latency count, so that the exact relation between the NOR flash latency and the FMC DATLAT parameter can be either:

NOR flash latency $= (DATLAT + 2)$ CLK clock cycles

or NOR flash latency $= (DATLAT + 3)$ CLK clock cycles

Some recent memories assert NWAIT during the latency phase. In such cases DATLAT can be set to its minimum value. As a result, the FMC samples the data and waits long enough to evaluate if the data are valid. Thus the FMC detects when the memory exits latency and real data are processed.

Other memories do not assert NWAIT during latency. In this case the latency must be set correctly for both the FMC and the memory, otherwise invalid data are mistaken for good data, or valid data are lost in the initial phase of the memory access.

Single-burst transfer

When the selected bank is configured in Burst mode for synchronous accesses, if for example an AHB single-burst transaction is requested on 16-bit memories, the FMC performs a burst transaction of length 1 (if the AHB transfer is 16 bits), or length 2 (if the AHB transfer is 32 bits) and de-assert the chip select signal when the last data is strobed.

Such transfers are not the most efficient in terms of cycles compared to asynchronous read operations. Nevertheless, a random asynchronous access would first require to re-program the memory access mode, which would altogether last longer.

Cross boundary page for CellularRAM $^{TM} 1.5$

CellularRAM

^{TM} 1.5

does not allow burst access to cross the page boundary. The FMC controller is used to split automatically the burst access when the memory page size is reached by configuring the CPSIZE bits in the FMC_BCR1 register following the memory page size.

Wait management

For synchronous NOR flash memories, NWAIT is evaluated after the programmed latency period, which corresponds to (DATLAT+2) CLK clock cycles.

If NWAIT is active (low level when WAITPOL = 0, high level when WAITPOL = 1), wait states are inserted until NWAIT is inactive (high level when WAITPOL = 0 , low level when WAITPOL = 1).

When NWAIT is inactive,the data is considered valid either immediately (bit WAITCFG

= 1

) or on the next clock edge (bit WAITCFG

= 0

During wait-state insertion via the NWAIT signal, the controller continues to send clock pulses to the memory, keeping the chip select and output enable signals valid. It does not consider the data as valid.

In Burst mode, there are two timing configurations for the NOR flash NWAIT signal:

The flash memory asserts the NWAIT signal one data cycle before the wait state (default after reset).

The flash memory asserts the NWAIT signal during the wait state

Figure 70. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM)

Byte lane outputs (NBL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access, they are held low.

Table 145. FMC_BCRx bitfields (Synchronous multiplexed read mode)

Bit number	Bit name	Value to set
31:24	Reserved	0x000
23:22	NBLSET[1:0]	Don't care
20	CCLKEN	As needed
19	CBURSTRW	No effect on synchronous read
18:16	CPSIZE	0x0 (no effect in Asynchronous mode)
15	ASYNCWAIT	0x0
14	EXTMOD	0x0
13	WAITEN	To be set to 1 if the memory supports this feature, to be kept at 0 otherwise
12	WREN	No effect on synchronous read
11	WAITCFG	To be set according to memory
10	Reserved	0x0
9	WAITPOL	To be set according to memory

Bit number	Bit name	Value to set
8	BURSTEN	0x1
7	Reserved	0x1
6	FACCEN	Set according to memory support (NOR flash memory)
5-4	MWID	As needed
3-2	MTYP	0x1 or 0x2
1	MUXEN	As needed
0	MBKEN	0x1

Bit number	Bit name	Value to set
31:30	DATAHLD	Don't care
29:28	ACCMOD	0x0
27-24	DATLAT	Data latency
27-24	DATLAT	Data latency
23-20	CLKDIV	0x0 to get CLK = HCLK 0x1 to get CLK = 2 × HCLK ..
19-16	BUSTURN	Time between NEx high to NEx low (BUSTURN HCLK).
15-8	DATAST	Don't care
7-4	ADDHLD	Don't care
3-0	ADDSET	Don't care

Table 147. FMC_BCRx bitfields (Synchronous multiplexed write mode) (continued)

Bit number	Bit name	Value to set
12	WREN	0x1
11	WAITCFG	0x0
10	Reserved	0x0
9	WAITPOL	to be set according to memory
8	BURSTEN	no effect on synchronous write
7	Reserved	0x1
6	FACCEN	Set according to memory support
5-4	MWID	As needed
3-2	MTYP	0x1
1	MUXEN	As needed
0	MBKEN	0x1

Table 148. FMC_BTRx bitfields (Synchronous multiplexed write mode)

Bit number	Bit name	Value to set
31-30	DATAHLD	Don't care
29:28	ACCMOD	0x0
27-24	DATLAT	Data latency
23-20	CLKDIV	0x0 to get CLK = HCLK 0x1 to get CLK = 2 × HCLK
19-16	BUSTURN	Time between NEx high to NEx low (BUSTURN HCLK).
15-8	DATAST	Don't care
7-4	ADDHLD	Don't care
3-0	ADDSET	Don't care

19.6.6 NOR/PSRAM controller registers

SRAM/NOR-flash chip-select control register for bank

x

(FMC_BCRx)

(x = 1 to 4)

Address offset:

0 \times 00 + 0 \times 8 * (x - 1), (x = 1 to 4)

Reset value: 0x0000 30DB, 0x0000 30D2, 0x0000 30D2, 0x0000 30D2

This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR flash memories.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	NBLSET[1:0]		WFDIS	CCLK EN	CBURST RW	CPSIZE[2:0]
								rw	rw	rw	rw	rw	rw	rw	rw

ASYNC WAIT	EXT MOD	WAIT EN	WREN	WAIT CFG	Res.	WAIT POL	BURST EN	Res.	FACC EN	MWID[1:0]		MTYP[1:0]		MUX EN	MBK EN
rw	rw	rw	rw	rw		rw	rw		rw	rw	rw	rw	rw	rw	rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:22 NBLSET[1:0]: Byte lane (NBL) setup

These bits configure the NBL setup timing from NBLx low to chip select NEx low.

00: NBL setup time is 0 AHB clock cycle

01: NBL setup time is 1 AHB clock cycle

10: NBL setup time is

2 AHB

clock cycles

11: NBL setup time is 3 AHB clock cycles

Bit 21 WFDIS: Write FIFO disable

This bit disables the Write FIFO used by the FMC controller.

0: Write FIFO enabled (Default after reset)

1: Write FIFO disabled

Note: The WFDIS bit of the FMC_BCR2..4 registers is don't care. It is only enabled through the FMC_BCR1 register.

Bit 20 CCLKEN: Continuous clock enable

This bit enables the FMC_CLK clock output to external memory devices. 0: The FMC_CLK is only generated during the synchronous memory access (read/write transaction). The FMC_CLK clock ratio is specified by the programmed CLKDIV value in the FMC_BCRx register (default after reset).

1: The FMC_CLK is generated continuously during asynchronous and synchronous access. The FMC_CLK clock is activated when the CCLKEN is set.

Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the FMC_CLK continuous clock.

Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don't care.

Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.)

Bit 19 CBURSTRW: Write burst enable

For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register.

0 : Write operations are always performed in Asynchronous mode.

1: Write operations are performed in Synchronous mode.

Bits 18:16 CPSIZE[2:0]: CRAM page size

These are used for CellularRAM

^{TM} 1.5

which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). 000: No burst split when crossing page boundary (default after reset)

001: 128 bytes

010: 256 bytes

011: 512 bytes

100: 1024 bytes

Others: Reserved, must not be used

Bit 15 ASYNCWAIT: Wait signal during asynchronous transfers

This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. 0: NWAIT signal is not taken in to account when running an asynchronous protocol (default after reset).

1: NWAIT signal is taken in to account when running an asynchronous protocol.

Bit 14 EXTMOD: Extended mode enable

This bit enables the FMC to program the write timings for non multiplexed asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. 0: values inside FMC_BWTR register are not taken into account (default after reset) 1: values inside FMC_BWTR register are taken into account

Note: When the Extended mode is disabled, the FMC can operate in mode 1 or mode 2 as follows:

Mode 1 is the default mode when the SRAM/PSRAM memory type is selected $(M T Y P = 0 \times 0 or 0 \times 01)$

Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10).

Bit 13 WAITEN: Wait enable bit

This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in Synchronous mode.

0: NWAIT signal is disabled (its level not taken into account, no wait state inserted after the programmed flash latency period).

1: NWAIT signal is enabled (its level is taken into account after the programmed latency period to insert wait states if asserted) (default after reset).

Bit 12 WREN: Write enable bit

This bit indicates whether write operations are enabled/disabled in the bank by the FMC.

0 : Write operations are disabled in the bank by the FMC, an AHB error is reported.

1: Write operations are enabled for the bank by the FMC (default after reset).

Bit 11 WAITCFG: Wait timing configuration

The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in Synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state: 0: NWAIT signal is active one data cycle before wait state (default after reset). 1: NWAIT signal is active during wait state (not used for PSRAM).

Bit 10 Reserved, must be kept at reset value.

Bit 9 WAITPOL: Wait signal polarity bit

Defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous mode.

0: NWAIT active low (default after reset)

1: NWAIT active high

Bit 8 BURSTEN: Burst enable bit

This bit enables/disables synchronous accesses during read operations. It is valid only for

synchronous memories operating in Burst mode.

0: Burst mode disabled (default after reset). Read accesses are performed in Asynchronous mode.

1: Burst mode enable. Read accesses are performed in Synchronous mode.

Bit 7 Reserved, must be kept at reset value.

Bit 6 FACCEN: Flash access enable

Enables NOR flash memory access operations.

0: Corresponding NOR flash memory access is disabled.

1: Corresponding NOR flash memory access is enabled (default after reset).

Bits 5:4 MWID[1:0]: Memory data bus width

Defines the external memory device width, valid for all type of memories.

00: 8 bits

01: 16 bits (default after reset)

10: reserved

11: reserved

Bits 3:2 MTYP[1:0]: Memory type

Defines the type of external memory attached to the corresponding memory bank.

00: SRAM/FRAM (default after reset for Bank 2...4)

01: PSRAM (CRAM) / FRAM

10: NOR flash/OneNAND flash (default after reset for Bank 1)

11: reserved

Bit 1 MUXEN: Address/data multiplexing enable bit

When this bit is set, the address and data values are multiplexed on the data bus, valid only with

NOR and PSRAM memories:

0: Address/data non multiplexed

1: Address/data multiplexed on databus (default after reset)

Bit 0 MBKEN: Memory bank enable bit

Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a

disabled bank causes an ERROR on AHB bus.

0 : Corresponding memory bank is disabled.

1: Corresponding memory bank is enabled.

SRAM/NOR-flash chip-select timing register for bank

x

(FMC_BTRx)

Address offset:

0 \times 04 + 0 \times 8 * (x - 1), (x = 1 to 4)

Reset value: 0x0FFF FFFF

This register contains the control information of each memory bank, used for SRAMs,

PSRAM and NOR flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then

this register is partitioned for write and read access, that is, 2 registers are available: one to

configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATAHLD[1:0]		ACCMOD[1:0]		DATLAT[3:0]				CLKDIV[3:0]				BUSTURN[3:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								ADDLILDION				ADDOSTION

DATAST[7:0]								ADDHLD[3:0]				ADDSET[3:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:30 DATAHLD[1:0]: Data hold phase duration

These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 54 to Figure 66), used in asynchronous accesses:

For read accesses

00: DATAHLD phase duration

= 0 \times

HCLK clock cycle (default)

01: DATAHLD phase duration

= 1 \times

HCLK clock cycle

10: DATAHLD phase duration

= 2 \times

HCLK clock cycle

11: DATAHLD phase duration

= 3 \times

HCLK clock cycle

For write accesses

00: DATAHLD phase duration

= 1 \times

HCLK clock cycle (default)

01: DATAHLD phase duration

= 2 \times

HCLK clock cycle

10: DATAHLD phase duration

= 3 \times

HCLK clock cycle

11: DATAHLD phase duration

= 4 \times

HCLK clock cycle

Bits 29:28 ACCMOD[1:0]: Access mode

Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1 .

00: Access mode A

01: Access mode B

10: Access mode C

11: Access mode D

Bits 27:24 DATLAT[3:0]: (see note below bit descriptions): Data latency for synchronous memory

For synchronous access with read/write Burst mode enabled (BURSTEN / CBURSTRW bits set),defines the number of memory clock cycles

(+ 2)

to issue to the memory before reading/writing the first data:

This timing parameter is not expressed in HCLK periods, but in FMC_CLK periods.

For asynchronous access, this value is don't care.

0000: Data latency of 2 CLK clock cycles for first burst access

1111: Data latency of

17 CLK

clock cycles for first burst access (default value after reset)

Bits 23:20 CLKDIV[3:0]: Clock divide ratio (for FMC_CLK signal)

Defines the period of FMC_CLK clock output signal, expressed in number of HCLK cycles:

0000: FMC_CLK period= 1x HCLK period

0001: FMC_CLK period

= 2 \times

HCLK periods

0010: FMC_CLK period

= 3 \times

HCLK periods

1111: FMC_CLK period

= 16 \times

HCLK periods (default value after reset)

In asynchronous NOR flash, SRAM or PSRAM accesses, this value is don't care.

Note: Refer to Section 19.6.5: Synchronous transactions for FMC_CLK divider ratio formula)

Bits 19:16 BUSTURN[3:0]: Bus turnaround phase duration

These bits are written by software to add a delay at the end of current read or write transaction to next transaction on the same bank.

This delay is used to match the minimum time between consecutive transactions

(t_{EHEL}

from NEx high to NEx low) and the maximum time needed by the memory to free the data bus after a read access (

t_{EHQZ}

,chip enable high to output

Hi - Z

). This delay is recommended for mode

D

and muxed mode. For non-muxed memory,the bus turnaround delay can be set to minimum value.

(BUSTURN + 1)HCLK period

\geq max (t_{EHEL} min, t_{EHQZ} max)

For FRAM memories, the bus turnaround delay must be configured to match the minimum tPC (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read) to match the tPC memory timing. The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period

\geq t_{PC}

min

0000: BUSTURN phase duration

= 1 HCLK

clock cycle added

1111: BUSTURN phase duration

= 16 \times

HCLK clock cycles added (default value after reset)

Bits 15:8 DATAST[7:0]: Data-phase duration

These bits are written by software to define the duration of the data phase (refer to Figure 54 to Figure 66), used in asynchronous accesses:

00000000: Reserved

00000001: DATAST phase duration

= 1 \times

HCLK clock cycles

00000010: DATAST phase duration

= 2 \times

HCLK clock cycles

\dots

1111 1111: DATAST phase duration

= 255 \times

HCLK clock cycles (default value after reset)

For each memory type and access mode data-phase duration, refer to the respective figure (Figure 54 to Figure 66).

Example: Mode 1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 HCLK clock cycles.

Note: In synchronous accesses, this value is don't care.

Bits 7:4 ADDHLD[3:0]: Address-hold phase duration

These bits are written by software to define the duration of the address hold phase (refer to

Figure 54 to Figure 66), used in mode D or multiplexed accesses:

0000: Reserved

0001: ADDHLD phase duration

= 1 \times

HCLK clock cycle

0010: ADDHLD phase duration

= 2 \times

HCLK clock cycle

\dots

1111: ADDHLD phase duration

= 15 \times

HCLK clock cycles (default value after reset)

For each access mode address-hold phase duration, refer to the respective figure (Figure 54 to Figure 66).

Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration.

Bits 3:0 ADDSET[3:0]: Address setup phase duration

These bits are written by software to define the duration of the address setup phase (refer to Figure 54 to Figure 66), used in SRAMs, ROMs, asynchronous NOR flash and PSRAM: 0000: ADDSET phase duration

= 0 \times

HCLK clock cycle

\dots

1111: ADDSET phase duration

= 15 \times

HCLK clock cycles (default value after reset)

For each access mode address setup phase duration, refer to the respective figure (Figure 54 to Figure 66).

Note: In synchronous accesses, this value is don't care.

In Muxed mode or mode D, the minimum value for ADDSET is 1.

In mode 1 and PSRAM memory, the minimum value for ADDSET is 1 .

Note: PSRAMs (CRAMs) have a variable latency due to internal refresh. Therefore these memories issue the NWAIT signal during the whole latency phase to prolong the latency as needed.

With PSRAMs (CRAMs) the filled DATLAT must be set to 0, so that the FMC exits its latency

phase soon and starts sampling NWAIT from memory, then starts to read or write when the memory is ready.

This method can be used also with the latest generation of synchronous flash memories that

issue the NWAIT signal, unlike older flash memories (check the datasheet of the specific flash memory being used).

SRAM/NOR-flash write timing registers x (FMC_BWTRx)

Address offset: 0x104 + 0x8 * (x - 1), (x = 1 to 4)

Reset value: 0x0FFF FFFF

This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATAHLD[1:0]		ACCMOD[1:0]		Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	BUSTURN[3:0]
rw	rw	rw	rw									rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATAST[7:0]								ADDHLD[3:0]				ADDSET[3:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:30 DATAHLD[1:0]: Data hold phase duration

These bits are written by software to define the duration of the data hold phase in HCLK cycles

(refer to Figure 54 to Figure 66), used in asynchronous write accesses:

00: DATAHLD phase duration

= 1 \times

HCLK clock cycle (default)

01: DATAHLD phase duration

= 2 \times

HCLK clock cycle

10: DATAHLD phase duration

= 3 \times

HCLK clock cycle

11: DATAHLD phase duration

= 4 \times

HCLK clock cycle

Bits 29:28 ACCMOD[1:0]: Access mode.

Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1 .

00: Access mode A

01: Access mode B

10: Access mode C

11: Access mode D

Bits 27:20 Reserved, must be kept at reset value.

Bits 19:16 BUSTURN[3:0]: Bus turnaround phase duration

These bits are written by software to add a delay at the end of current write transaction to next transaction on the same bank.

For FRAM memories,the bus turnaround delay must be configured to match the minimum

t_{PC}

(precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read). The chip select is toggling between any consecutive accesses.

(BUSTURN + 1)HCLK period

\geq tPC

min

0000: BUSTURN phase duration

= 1 HCLK

clock cycle added

1111: BUSTURN phase duration

= 16 \times HCLK

clock cycles added (default value after reset)

Bits 15:8 DATAST[7:0]: Data-phase duration.

These bits are written by software to define the duration of the data phase (refer to Figure 54 to Figure 66), used in asynchronous SRAM, PSRAM and NOR flash memory accesses: 00000000: Reserved

00000001: DATAST phase duration

= 1 \times

HCLK clock cycles

00000010: DATAST phase duration

= 2 \times

HCLK clock cycles

1111 1111: DATAST phase duration

= 255 \times

HCLK clock cycles (default value after reset)

Bits 7:4 ADDHLD[3:0]: Address-hold phase duration.

These bits are written by software to define the duration of the address hold phase (refer to

Figure 63 to Figure 66), used in asynchronous multiplexed accesses:

0000: Reserved

0001: ADDHLD phase duration

= 1 \times

HCLK clock cycle

0010: ADDHLD phase duration

= 2 \times

HCLK clock cycle

\dots

1111: ADDHLD phase duration

= 15 \times

HCLK clock cycles (default value after reset)

Note: In synchronous NOR flash accesses, this value is not used, the address hold phase is always

1 flash clock period duration.

Bits 3:0 ADDSET[3:0]: Address setup phase duration.

These bits are written by software to define the duration of the address setup phase in HCLK cycles

(refer to Figure 54 to Figure 66), used in asynchronous accesses:

0000: ADDSET phase duration

= 0 \times

HCLK clock cycle

\dots

1111: ADDSET phase duration

= 15 \times

HCLK clock cycles (default value after reset)

Note: In synchronous accesses, this value is not used, the address setup phase is always 1 flash clock period duration. In muxed mode, the minimum ADDSET value is 1 .

PSRAM chip select counter register (FMC_PCSCNTR)

Address offset: 0x20

Reset value: 0x00000000

This register contains the PSRAM chip select counter value for Synchronous and Asynchronous modes. The chip select counter is common to all banks and can be enabled separately on each bank. During PSRAM read or write accesses, this value is loaded into a timer which is decremented while the NE signal is held low. When the timer reaches 0 , the PSRAM controller splits the current access, toggles NE to allow PSRAM device refresh, and restarts a new access. The programmed counter value guarantees a maximum NE pulse width

(t_{CEM})

as specified for PSRAM devices. The counter is reloaded and starts decrementing each time a new access is started by a transition of NE from high to low.

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 CNTB4EN: Counter Bank 4 enable

This bit enables the chip select counter for PSRAM/NOR Bank 4.

0 : Counter disabled for Bank 4

1: Counter enabled for Bank 4

Bit 18 CNTB3EN: Counter Bank 3 enable

This bit enables the chip select counter for PSRAM/NOR Bank 3.

0 : Counter disabled for Bank 3.

1: Counter enabled for Bank 3

Bit 17 CNTB2EN: Counter Bank 2 enable

This bit enables the chip select counter for PSRAM/NOR Bank 2.

0: Counter disabled for Bank 2

1: Counter enabled for Bank 2

Bit 16 CNTB1EN: Counter Bank 1 enable

This bit enables the chip select counter for PSRAM/NOR Bank 1.

0: Counter disabled for Bank 1

1: Counter enabled for Bank 1

Bits 15:0 CSCOUNT[15:0]: Chip select counter.

This bitfield is used to define the maximum duration of the chip select low, which is obtained by the formula:

CSCOUNT[15:0] *

T_{AHB}

,where

T_{AHB}

is the

AHB

clock period.

For refresh considerations,the PSRAM chip select must not stay low for more than

t_{CEM} =\sim 4 μ s

CSCOUNT[15:0] applies both to asynchronous and synchronous modes.

When CSCOUNT[15:0] = 0x0000, the feature is disabled.

19.7 NAND flash controller

The FMC generates the appropriate signal timings to drive the following types of device:

8- and 16-bit NAND flash memories

The NAND bank is configured through dedicated registers (Section 19.7.7). The programmable memory parameters include access timings (shown in Table 149) and ECC configuration.

Table 149. Programmable NAND flash access parameters

Parameter	Function	Access mode	Unit	Min.	Max.
Memory setup time	Number of clock cycles (HCLK) required to set up the address before the command assertion	Read/Write	AHB clock cycle (HCLK)	1	255
Memory wait	Minimum duration (in HCLK clock cycles) of the command assertion	Read/Write	AHB clock cycle (HCLK)	2	255
Memory hold	Number of clock cycles (HCLK) during which the address must be held (as well as the data if a write access is performed) after the command de-assertion	Read/Write	AHB clock cycle (HCLK)	1	254
Memory databus high-Z	Number of clock cycles (HCLK) during which the data bus is kept in high-Z state after a write access has started	Write	AHB clock cycle (HCLK)	1	255

19.7.1 External memory interface signals

The following tables list the signals that are typically used to interface NAND flash memory.

Note: The prefix "N" identifies the signals which are active low.

8-bit NAND flash memory

Table 150. 8-bit NAND flash

FMC signal name	I/O	Function
A[17]	O	NAND flash address latch enable (ALE) signal
A[16]	O	NAND flash command latch enable (CLE) signa
D[7:0]	I/O	8-bit multiplexed, bidirectional address/data bus
NCE	O	Chip select
NOE(= NRE)	O	Output enable (memory signal name: read enable, NRE)
NWE	O	Write enable
NWAIT/INT	1	NAND flash ready/busy input signal to the FMC

Theoretically, there is no capacity limitation as the FMC can manage as many address cycles as needed.

16-bit NAND flash memory

Table 151. 16-bit NAND flash

FMC signal name	I/O	Function
A[17]	O	NAND flash address latch enable (ALE) signal
A[16]	O	NAND flash command latch enable (CLE) signa
D[15:0]	I/O	16-bit multiplexed, bidirectional address/data bus
NCE	O	Chip select
NOE(= NRE)	O	Output enable (memory signal name: read enable, NRE)
NWE	O	Write enable
NWAIT/INT	1	NAND flash ready/busy input signal to the FMC

Theoretically, there is no capacity limitation as the FMC can manage as many address cycles as needed.

19.7.2 NAND flash supported memories and transactions

Table 152 shows the supported devices, access modes and transactions. Transactions not allowed (or not supported) by the NAND flash controller are shown in gray.

Table 152. Supported memories and transactions

Device	Mode	R/W	AHB data size	Memory data size	Allowed/ not allowed	Comments
NAND 8-bit	Asynchronous	R	8	8	Y	-
	Asynchronous	W	8	8	Y	-
	Asynchronous	R	16	8	Y	Split into 2 FMC accesses
	Asynchronous	W	16	8	Y	Split into 2 FMC accesses
	Asynchronous	R	32	8	Y	Split into 4 FMC accesses
	Asynchronous	w	32	8	Y	Split into 4 FMC accesses
NAND 16-bit	Asynchronous	R	8	16	Y	-
	Asynchronous	W	8	16	N	-
	Asynchronous	R	16	16	Y	-
	Asynchronous	W	16	16	Y	-
	Asynchronous	R	32	16	Y	Split into 2 FMC accesses
	Asynchronous	W	32	16	Y	Split into 2 FMC accesses

19.7.3 Timing diagrams for NAND flash memory

The NAND flash memory bank is managed through a set of registers:

Control register: FMC_PCR

Interrupt status register: FMC_SR

ECC register: FMC_ECCR

Timing register for Common memory space: FMC_PMEM

Timing register for Attribute memory space: FMC_PATT

Each timing configuration register contains three parameters used to define number of HCLK cycles for the three phases of any NAND flash access, plus one parameter that defines the timing for starting driving the data bus when a write access is performed. Figure 72 shows the timing parameter definitions for common memory accesses, knowing that Attribute memory space access timings are similar.

Figure 72. NAND flash controller waveforms for common memory access

NOE remains high (inactive) during write accesses. NWE remains high (inactive) during read accesses.

For write access, the hold phase delay is (MEMHOLD) HCLK cycles and for read access is (MEMHOLD + 2) HCLK cycles.

19.7.4 NAND flash operations

The command latch enable (CLE) and address latch enable (ALE) signals of the NAND flash memory device are driven by address signals from the FMC controller. This means that to send a command or an address to the NAND flash memory, the CPU has to perform a write to a specific address in its memory space.

A typical page read operation from the NAND flash device requires the following steps:

Program and enable the corresponding memory bank by configuring the FMC_PCR and FMC_PMEM (and for some devices, FMC_PATT, see Section 19.7.5: NAND flash prewait functionality) registers according to the characteristics of the NAND flash memory (PWID bits for the data bus width of the NAND flash, PTYP = 1, PWAITEN = 0 or 1 as needed, see Section 19.5.2: NAND flash memory address mapping for timing configuration).

The CPU performs a byte write to the common memory space, with data byte equal to one flash command byte (for example 0x00 for Samsung NAND flash devices). The LE input of the NAND flash memory is active during the write strobe (low pulse on NWE), thus the written byte is interpreted as a command by the NAND flash memory. Once the command is latched by the memory device, it does not need to be written again for the following page read operations.

The CPU can send the start address (STARTAD) for a read operation by writing four bytes (or three for smaller capacity devices), STARTAD[7:0], STARTAD[16:9], STARTAD[24:17] and finally STARTAD[25] (for 64 Mb x 8 bit NAND flash memories) in the common memory or attribute space. The ALE input of the NAND flash device is active during the write strobe (low pulse on NWE), thus the written bytes are interpreted as the start address for read operations. Using the attribute memory space makes it possible to use a different timing configuration of the FMC, which can be used to implement the prewait functionality needed by some NAND flash memories (see details in Section 19.7.5: NAND flash prewait functionality).

The controller waits for the NAND flash memory to be ready (R/NB signal high), before starting a new access to the same or another memory bank. While waiting, the controller holds the NCE signal active (low).

The CPU can then perform byte read operations from the common memory space to read the NAND flash page (data field + Spare field) byte by byte.

The next NAND flash page can be read without any CPU command or address write operation. This can be done in three different ways:

by simply performing the operation described in step 5

a new random address can be accessed by restarting the operation at step 3

a new command can be sent to the NAND flash device by restarting at step 2

19.7.5 NAND flash prewait functionality

Some NAND flash devices require that, after writing the last part of the address, the controller waits for the R/NB signal to go low. (see Figure 73).

Figure 73. Access to non 'CE don't care' NAND-flash

CPU wrote byte 0x00 at address 0x70010000.

CPU wrote byte A7 A0 at address 0x70020000.

CPU wrote byte A16 A9 at address 0x70020000.

CPU wrote byte A24 A17 at address 0x70020000.

CPU wrote byte A25 at address 0x78020000: FMC performs a write access using FMC_PATT timing definition,where ATTHOLD $\geq 7$ (providing that $(7 + 1) \times HCLK = 112 ns > t_{WB}$ max). This guarantees that NCE remains low until R/NB goes low and high again (only requested for NAND flash memories where NCE is not don't care).

When this functionality is required, it can be ensured by programming the MEMHOLD value to meet the

t_{W B}

timing. However any CPU read access to the NAND flash memory has a hold delay of (MEMHOLD + 2) HCLK cycles and CPU write access has a hold delay of (MEMHOLD) HCLK cycles inserted between the rising edge of the NWE signal and the next access.

To cope with this timing constraint, the attribute memory space can be used by programming its timing register with an ATTHOLD value that meets the

t_{WB}

timing,and by keeping the MEMHOLD value at its minimum value. The CPU must then use the common memory space for all NAND flash read and write accesses, except when writing the last address byte to the NAND flash device, where the CPU must write to the attribute memory space.

19.7.6 Computation of the error correction code (ECC) in NAND flash memory

The FMC NAND Card controller includes two error correction code computation hardware blocks, one per memory bank. They reduce the host CPU workload when processing the ECC by software.

These two ECC blocks are identical and associated with Bank 2 and Bank 3. As a consequence, no hardware ECC computation is available for memories connected to Bank 4.

The ECC algorithm implemented in the FMC can perform 1-bit error correction and 2-bit error detection per 256, 512, 1024, 2048, 4096 or 8192 bytes read or written from/to the NAND flash memory. It is based on the Hamming coding algorithm and consists in calculating the row and column parity.

The ECC modules monitor the NAND flash data bus and read/write signals (NCE and NWE) each time the NAND flash memory bank is active.

The ECC operates as follows:

When accessing NAND flash memory bank 2 or bank 3 , the data present on the $D [15 : 0]$ bus is latched and used for ECC computation.

When accessing any other address in NAND flash memory, the ECC logic is idle, and does not perform any operation. As a result, write operations to define commands or addresses to the NAND flash memory are not taken into account for ECC computation.

Once the desired number of bytes has been read/written from/to the NAND flash memory by the host CPU, the FMC_ECCR registers must be read to retrieve the computed value. Once read, they must be cleared by resetting the ECCEN bit to ' 0 '. To compute a new data block, the ECCEN bit must be set to one in the FMC_PCR registers.

To perform an ECC computation:

Enable the ECCEN bit in the FMC_PCR register.

Write data to the NAND flash memory page. While the NAND page is written, the ECC block computes the ECC value.

Read the ECC value available in the FMC_ECCR register and store it in a variable.

Clear the ECCEN bit and then enable it in the FMC_PCR register before reading back the written data from the NAND page. While the NAND page is read, the ECC block computes the ECC value.

Read the new ECC value available in the FMC_ECCR register.

If the two ECC values are the same, no correction is required, otherwise there is an ECC error and the software correction routine returns information on whether the error can be corrected or not.

19.7.7 NAND flash controller registers

NAND flash control registers (FMC_PCR)

Address offset: 0x80

Reset value: 0x0000 0018

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	ECCPS[2:0]			TAR3
												rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TAR[2:0]			TCLR[3:0]				Res.	Res.	ECCEN	PWID[1:0]		PTYP	PBKEN	PWAITEN	Res.
rw	rw	rw	rw	rw	rw	rw			rw	rw	rw	rw	rw	rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:17 ECCPS[2:0]: ECC page size

Defines the page size for the extended ECC:

000: 256 bytes

001: 512 bytes

010: 1024 bytes

011: 2048 bytes

100: 4096 bytes

101: 8192 bytes

Bits 16:13 TAR[3:0]: ALE to RE delay

Sets time from ALE low to RE low in number of AHB clock cycles (HCLK).

Time is:

t_a r = (T A R + S E T + 2) \times T H C L K

where THCLK is the HCLK clock period

0000: 1 HCLK cycle (default)

1111: 16 HCLK cycles

Note: SET is MEMSET or ATTSET according to the addressed space.

Bits 12:9 TCLR[3:0]: CLE to RE delay

Sets time from CLE low to RE low in number of AHB clock cycles (HCLK).

Time is

t_c l r = (T C L R + S E T + 2) \times T H C L K

where THCLK is the HCLK clock period

0000: 1 HCLK cycle (default)

1111: 16 HCLK cycles

Note: SET is MEMSET or ATTSET according to the addressed space.

Bits 8:7 Reserved, must be kept at reset value.

Bit 6 ECCEN: ECC computation logic enable bit

0: ECC logic is disabled and reset (default after reset),

1: ECC logic is enabled.

Bits 5:4 PWID[1:0]: Data bus width

Defines the external memory device width.

00: 8 bits

01: 16 bits (default after reset).

10: reserved.

11: reserved.

Bit 3 PTYP: Memory type

Defines the type of device attached to the corresponding memory bank:

0 : Reserved, must be kept at reset value

1: NAND flash (default after reset)

Bit 2 PBKEN: NAND flash memory bank enable bit

Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB

bus

0: Corresponding memory bank is disabled (default after reset)

1: Corresponding memory bank is enabled

Bit 1 PWAITEN: Wait feature enable bit

Enables the Wait feature for the NAND flash memory bank:

0: disabled

1: enabled

Bit 0 Reserved, must be kept at reset value.

FIFO status and interrupt register (FMC_SR)

Address offset: 0x84

Reset value: 0x00000040

This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data from the AHB.

This is used to quickly write to the FIFO and free the AHB for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.

The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	FEMPT	IFEN	ILEN	IREN	IFS	ILS	IRS
									r	rw	rw	rw	rw	rw	rw

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 FEMPT: FIFO empty

Read-only bit that provides the status of the FIFO

0 : FIFO not empty

1: FIFO empty

Bit 5 IFEN: Interrupt falling edge detection enable bit

0: Interrupt falling edge detection request disabled

1: Interrupt falling edge detection request enabled

Bit 4 ILEN: Interrupt high-level detection enable bit

0: Interrupt high-level detection request disabled

1: Interrupt high-level detection request enabled

Bit 3 IREN: Interrupt rising edge detection enable bit

0: Interrupt rising edge detection request disabled

1: Interrupt rising edge detection request enabled

Bit 2 IFS: Interrupt falling edge status

The flag is set by hardware and reset by software.

0 : No interrupt falling edge occurred

1: Interrupt falling edge occurred

Note: If this bit is written by software to 1 it is set.

Bit 1 ILS: Interrupt high-level status

The flag is set by hardware and reset by software.

0 : No Interrupt high-level occurred

1: Interrupt high-level occurred

Bit 0 IRS: Interrupt rising edge status

The flag is set by hardware and reset by software.

0 : No interrupt rising edge occurred

1: Interrupt rising edge occurred

Note: If this bit is written by software to 1 it is set.

Common memory space timing register (FMC_PMEM)

Address offset: 0x88

Reset value: 0xFCFC FCFC

The FMC_PMEM read/write register contains the timing information for NAND flash memory bank. This information is used to access either the common memory space of the NAND flash for command, address write access and data read/write access.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MEMHIZ[7:0]								MEMHOLD[7:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MEMWAIT(7:0)								MEMSET[7:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:24 MEMHIZ[7:0]: Common memory x data bus Hi-Z time

Defines the number of HCLK clock cycles during which the data bus is kept Hi-Z after the start of a NAND flash write access to common memory space on socket. This is only valid for write transactions:

00000000: 1 HCLK cycle

1111 1110: 255 HCLK cycles

1111 1111: reserved.

Bits 23:16 MEMHOLD[7:0]: Common memory hold time

Defines the number of HCLK clock cycles for write access and HCLK (+2) clock cycles for read access during which the address is held (and data for write accesses) after the command is deasserted (NWE, NOE), for NAND flash read or write access to common memory space on socket

x

00000000: reserved.

00000001: 1 HCLK cycle for write access / 3 HCLK cycles for read access

11111110: 254 HCLK cycles for write access / 256 HCLK cycles for read access

1111 1111: reserved.

Bits 15:8 MEMWAIT[7:0]: Common memory wait time

Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, NOE), for NAND flash read or write access to common memory space on socket. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of HCLK:

00000000: reserved

00000001: 2HCLK cycles (+ wait cycle introduced by deasserting NWAIT)

1111 1110: 255 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)

11111111: reserved.

Bits 7:0 MEMSET[7:0]: Common memory x setup time

Defines the number of HCLK (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for NAND flash read or write access to common memory space on socket

x

00000000: 1 HCLK cycle

11111110: 255 HCLK cycles

1111 1111: reserved

Attribute memory space timing register (FMC_PATT)

Address offset: 0x8C

Reset value: 0xFCFC FCFC

The FMC_PATT read/write register contains the timing information for NAND flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section 19.7.5: NAND flash prewait functionality).

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ATTHIZ[7:0]								ATTHOLD[7:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ATTWAIT[7:0]								ATTSET[7:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:24 ATTHIZ[7:0]: Attribute memory data bus Hi-Z time

Defines the number of HCLK clock cycles during which the data bus is kept in Hi-Z after the start of a NAND flash write access to attribute memory space on socket. Only valid for writ transaction:

00000000: 0 HCLK cycle

1111 1110: 255 HCLK cycles

1111 1111: reserved.

Bits 23:16 ATTHOLD[7:0]: Attribute memory hold time

Defines the number of HCLK clock cycles for write access and HCLK (+2) clock cycles for read access during which the address is held (and data for write access) after the command deassertion (NWE, NOE), for NAND flash read or write access to attribute memory space on socket:

00000000: reserved

00000001: 1 HCLK cycle for write access / 3 HCLK cycles for read access

11111110: 254 HCLK cycles for write access / 256 HCLK cycles for read access

11111111: reserved.

Bits 15:8 ATTWAIT[7:0]: Attribute memory wait time

Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,

NOE),for NAND flash read or write access to attribute memory space on socket

x

. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of HCLK:

00000000: reserved

00000001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)

11111110: 255 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)

11111111: reserved.

Bits 7:0 ATTSET[7:0]: Attribute memory setup time

Defines the number of HCLK (+1) clock cycles to set up address before the command assertion (NWE, NOE), for NAND flash read or write access to attribute memory space on socket:

00000000: 1 HCLK cycle

1111 1110: 255 HCLK cycles

1111 1111: reserved.

ECC result registers (FMC_ECCR)

Address offset: 0x94

Reset value: 0x00000000

This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads the data from a NAND flash memory page at the correct address (refer to Section 19.7.6: Computation of the error correction code (ECC) in NAND flash memory), the data read/written from/to the NAND flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register must be cleared after being read by setting the ECCEN bit to 0 . To compute a new data block, the ECCEN bit must be set to 1 .

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ECC[31:16]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ECC[15:0]
$r$	r	r	$r$	$r$	r	r	$r$	$r$	$r$	r	$r$	r	$r$	r	$r$

Bits 31:0 ECC[31:0]: ECC result

This field contains the value computed by the ECC computation logic. Table 153 describes the contents of these bitfields.

Table 153. ECC result relevant bits

ECCPS[2:0]	Page size in bytes	ECC bits
000	256	ECC[21:0]
001	512	ECC[23:0]
010	1024	ECC[25:0]
011	2048	ECC[27:0]
100	4096	ECC[29:0]
101	8192	ECC[31:0]

19.7.8 FMC register map

Table 154. FMC register map and reset values

Offset	Register name reset value	31	30	23	28	2726	25	24	232221	20	1.9	1.8仍伯	伯1413	121110	9	007	54	321	0
0x00	FMC_BCR1	B	8	y)	SHE	时LIS	小时		[1:0]NBLSETSIGHM	NEPPROO	MYLLSYNGO	CPSIZE [2:0]	LIVMON人SYaowix3NELIVM	Why 12 (1)9.10.11VM	70d1IVM	NELLSYNANEOOVE	MWID [1:0]	MTYP[1:0]NEXNW	NEWAW
0x00	Reset value								000	0		00	01	10	0	0	01	101	1
0x08	FMC_BCR2	8	3	(1)	1.00	SSTA	好	新市	NBL SET [1:0]	CONDER	MYLLSYNGO	CPSIZE [2:0]	LIVMON人SYCOWLX3NELIVM	Why 129.10.1.1VM	70d1IVM	NELLSYNA	MWID [1:0]	MTYP[1:0]NEXNW	NEWSW
0x08	Reset value								00			│ 0│ 0	01	10	0	0	01	001	0
0x10	FMC_BCR3	8	13	COM	33	BUD3	S	a	NBL [1:0]SETa	g	Malisango	CPSIZE [2:0]	LIVMON人SVCOWLX3NELIVM	N38M9.10.1.1VM	70dJIVM	NELLSYNANEJOVE	MWID [1:0]	MTYP[1:0]NEXNW	N3X8W
0x10	Reset value								00		0	│ 0│ 0	01	10	0	0	01	001	0
0x18	FMC_BCR4		B	3	8	3SHOP	3	8	NBL SET [1:0]		MYLLSYNAO	CPSIZE [2:0]	LIVMONASYCOW1X3NELIVM	Why 129.10.1.1VM	70d1IVM	NELLSYNA	MWID [1:0]	MTYP[1:0]N3XΛW	NEXISW
0x18	Reset value								00		000 \|0		001	10	0	0	01	001	0
0x04	FMC_BTR1	[0:1] CTHVIVI		[0:1] goweov		DATLAT[3:0]			CLKDIV[3:0]		BUSTURN [3:0]		DATAST[7:0]				ADDHLD[3:0]	ADDSET[3:0]
0x04	Reset value	0	0	0	0	11 \| 11			1111		111		111111111				11	1111
0x0C	FMC_BTR2	[0:1] CTHVIVA		[0:1] gowo v		DATLAT[3:0]			CLKDIV[3:0]		BUSTURN [3:0]		DATAST[7:0]				ADDHLD[3:0]	ADDSET[3:0]
0x0C	Reset value	0	0	0	0	11 \| 1 \|			11		1	111	111111111				11	1111
0x14	FMC_BTR3	[0:1] an HVIV a		[0:1] do wow		DATLAT[3:0]			CLKDIV[3:0]		BUSTURN [3:0]		DATAST[7:0]				ADDHLD[3:0]	ADDSET[3:0]
0x14	Reset value	0	0	0	0	11	1	1	111	1	1	111	111111111				11	111	1
0x1C	FMC_BTR4	[0:1]CTHV1VC		[0:1] gowest		DATLAT[3:0]			CLKDIV[3:0]			BUSTURN [3:0]	DATAST[7:0]				ADDHLD[3:0]	ADDSET[3:0]
0x1C	Reset value	0	0	0	0	11	1	1	111	1	1	111	111111111				11	111	1
0x20	FMC PCSCNTR	e	8	9	品	3的	的	留	de3		Ｎ３ｔ８１ＮＯ	NELLNON379.1N0NE181N0	CSCOUNT[15:0]
0x20	Reset value										0	00	000	000	0	00	00	000	0
0x104	FMC_BWTR1	[O': 1]CTHV1VC		[0:1] goweov		LetBUB	y y	时间	新时间Let	5,549		BUSTURN [3:0]	DATAST[7:0]				ADDHLD[3:0]	ADDSET[3:0]
0x104	Reset value	0	0	0	0						1	111	111	111	1	11	11	111	1

Table 154. FMC register map and reset values (continued)

Offset	Register name reset value	31	30	23	28	27	26	25	24	23	22	21	2022	1.91.8	17伯	1614	13	1211	109	8	76	54	32	1	O
0x10C	FMC_BWTR2	[0:1]		[0:1] above over		Light	3	3	3	LOUR	：	CHE	STRAND	BUSTURN [3:0]		DATAST[7:0]					ADDHLD[3:0]		ADDSET[3:0]
0x10C	Reset value	0	0	0	0									11	11	11	1	11	11	1	11	11	11	1	1
0x114	FMC_BWTR3	[0:1] CTHVIVA		[0:1] do work		y	3	Mat	3	新鲜	3	y	:	BUSTURN [3:0]		DATAST[7:0]					ADDHLD[3:0]		ADDSET[3:0]
0x114	Reset value	0	0	0	0									11	11	11	1	11	11	1	11	11	11	1	1
0x11C	FMC_BWTR4	[0:1]		：1] COWOOV		3	3	路	13	路	S	RAND	3	BUSTURN [3:0]		DATAST[7:0]					ADDHLD[3:0]		ADDSET[3:0]
0x11C	Reset value	0	0	0	0									11	11	11	1	11	11	1	11	11	11	1	1
0x80	FMC_PCR		3	ig	13	3	3	S	y	3	3	y	3	ECCPS [2:0]		TAR[3:0]		TCLR[3:0]		3	:N3003	PWID [1:0]	Problem 2Pre-20	NELIVMd	3
0x80	Reset value													00	00	00	0	00	00		0	01	10	0
0x84	FMC_SR				BUR	Let			BUR	Let	13.00%		si	中心g	siB	SupposeLet		Let	For		STA1dW3-	止日出2022	HK$’000III.	HK$’00	HK$’00
0x84	Reset value																				1	00	00	0	0
0x88	FMC PMEM	MEMHIZx[7:0]								MEMHOLDx[7:0						MEMWAITx[7:0]					MEMSETx[7:0]
0x88	Reset value	1	1	1	1	1	1	0	0	1	1	1	1	11	00	11	1	11	10	0	11	11	11	0	0
0x8C	FMC_PATT	ATTHIZ[7:0]								ATTHOLD[7:0]						ATTWAIT[7:0]					ATTSET[7:0]
0x8C	Reset value	1	1	1	1	1	1	0	0	1	1	1	1	11	00	11	1	11	10	0	11	11	11	0	0
0x94	FMC ECCR	ECCx[31:0]
0x94	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	00	00	00	0	00	00	0	00	00	00	0	0

Refer to Section 2.2 on page 81 for the register boundary addresses.

20 Quad-SPI interface (QUADSPI)

20.1 Introduction

The QUADSPI is a specialized communication interface targeting single, dual- or quad-SPI flash memories. It can operate in any of the three following modes:

indirect mode: all the operations are performed using the QUADSPI registers.

automatic status-polling mode: the external flash memory status register is periodically read and an interrupt can be generated in case of flag setting.

memory-mapped mode: the external flash memory is mapped to the device address space and is seen by the system as if it was an internal memory.

Both throughput and capacity can be increased two-fold using dual-flash mode, where two Quad-SPI flash memories are accessed simultaneously.

20.2 QUADSPI main features

Three functional modes: indirect, automatic status-polling, and memory-mapped

Dual-flash mode, where 8 bits can be sent/received simultaneously by accessing two flash memories in parallel

SDR and DDR support

Fully programmable opcode for both indirect and memory-mapped modes

Fully programmable frame format for both indirect and memory-mapped modes

Integrated FIFO for reception and transmission

8-, 16-, and 32-bit data accesses allowed

DMA channel for indirect mode operations

Interrupt generation on FIFO threshold, timeout, operation complete, and access error

20.3 QUADSPI functional description

20.3.1 QUADSPI block diagram

20.3.2 QUADSPI pins

The table below lists the QUADSPI pins, six for interfacing with a single flash memory, or 10 to 11 for interfacing with two flash memories (FLASH 1 and FLASH 2) in dual-flash mode.

Table 155. QUADSPI pins

Signal name	Signal type	Description
CLK	Digital output	Clock to FLASH 1 and FLASH 2
BK1_IO0/SO	Digital input/output	Bidirectional I/O in dual/quad modes or serial output in single mode, for FLASH 1
BK1_IO1/SI	Digital input/output	Bidirectional I/O in dual/quad modes or serial input in single mode, for FLASH 1
BK1_IO2	Digital input/output	Bidirectional I/O in quad mode, for FLASH 1
BK1_IO3	Digital input/output	Bidirectional I/O in quad mode, for FLASH 1
BK2_IO0/SO	Digital input/output	Bidirectional I/O in dual/quad modes or serial output in single mode, for FLASH 2
BK2_IO1/SI	Digital input/output	Bidirectional I/O in dual/quad modes or serial input in single mode, for FLASH 2
BK2_IO2	Digital input/output	Bidirectional I/O in quad mode, for FLASH 2
BK2_IO3	Digital input/output	Bidirectional I/O in quad mode, for FLASH 2
BK1_NCS	Digital output	Chip select (active low) for FLASH 1. Can also be used for FLASH 2 if QUADSP is always used in dual-flash mode.
BK2_NCS	Digital output	Chip select (active low) for FLASH 2. Can also be used for FLASH 1 if QUADSPI is always used in dual-flash mode.

20.3.3 QUADSPI command sequence

The QUADSPI communicates with the flash memory using commands. Each command can include five phases: instruction, address, alternate byte, dummy, data. Any of these phases can be configured to be skipped, but at least one of the instruction, address, alternate byte, or data phase must be present.

NCS falls before the start of each command and rises again after each command finishes.

Figure 76. Example of read command in quad-SPI mode

Instruction phase

During this phase, an 8-bit instruction, configured in INSTRUCTION bitfield of

QUADSPI_CCR[7:0] register, is sent to the flash memory, specifying the type of operation to be performed.

Most flash memories can receive instructions only one bit at a time from the IO0/SO signal (single-SPI mode), the instruction phase can optionally send 2 bits at a time (over IO0/IO1 in dual-SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad-SPI mode). This can be configured using the IMODE[1:0] bitfield of QUADSPI_CCR[9:8] register.

When IMODE = 00 , the instruction phase is skipped, and the command sequence starts with the address phase, if present.

Address phase

In the address phase, 1-4 bytes are sent to the flash memory to indicate the address of the operation. The number of address bytes to be sent is configured in the ADSIZE[1:0] bitfield of QUADSPI_CCR[13:12] register. In indirect and automatic status-polling modes, address bytes to be sent are specified in the ADDRESS[31:0] bitfield of QUADSPI_AR register, while in memory-mapped mode, the address is given directly via the AHB (from the Cortex or from a DMA).

The address phase can send 1 bit at a time (over SO in single-SPI mode), 2 bits at a time (over IO0/IO1 in dual-SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad-SPI mode). This can be configured using the ADMODE[1:0] bitfield of QUADSPI_CCR[11:10] register.

When ADMODE

= 00

,the address phase is skipped,and the command sequence proceeds directly to the next phase, if any.

Alternate-byte phase

In the alternate-byte phase, 1-4 bytes are sent to the flash memory, generally to control the mode of operation. The number of alternate bytes to be sent is configured in the [1:0] bitfield of QUADSPI_CCR[17:16] register. The bytes to be sent are specified in the QUADSPI_ABR register.

The alternate-bytes phase can send 1 bit at a time (over SO in single-SPI mode), 2 bits at a time (over IO0/IO1 in dual-SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad-SPI mode). This can be configured using the ABMODE[1:0] bitfield of QUADSPI_CCR[15:14] register.

When ABMODE

= 00

,the alternate-byte phase is skipped,and the command sequence proceeds directly to the next phase, if any.

There may be times when only a single nibble needs to be sent during the alternate-byte phase rather than a full byte, such as when the dual-mode is used and only two cycles are used for the alternate bytes. In this case,the firmware can use quad-mode (ABMODE = 11) and send a byte with bits 7 and 3 of ALTERNATE set to 1 (keeping the IO3 line high), and bits 6 and 2 set to 0 (keeping the IO2 line low). In this case, the upper two bits of the nibble to be sent are placed in bits 4:3 of ALTERNATE, while the lower two bits are placed in bits 1 and 0 . For example, if the nibble 2 (0010) is to be sent over IO0/IO1, then ALTERNATE must be set to 0x8A (1000_1010).

Dummy-cycle phase

In the dummy-cycle phase, 1-31 cycles are given without any data being sent or received, in order to give time to the flash memory to prepare for the data phase when higher clock frequencies are used. The number of cycles given during this phase is specified in the DCYC[4:0] bitfield of QUADSPI_CCR[22:18] register. In both SDR and DDR modes, the duration is specified as a number of full CLK cycles.

When DCYC is zero, the dummy-cycles phase is skipped, and the command sequence proceeds directly to the data phase, if present.

The operating mode of the dummy-cycles phase is determined by DMODE.

In order to assure enough "turn-around" time for changing data signals from output mode to input mode, there must be at least one dummy cycle when using dual or quad mode to receive data from the flash memory.

Data phase

During the data phase, any number of bytes can be sent to, or received from the flash memory.

In indirect and automatic status-polling modes, the number of bytes to be sent/received is specified in the QUADSPI_DLR register.

In indirect-write mode the data to be sent to the flash memory must be written to the QUADSPI_DR register. In indirect-read mode the data received from the flash memory is obtained by reading the QUADSPI_DR register.

In memory-mapped mode, the data which is read is sent back directly over the AHB to the Cortex or to a DMA.

The data phase can send/receive 1 bit at a time (over SO/SI in single-SPI mode), 2 bits at a time (over IO0/IO1 in dual-SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad-SPI mode). This can be configured using the ABMODE[1:0] bitfield of QUADSPI_CCR[15:14] register.

When DMODE

= 00

,the data phase is skipped,and the command sequence finishes immediately by raising NCS. This configuration must only be used in only indirect write mode.

20.3.4 QUADSPI signal interface protocol modes

Single-SPI mode

This legacy SPI mode allows just one single bit to be sent/received serially. In this mode, data are sent to the flash memory over the SO signal (whose I/O shared with IO0). Data received from the flash memory arrive via SI (whose I/O shared with IO1).

The different phases can each be configured separately to use this mode by setting the IMODE/ADMODE/ABMODE/DMODE fields (in QUADSPI_CCR) to 01.

In each phase which is configured in single-SPI mode:

IO0 (SO) is in output mode.

IO1 (SI) is in input mode (high impedance).

IO2 is in output mode and forced to 0 .

IO3 is in output mode and forced to 1 (to deactivate the "hold" function).

This is the case even for the dummy phase if DMODE = 01.

Dual-SPI mode

In dual-SPI mode, two bits are sent/received simultaneously over the IO0/IO1 signals.

The different phases can each be configured separately to use dual-SPI mode by setting the IMODE/ADMODE/ABMODE/DMODE fields of QUADSPI_CCR register to 10.

In each phase which is configured in dual-SPI mode:

IO0/IO1 are at high-impedance (input) during the data phase for read operations, and outputs in all other cases.

IO2 is in output mode and forced to 0 .

IO3 is in output mode and forced to 1 .

In the dummy phase when DMODE = 01, IO0/IO1 are always high-impedance.

Quad-SPI mode

In quad-SPI mode, four bits are sent/received simultaneously over the IO0/IO1/IO2/IO3 signals.

The different phases can each be configured separately to use quad-SPI mode by setting the IMODE/ADMODE/ABMODE/DMODE fields of QUADSPI_CCR register to 11.

In each phase which is configured in this mode, IO0/IO1/IO2/IO3 are all are at high-impedance (input) during the data phase for read operations, and outputs in all other cases.

In the dummy phase when DMODE = 11, IO0/IO1/IO2/IO3 are all high-impedance.

IO2 and IO3 are used only in quad-SPI mode. If none of the phases are configured to use quad-SPI mode, then the pins corresponding to IO2 and IO3 can be used for other functions even while the QUADSPI is active.

SDR mode

By default, the DDRM bit (QUADSPI_CCR[31]) is 0 and the QUADSPI operates in single-data rate (SDR) mode.

In SDR mode, when the QUADSPI drives IO0/SO, IO1, IO2, IO3 signals, these signals transition only with the falling edge of CLK.

When receiving data in SDR mode, the QUADSPI assumes that flash memories also send the data using CLK falling edge. By default (when SSHIFT = 0), the signals are sampled using the following (rising) edge of CLK.

DDR mode

When the DDRM bit (QUADSPI_CCR[31]) is set to 1, the QUADSPI operates in double-data rate (DDR) mode.

In DDR mode, when the QUADSPI is driving the IO0/SO, IO1, IO2, IO3 signals in the address/alternate-byte/data phases, a bit is sent on each of CLK falling and rising edges.

The instruction phase is not affected by DDRM. The instruction is always sent using CLK falling edge.

When receiving data in DDR mode, the QUADSPI assumes that flash memories also send the data using both CLK rising and falling edges. When DDRM

= 1

,the firmware must clear SSHIFT (bit 4 of QUADSPI_CR). Thus, the signals are sampled one half of a CLK cycle later (on the following, opposite edge).

Figure 77. Example of a DDR command in quad-SPI mode

MS35318V2

Dual-flash mode

When the DFM bit (bit 6 of QUADSPI_CR) is 1, the QUADSPI is in dual-flash mode, where two external quad-SPI flash memories (FLASH 1 and FLASH 2) are used in order to send/receive 8 bits (or 16 bits in DDR mode) every cycle, effectively doubling the throughput as well as the capacity.

Each of the flash memories uses the same CLK and optionally the same NCS signals, but each have separate

100, 101, 102

,and 103 signals.

The dual-flash mode can be used in conjunction with single-, dual-, and quad-SPI modes, as well as with either SDR or DDR mode.

The flash memory size, as specified in FSIZE[4:0] (QUADSPI_DCR[20:16]), must reflect the total flash memory capacity, which is double the size of one individual component.

If address

X

is even,then the byte which the QUADSPI gives for address

X

is the byte at the address X/2 of FLASH 1, and the byte which the QUADSPI gives for address X+1 is the byte at the address

X / 2

of FLASH 2. In other words,bytes at even addresses are all stored in FLASH 1 and bytes at odd addresses are all stored in FLASH 2. When reading the flash memories status registers in dual-flash mode, twice as many bytes must be read compared to doing the same read in single-flash mode. This means that if each flash memory gives 8 valid bits after the instruction for fetching the status register, then the QUADSPI must be configured with a data length of 2 bytes (16 bits), and the QUADSPI receives one byte from each flash memory. If each flash memory gives a status of 16 bits, then the QUADSPI must be configured to read 4 bytes to get all the status bits of both flash memories in dual-flash mode. The least-significant byte of the result (in the data register) is the least-significant byte of FLASH 1 status register, while the next byte is the least-significant byte of FLASH 2 status register. Then, the third byte of the data register is FLASH 1 second byte, while the forth byte is FLASH 2 second byte (in the case that the flash memories have 16-bit status registers).

An even number of bytes must always be accessed in dual-flash mode. For this reason, bit 0 of the data length bitfield (QUADSPI_DLR[0]) is stuck at 1 when DFM = 1 .

In dual-flash mode, the behavior of FLASH 1 interface signals are basically the same as in normal mode. FLASH 2 interface signals have exactly the same waveforms as FLASH 1 during the instruction, address, alternate-byte, and dummy-cycles phases. In other words, each flash memory always receives the same instruction and the same address. Then, during the data phase,the

BK 1_IOx

and

BK 2_IOx

buses are both transferring data in parallel, but the data that are sent to (or received from) FLASH 1 are distinct from those of FLASH 2.

20.3.5 QUADSPI indirect mode

When in indirect mode, commands are started by writing to QUADSPI registers, and data are transferred by writing or reading the data register, in the same way as for other communication peripherals.

When FMODE = 00 (QUADSPI_CCR[27:26]), the QUADSPI is in indirect-write mode, where bytes are sent to the flash memory during the data phase. Data are provided by writing to the data register (QUADSPI_DR).

When FMODE = 01, the QUADSPI is in indirect-read mode, where bytes are received from the flash memory during the data phase. Data are recovered by reading QUADSPI_DR.

The number of bytes to be read/written is specified in the data length register (QUADSPI_DLR). If QUADSPI_DLR = 0xFFFF_FFFF (all 1s), then the data length is considered undefined and the QUADSPI simply continues to transfer data until the end of flash memory (as defined by FSIZE) is reached. If no bytes are to be transferred, DMODE (QUADSPI_CCR[25:24]) must be set to 00.

If QUADSPI_DLR = 0xFFFF_FFFF and FSIZE = 0x1F (max value indicating a 4-Gbyte flash memory), then in this special case, transfers continue indefinitely, stopping only after an abort request or after the QUADSPI is disabled. After the last memory address is read (at address 0xFFFF_FFFF), reading continues with address = 0x0000_0000.

When the programmed number of bytes to be transmitted or received is reached, TCF is set and an interrupt is generated if TCIE = 1 . In the case of undefined number of data, the TCF is set when the limit of the external SPI memory is reached according to the flash memory size defined in QUADSPI_CR.

Triggering the start of a command

Essentially, a command starts as soon as firmware gives the last information that is necessary for this command. Depending on the QUADSPI configuration, there are three different ways to trigger the start of a command in indirect mode. The commands starts immediately:

after a write is performed to INSTRUCTION[7:0] (QUADSPI_CCR), if no address is necessary (when ADMODE = 00) and if no data needs to be provided by the firmware (when FMODE $= 01$ or DMODE $= 00$ )

after a write is performed to ADDRESS[31:0] (QUADSPI_AR), if an address is necessary (when ADMODE $\neq 00$ ) and if no data needs to be provided by the firmware (when FMODE $= 01$ or DMODE $= 00$ )

after a write is performed to DATA[31:0] (QUADSPI_DR), if data needs to be provided by the firmware (when FMODE $= 00$ and DMODE $! = 00$ )

Writes to the alternate byte register (QUADSPI_ABR) never trigger the communication start. If alternate bytes are required, they must be programmed before.

As soon as a command is started, BUSY (bit 5 of QUADSPI_SR) is automatically set.

FIFO and data management

In indirect mode, data go through a 16-byte FIFO which is internal to the QUADSPI. FLEVEL[4:0] (QUADSPI_SR[12:8]) indicates how many bytes are currently being held in the FIFO.

In indirect-write mode (FMODE = 00), the firmware adds data to the FIFO when it writes QUADSPI_DR. Word writes add 4 bytes to the FIFO, halfword writes add 2 bytes, and byte writes add only 1 byte. If the firmware adds too many bytes to the FIFO (more than is indicated by DL[31:0]), the extra bytes are flushed from the FIFO at the end of the write operation (when TCF is set).

Byte/halfword accesses to QUADSPI_DR must be done only to the least significant byte/halfword of the 32-bit register.

FTHRES[3:0] is used to define a FIFO threshold. When the threshold is reached, FTF (FIFO threshold flag) is set. In indirect-read mode, FTF is set when the number of valid bytes to be read from the FIFO is above the threshold. FTF is also set if there are data in the FIFO after the last byte is read from the flash memory, regardless of the FTHRES setting. In indirect-write mode, FTF is set when the number of empty bytes in the FIFO is above the threshold.

If FTIE

= 1

,there is an interrupt when FTF is set. If DMAEN

= 1

,a DMA transfer is initiated when FTF is set. FTF is cleared by hardware as soon as the threshold condition is no longer true (after enough data is transferred by the CPU or DMA).

20.3.6 QUADSPI automatic status-polling mode

In automatic status-polling mode, the QUADSPI periodically starts a command to read a defined number of status bytes (up to 4). The received bytes can be masked to isolate some status bits and an interrupt can be generated when the selected bits have a defined value.

Accesses to the flash memory begin in the same way as in indirect-read mode: if no address is required (AMODE = 00), accesses begin as soon as the QUADSPI_CCR is written.

Otherwise, if an address is required, the first access begins when QUADSPI_AR is written. BUSY goes high at this point and stays high even between the periodic accesses.

The contents of MASK[31:0] (QUADSPI_PSMAR) are used to mask the data from the flash memory in automatic status-polling mode. If

MASK [n] = 0

,then bit

n

of the result is masked and not considered. If

MASK [n] = 1

,and the content of bit

[n]

is the same as

MATCH [n]

(QUADSPI_PSMAR), then there is a match for bit n.

If the polling match mode bit (PMM, bit 23 of QUADSPI_CR) is 0, then "AND" match mode is activated. This means status match flag (SMF) is set only when there is a match on all of the unmasked bits.

If PMM = 1, then "OR" match mode is activated. This means SMF is set if there is a match on any of the unmasked bits.

An interrupt is called when SMF is set if SMIE = 1.

If the automatic status-polling mode stop (APMS) bit is set, the operation stops and BUSY goes to 0 as soon as a match is detected. Otherwise, BUSY stays at 1 , and the periodic accesses continue until there is an abort or the QUADSPI is disabled

(EN = 0)

The data register (QUADSPI_DR) contains the latest received status bytes (the FIFO is deactivated). The content of the data register is not affected by the masking used in the matching logic. The FTF status bit is set as soon as a new reading of the status is complete, and FTF is cleared as soon as the data is read.

20.3.7 QUADSPI memory-mapped mode

When configured in memory-mapped mode, the external SPI device is seen as an internal memory.

It is forbidden to access the quad-SPI flash bank area before having properly configured and enabled the QUADSPI peripheral.

No more than 256 Mbytes can addressed even if the flash memory capacity is larger.

If an access is made to an address outside of the range defined by FSIZE but still within the 256-Mbyte range, then a bus error is given. The effect of this error depends on the bus master that attempted the access:

If it is the Cortex CPU, bus fault exception is generated when enabled (or an HardFault exception when bus fault is disabled).

If it is a DMA, a DMA transfer error is generated and the corresponding DMA channel is automatically disabled.

Byte, halfword, and word access types are all supported.

Support for execute in place (XIP) operation is implemented, where the QUADSPI anticipates the next access and load in advance the byte at the following address. If the subsequent access is indeed made at a continuous address, the access is completed faster since the value is already prefetched.

the application may want to activate the timeout counter (TCEN = 1, bit 3 of QUADSPI_CR) so that NCS is released after a period of TIMEOUT[15:0] (QUADSPI_LPTR) cycles have elapsed without any access since when the FIFO becomes full with prefetch data. BUSY goes high as soon as the first memory-mapped access occurs. Because of the prefetch operations, BUSY does not fall until there is a timeout, there is an abort, or the peripheral is disabled.

20.3.8 QUADSPI flash memory configuration

The device configuration register (QUADSPI_DCR) can be used to specify the characteristics of the external SPI flash memory.

The FSIZE[4:0] bitfield defines the size of external memory using the following formula:

Number of bytes in flash memory

= 2^{[FSIZE + 1]}

FSIZE+1 is effectively the number of address bits required to address the flash memory. The flash memory capacity can be up to 4 Gbytes (addressed using 32 bits) in indirect mode, but the addressable space in memory-mapped mode is limited to 256 Mbytes.

If DFM = 1, FSIZE indicates the total capacity of the two flash memories together.

When the QUADSPI executes two commands, one immediately after the other, it raises NCS high between the two commands for only one CLK cycle by default. If the flash memory requires more time between commands, the CSHT biffield can be used to specify the minimum number of CLK cycles (up to 8) that NCS must remain high.

The clock mode (CKMODE) bit indicates the CLK signal logic level in between commands (when NCS = 1).

20.3.9 QUADSPI delayed data sampling

By default, the QUADSPI samples the data driven by the flash memory one half of a CLK cycle after the flash memory drives the signal.

In case of external signal delays, it may be beneficial to sample the data later. Using SSHIFT (bit 4 of QUADSPI_CR), the sampling of the data can be shifted by half of a CLK cycle.

Clock shifting is not supported in DDR mode: SSHIFT must be clear when DDRM bit is set.

20.3.10 QUADSPI configuration

The QUADSPI configuration is done in two phases:

QUADSPI peripheral configuration

QUADSPI flash memory configuration

Once configured and enabled, the QUADSPI can be used in one of its three operating modes: indirect, automatic status-polling, or memory-mapped mode.

QUADSPI configuration

The QUADSPI is configured using QUADSPI_CR. The user must configure the clock prescaler division factor and the sample shifting settings for the incoming data.

The DDR mode can be set through the DDRM bit. When setting the quad-SPI interface in DDR mode, the internal divider of kernel clock must be set with a division ratio of two or more. Once enabled, the address and the alternate bytes are sent on both clock edges, and the data are sent/received on both clock edges. Regardless of the DDRM bit setting, instructions are always sent in SDR mode.

DMA requests are enabled setting the DMAEN bit. In case of interrupt usage, their respective enable bit can be also set during this phase.

The FIFO level for either DMA request generation or interrupt generation is programmed in the FTHRES bits.

If a timeout counter is needed, the TCEN bit can be set and the timeout value programmed in the QUADSPI_LPTR register.

The dual-flash mode can be activated by setting DFM to 1 .

QUADSPI flash memory configuration

The parameters related to the targeted external flash memory are configured through the QUADSPI_DCR register.The user must program the flash memory size in the FSIZE bits, the chip-select minimum high time in CSHT bits, and the functional mode (Mode 0 or Mode 3) in the MODE bit.

20.3.11 QUADSPI use

The operating mode is selected using FMODE[1:0] (QUADSPI_CCR[27:26]).

Indirect mode

When FMODE is programmed to 00 , the indirect-write mode is selected and data can be sent to the flash memory. With FMODE

= 01

,the indirect-read mode is selected where data can be read from the flash memory.

When the QUADSPI is used in indirect mode, the frames are constructed in the following way:

Specify a number of data bytes to read or write in QUADSPI_DLR.

Specify the frame format, mode and instruction code in QUADSPI_CCR.

Specify optional alternate byte to be sent right after the address phase in QUADSPI_ABR.

Specify the operating mode in QUADSPI_CR. If FMODE $= 00$ (indirect-write mode) and DMAEN $= 1$ ,then QUADSPI_AR must be specified before QUADSPI_CR. Otherwise QUADSPI_DR can be written by the DMA before QUADSPI_AR is updated (if the DMA controller has already been enabled).

Specify the targeted address in QUADSPI_AR.

Read/write the data from/to the FIFO through QUADSPI_DR.

When writing QUADSPI_CR, the user specifies the following settings:

enable bit (EN) set to 1

DMA enable bit (DMAEN) for transferring data to/from RAM

timeout counter enable bit (TCEN)

sample shift setting (SSHIFT)

FIFO threshold level (FTRHES) to indicate when the FTF flag must be set

interrupt enables

automatic status-polling mode parameters: match mode and stop mode (valid when FMODE = 11)

clock prescaler

When writing QUADSPI_CCR, the user specifies the following parameters:

instruction byte through INSTRUCTION bits

the way the instruction has to be sent through the IMODE bits (1/2/4 lines)

the way the address has to be sent through the ADMODE bits (None/1/2/4 lines)

address size (8/16/24/32-bit) through ADSIZE bits

the way the alternate bytes have to be sent through the ABMODE (None/1/2/4 lines)

alternate bytes number $(1 / 2 / 3 / 4)$ through the ABSIZE bits

presence or not of dummy bytes through the DBMODE bit

number of dummy bytes through the DCYC bits

the way data have to be sent/received (none/1/2/4 lines) through DMODE bits

If neither QUADSPI_AR nor QUADSPI_DR need to be updated for a particular command, then the command sequence starts as soon as QUADSPI_CCR is written. This is the case when both ADMODE and DMODE are 00, or if just ADMODE = 00 when in indirect read mode (FMODE = 01).

When an address is required (ADMODE is not 00) and the data register does not need to be written (when FMODE

= 01

or DMODE

= 00

),the command sequence starts as soon as the address is updated with a write to QUADSPI_AR.

In case of data transmission (FMODE = 00 and DMODE! = 00), the communication start is triggered by a write in the FIFO through QUADSPI_DR.

Automatic status-polling mode

This mode is enabled setting the FMODE bitfield (QUADSPI_CCR[27:26]) to 10 . In this mode, the programmed frame is sent and the data retrieved periodically.

The maximum amount of data read in each frame is 4 bytes. If more data is requested in QUADSPI_DLR, it is ignored and only 4 bytes are read.

The periodicity is specified in the QUADSPI_PISR register.

Once the status data is retrieved, it can internally be processed:

to set the status match flag and generate an interrupt if enabled

to stop automatically the periodic retrieving of the status bytes

The received value can be masked with the value stored in QUADSPI_PSMKR and ORed or ANDed with the value stored in QUADSPI_PSMAR.

In case of match, the status match flag is set and an interrupt is generated if enabled, and the QUADSPI can be automatically stopped if the AMPS bit is set.

In any case, the latest retrieved value is available in QUADSPI_DR.

Memory-mapped mode

In memory-mapped mode, the external flash memory is seen as an internal memory but with some latency during accesses. Only read operations are allowed to the external flash memory in this mode.

The memory-mapped mode is entered by setting FMODE to 11 in QUADSPI_CCR.

The programmed instruction and frame is sent when a master is accessing the memory-mapped space.

The FIFO is used as a prefetch buffer to anticipate linear reads. Any access to QUADSPI_DR in this mode returns zero.

QUADSPI_DLR has no meaning in memory-mapped mode.

20.3.12 Sending the instruction only once

Some flash memories (for example: Winbound) provide a mode where an instruction must be sent only with the first command sequence, while subsequent commands start directly with the address. One can take advantage of such a feature using the SIOO bit (QUADSPI_CCR[28]).

SIOO is valid for all functional modes (indirect, automatic status-polling, and memory-mapped). If the SIOO bit is set, the instruction is sent only for the first command following a write to QUADSPI_CCR. Subsequent command sequences skip the instruction phase, until there is a write to QUADSPI_CCR.

SIOO has no effect when IMODE

= 00

(no instruction).

20.3.13 QUADSPI error management

An error can be generated in the following case:

In indirect mode or automatic status-polling mode when a wrong address is programmed in QUADSPI_AR (according to the flash memory size defined by FSIZE[4:0] in the QUADSPI_DCR), TEF is set and an interrupt is generated if enabled.

Also in indirect mode, if the address plus the data length exceeds the flash memory size, TEF is set as soon as the access is triggered.

In memory-mapped mode, when an out-of-range access is done by a master or when the QUADSPI is disabled, a bus error is generated as a response to the faulty bus master request.

When a master is accessing the memory mapped space while the memory-mapped mode is disabled, a bus error is generated as a response to the faulty bus master request.

20.3.14 QUADSPI busy bit and abort functionality

Once the QUADSPI starts an operation with the flash memory, the BUSY bit is automatically set in QUADSPI_SR.

In indirect mode, BUSY is reset once the QUADSPI has completed the requested command sequence, and the FIFO is empty.

In automatic status-polling mode, BUSY goes low only after the last periodic access is complete,due to a match when

APMS = 1

,or due to an abort.

After the first access in memory-mapped mode, BUSY goes low only on a timeout event or on an abort.

Any operation can be aborted by setting the ABORT bit in QUADSPI_CR. Once the abort is completed, BUSY and ABORT are automatically reset, and the FIFO is flushed.

Note: Some flash memories may misbehave if a write operation to a status registers is aborted.

20.3.15 NCS behavior

By default, NCS is high, deselecting the external flash memory. NCS falls before an operation begins and rises as soon as it finishes.

When CKMODE

= 0

("mode0",where CLK stays low when no operation is in progress), NCS falls one CLK cycle before an operation first rising CLK edge, and NCS rises one CLK cycle after the operation final rising CLK edge, as shown in the figure below.

Figure 78. NCS when CKMODE

= 0 (T = CLK period)

When CKMODE=1 ("mode3", where CLK goes high when no operation is in progress) and DDRM=0 (SDR mode), NCS still falls one CLK cycle before an operation first rising CLK edge, and NCS rises one CLK cycle after the operation final rising CLK edge, as shown in the figure below.

Figure 79. NCS when CKMODE = 1 in SDR mode (T = CLK period)

When CKMODE

= 1

(“mode3”) and DDRM

= 1

(DDR mode),NCS falls one CLK cycle before an operation first rising CLK edge, and NCS rises one CLK cycle after the operation final active rising CLK edge, as shown in the figure below. Because DDR operations must finish with a falling edge, CLK is low when NCS rises, and CLK rises back up one half of a CLK cycle afterwards.

When the FIFO stays full in a read operation or if the FIFO stays empty in a write operation, the operation stalls and CLK stays low until firmware services the FIFO. If an abort occurs when an operation is stalled, NCS rises just after the abort is requested and then CLK rises one half of a CLK cycle later, as shown in Figure 81.

Figure 81. NCS when CKMODE = 1 with an abort (T = CLK period)

When not in dual-flash mode (DFM = 0) and FSEL = 0 (default value), only FLASH 1 is accessed. Thus BK2_NCS stays high,if FSEL = 1, only FLASH 2 is accessed and BK1_NCS stays high. In dual-flash mode, BK2_NCS behaves exactly the same as BK1_NCS. Thus, if there is a FLASH 2 and if the application is dual-flash mode only, then BK1_NCS signal can be used for FLASH 2 as well, and the pin devoted to BK2_NCS can be used for other functions.

20.4 QUADSPI interrupts

An interrupt can be produced on the following events:

Timeout

Status match

FIFO threshold

Transfer complete

Transfer error

Separate interrupt enable bits are available for flexibility.

Table 156. QUADSPI interrupt requests

Interrupt event	Event flag	Enable control bit
Timeout	TOF	TOIE
Status match	SMF	SMIE
FIFO threshold	FTF	FTIE
Transfer complete	TCF	TCIE
Transfer error	TEF	TEIE

20.5 QUADSPI registers

20.5.1 QUADSPI control register (QUADSPI_CR)

Address offset: 0x000

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRESCALER[7:0]								PMM	APMS	Res.	TOIE	SMIE	FTIE	TCIE	TEIE
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw		rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Resr	Res.	Res.	FTHRES[3:0]				FSEL	DFM	Res.	SSHIF T	TCEN	DMAE N	ABORT	EN
				rw	rw	rw	rw	rw	rw		rw	rw	rw	rw	rw

Bits 31:24 PRESCALER[7:0]: Clock prescaler

This bitfield defines the scaler factor for generating CLK based on the clock (value+1).

F_{CLK} = F

,clock used directly as QUADSPI CLK (prescaler bypassed)

F_{CLK} = F / 2

F_{CLK} = F / 3

\dots

255:

F_{CLK} = F / 256

For odd clock division factors,CLK duty cycle is not

50 %

. The clock signal remains low one cycle longer than it stays high.

When setting quad-SPI interface in DDR mode, the prescaler must be set with a division ratio of two or more.

Note: This bitfield can be modified only when BUSY

= 0

Bit 23 PMM: Polling match mode

This bit indicates which method must be used for determining a "match" during automatic status-polling mode.

0: AND match mode. SMF is set if all the unmasked bits received from the flash memory

match the corresponding bits in the match register.

1: OR match mode. SMF is set if any one of the unmasked bits received from the flash

memory matches its corresponding bit in the match register.

Note: This bit can be modified only when BUSY

= 0

Bit 22 APMS: Automatic status-polling mode stop

This bit determines if automatic status-polling is stopped after a match.

0: Automatic status-polling mode is stopped only by abort or by disabling the QUADSPI.

1: Automatic status-polling mode stops as soon as there is a match.

Note: This bit can be modified only when BUSY

= 0

Bit 21 Reserved, must be kept at reset value.

Bit 20 TOIE: Timeout interrupt enable

This bit enables the timeout interrupt.

0: Interrupt disabled

1: Interrupt enabled

Bit 19 SMIE: Status match interrupt enable

This bit enables the status match interrupt.

0 : Interrupt disabled

1: Interrupt enabled

Bit 18 FTIE: FIFO threshold interrupt enable

This bit enables the FIFO threshold interrupt.

0 : Interrupt disabled

1: Interrupt enabled

Bit 17 TCIE: Transfer complete interrupt enable

This bit enables the transfer complete interrupt.

0 : Interrupt disabled

1: Interrupt enabled

Bit 16 TEIE: Transfer error interrupt enable

This bit enables the transfer error interrupt.

0 : Interrupt disabled

1: Interrupt enabled

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:8 FTHRES[3:0]: FIFO threshold level

This bitfield defines, in indirect mode, the threshold number of bytes in the FIFO that causes the FIFO threshold flag (bit FTF in register QUADSPI_SR) to be set. 0: In indirect-write mode (FMODE = 00), FTF is set if there are one or more free bytes location left in the FIFO, or indirect-read mode (FMODE = 01), FTF is set if there are 1 or more valid bytes that can be read from the FIFO.

1: In indirect-write mode (FMODE = 00), FTF is set if there are two or more free bytes location left in the FIFO, or indirect read mode (FMODE = 01), FTF is set if there are two or more valid bytes that can be read from the FIFO.

\dots

15: In indirect-write mode (FMODE = 00), FTF is set if there are 16 free bytes location left in the FIFO, or indirect read mode (FMODE = 01), FTF is set if there are 16 valid bytes that can be read from the FIFO.

If DMAEN

= 1

,then the DMA controller for the corresponding channel must be disabled before changing the FTHRES value.

Bit 7 FSEL: Flash memory selection

This bit selects the flash memory to be addressed in single-flash mode (when DFM = 0).

0: FLASH 1 selected

1: FLASH 2 selected

Note: This bit can be modified only when BUSY = 0 . This bit is ignored when DFM = 1 .

Bit 6 DFM: Dual-flash mode

This bit activates dual-flash mode, where two external flash memories are used

simultaneously to double throughput and capacity.

0: Dual-flash mode disabled

1: Dual-flash mode enabled

Note: This bit can be modified only when BUSY

= 0

Bit 5 Reserved, must be kept at reset value.

Bit 4 SSHIFT: Sample shift

By default, the QUADSPI samples data 1/2 of a CLK cycle after the data is driven by the flash memory. This bit allows the data to be sampled later in order to account for external signal delays.

0 : No shift

1: 1/2 cycle shift

The firmware must assure that SSHIFT

= 0

when in DDR mode (when DDRM

= 1

Note: This bitfield can be modified only when BUSY

= 0

Bit 3 TCEN: Timeout counter enable

This bit is valid only when memory-mapped mode (FMODE = 11) is selected. Activating this bit causes the NCS to be released (and thus reduces consumption) if there has not been an access after a certain amount of time, where this time is defined by TIMEOUT[15:0] (QUADSPI_LPTR). This bit enables the timeout counter.

By default, the QUADSPI never stops its prefetch operation, keeping the previous read operation active with NCS maintained low, even if no access to the flash memory occurs for a long time. Since flash memories tend to consume more when NCS is held low, the application may want to activate the timeout counter (TCEN = 1, bit 3 of QUADSPI_CR) so that NCS is released after a period of TIMEOUT[15:0] (QUADSPI_LPTR) cycles have elapsed without an access since when the FIFO becomes full with prefetch data.

0: Timeout counter is disabled, and thus the NCS remains active indefinitely after an access in memory-mapped mode.

1: Timeout counter is enabled, and thus the NCS is released in memory-mapped mode after TIMEOUT[15:0] cycles of flash memory inactivity.

Note: This bit can be modified only when BUSY

= 0

Bit 2 DMAEN: DMA enable

In indirect mode, the DMA can be used to input or output data via the QUADSPI_DR register.

DMA transfers are initiated when the FIFO threshold flag, FTF, is set.

0: DMA is disabled for indirect mode.

1: DMA is enabled for indirect mode.

Bit 1 ABORT: Abort request

This bit aborts the ongoing command sequence. It is automatically reset once the abort is complete. This bit stops the current transfer.

In automatic status-polling or memory-mapped mode, this bit also reset APM or DM bit.

0 : No abort requested

1: Abort requested

Bit 0 EN: QUADSPI enable

0: QUADSPI disabled

1: QUADSPI enabled

20.5.2 QUADSPI device configuration register (QUADSPI_DCR)

Address offset: 0x004 Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	FSIZE[4:0]
											rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Resr	Res.	Res.	Res.	CSHT[2:0]			Res.	Res.	Res.	Res.	Res.	Res.	Res.	CKMO DE
					rw	rw	rw								rw

Bits 31:21 Reserved, must be kept at reset value.

Bits 20:16 FSIZE[4:0]: Flash memory size

This bitfield defines the size of external memory using the following formula: Number of bytes in flash memory

= 2^{[FSIZE + 1]}

If DFM = 1, FSIZE indicates the total capacity of the two flash memories together.

Note: This bitfield can be modified only when BUSY

= 0

Bits 15:11 Reserved, must be kept at reset value.

Bits 10:8 CSHT[2:0]: Chip select high time

CSHT+1 defines the minimum number of CLK cycles which the chip select (NCS) must

remain high between commands issued to the flash memory.

0: NCS stays high for at least 1 cycle between flash memory commands

1: NCS stays high for at least 2 cycles between flash memory commands

\dots

7: NCS stays high for at least 8 cycles between flash memory commands

Note: This bitfield can be modified only when BUSY

= 0

Bits 7:1 Reserved, must be kept at reset value.

Bit 0 CKMODE: Mode 0/mode 3

This bit indicates the level that CLK takes between commands (when NCS = 1).

0: CLK must stay low while NCS is high (chip select released). This is referred to as mode 0 .

1: CLK must stay high while NCS is high (chip select released). This is referred to as mode 3.

Note: This bitfield can be modified only when BUSY

= 0

20.5.3 QUADSPI status register (QUADSPI_SR)

Address offset: 0x008

Reset value: 0x00000000

Bits 31:13 Reserved, must be kept at reset value.

Bits 12:8 FLEVEL[4:0]: FIFO level

This bitfield gives the number of valid bytes which are being held in the FIFO. FLEVEL = 0 when the FIFO is empty, and 16 when it is full. In memory-mapped mode and in automatic status-polling mode, FLEVEL is zero.

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 BUSY: Busy

This bit is set when an operation is on going. This bit clears automatically when the operation with the flash memory is finished and the FIFO is empty.

Bit 4 TOF: Timeout flag

This bit is set when timeout occurs. It is cleared by writing 1 to CTOF.

Bit 3 SMF: Status match flag

This bit is set in automatic status-polling mode when the unmasked received data matches the corresponding bits in the match register (QUADSPI_PSMAR). It is cleared by writing 1 to CSMF.

Bit 2 FTF: FIFO threshold flag

In indirect mode, this bit is set when the FIFO threshold is reached, or if there is any data left in the FIFO after reads from the flash memory are complete. It is cleared automatically as soon as threshold condition is no longer true.

In automatic status-polling mode this bit is set every time the status register is read, and the bit is cleared when the data register is read.

Bit 1 TCF: Transfer complete flag

This bit is set in indirect mode when the programmed number of data is transferred or in any mode when the transfer is aborted.It is cleared by writing 1 to CTCF.

Bit 0 TEF: Transfer error flag

This bit is set in indirect mode when an invalid address is being accessed in indirect mode. It is cleared by writing 1 to CTEF.

20.5.4 QUADSPI flag clear register (QUADSPI_FCR)

Address offset: 0x00C

Reset value: 0x00000000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	CTOF	CSMF	Res.	CTCF	CTEF
											w	w		w	w

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 CTOF: Clear timeout flag

Writing 1 clears the TOF flag in QUADSPI_SR.

Bit 3 CSMF: Clear status match flag

Writing 1 clears the SMF flag in QUADSPI_SR.

Bit 2 Reserved, must be kept at reset value.

Bit 1 CTCF: Clear transfer complete flag

Writing 1 clears the TCF flag in QUADSPI_SR.

Bit 0 CTEF: Clear transfer error flag

Writing 1 clears the TEF flag in QUADSPI_SR.

20.5.5 QUADSPI data length register (QUADSPI_DLR)

Address offset: 0x010

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DL[31:16]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

DL[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:0 DL[31:0]: Data length

Number of data to be retrieved (value+1) in indirect and automatic status-polling modes. A value no greater than 3 (indicating 4 bytes) must be used for automatic status-polling mode.

All 1s in indirect mode means undefined length, where the QUADSPI continues until the end

of memory, as defined by FSIZE.

0x0000_0000: 1 byte is to be transferred

0x0000_0001: 2 bytes are to be transferred

0x0000_0002: 3 bytes are to be transferred

0x0000_0003: 4 bytes are to be transferred

0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be transferred

0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes are to be transferred

0xFFFF_FFFF: undefined length - all bytes until the end of flash memory (as defined by

FSIZE) are to be transferred. Continue reading indefinitely if FSIZE = 0x1F.

DL [0]

is stuck at 1 in dual-flash mode

(DFM = 1)

even when 0 is written to this bit,thus

assuring that each access transfers an even number of bytes.

This bitfield has no effect when in memory-mapped mode (FMODE = 10).

Note: This bitfield can be written only when BUSY

= 0

20.5.6 QUADSPI communication configuration register (QUADSPI_CCR)

Address offset: 0x014 Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DDRM	DHHC	Res.	SIOO	FMODE[1:0]		DMODE[1:0]		Res.	DCYC[4:0]					ABSIZE[1:0]
rw	rw		rw	rw	rw	rw	rw		rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABMODE[1:0]		ADSIZE[1:0]		ADMODE[1:0]		IMODE[1:0]		INSTRUCTION(7:0)
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bit 31 DDRM: Double data rate mode

This bit sets the DDR mode for the address, alternate byte and data phase:

0: DDR mode disabled

1: DDR mode enabled

Note: This bit can be written only when BUSY

= 0

Bit 30 DHHC: DDR hold

This bit delays the data output by 1/4 of the QUADSPI output clock cycle in DDR mode:

0: Data output delayed using analog delay

1: Data output delayed by 1/4 of a QUADSPI output clock cycle

This feature is only active in DDR mode.

Note: This bit can be written only when BUSY

= 0

PRESCALER

> 0

is mandatory when DHHC

= 1

Bit 29 Reserved, must be kept at reset value.

Bit 28 SIOO: Send instruction only once mode

This bit has no effect when IMODE = 00.See Section 20.3.12 for more details.

0: Instruction sent on every transaction

1: Instruction sent only for the first command

Note: This bit can be written only when BUSY

= 0

Bits 27:26 FMODE[1:0]: Functional mode

This bitfield defines the QUADSPI functional mode of operation.

00: Indirect-write mode

01: Indirect-read mode

10: Automatic status-polling mode

11: Memory-mapped mode

If DMAEN = 1 already, the DMA controller for the corresponding channel must be disabled

before changing the FMODE value.

Note: This bitfield can be written only when BUSY

= 0

Bits 25:24 DMODE[1:0]: Data mode

This bitfield defines the data phase mode of operation:

00: No data

01: Data on a single line

10: Data on two lines

11: Data on four lines

This bitfield also determines the dummy phase mode of operation.

Note: This bitfield can be written only when BUSY

= 0

Bit 23 Reserved, must be kept at reset value.

Bits 22:18 DCYC[4:0]: Number of dummy cycles

This bitfield defines the duration of the dummy phase. In both SDR and DDR modes,

it specifies a number of CLK cycles (0-31).

Note: This bitfield can be written only when BUSY

= 0

Bits 17:16 ABSIZE[1:0]: Alternate-byte size

This bit defines the size of alternate bytes.

00: 8-bit alternate byte

01: 16-bit alternate bytes

10: 24-bit alternate bytes

11: 32-bit alternate bytes

Note: This bitfield can be written only when BUSY

= 0

Bits 15:14 ABMODE[1:0]: Alternate byte mode

This bitfield defines the alternate-byte phase mode of operation.

00: No alternate bytes

01: Alternate bytes on a single line

10: Alternate bytes on two lines

11: Alternate bytes on four lines

Note: This bitfield can be written only when BUSY

= 0

Bits 13:12 ADSIZE[1:0]: Address size

This bit defines address size:

00: 8-bit address

01: 16-bit address

10: 24-bit address

11: 32-bit address

Note: This bitfield can be written only when BUSY

= 0

Bits 11:10 ADMODE[1:0]: Address mode

This bitfield defines the address phase mode of operation.

00: No address

01: Address on a single line

10: Address on two lines

11: Address on four lines

Note: This bitfield can be written only when BUSY

= 0

Bits 9:8 IMODE[1:0]: Instruction mode

This bitfield defines the instruction phase mode of operation.

00: No instruction

01: Instruction on a single line

10: Instruction on two lines

11: Instruction on four lines

Note: This bitfield can be written only when BUSY

= 0

Bits 7:0 INSTRUCTION[7:0]: Instruction

Instruction to be sent to the external SPI device.

Note: This bitfield can be written only when BUSY

= 0

20.5.7 QUADSPI address register (QUADSPI_AR)

Address offset: 0x018 Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADDRESS[31:16]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDRESS[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:0 ADDRESS[31:0]: Address

This bitfield contains the address to be sent to the external flash memory.

Writes to this bitfield are ignored when BUSY

= 1

or when FMODE

= 11

(memory-mapped mode).

In dual flash mode, ADDRESS[0] is automatically stuck to 0 as the address must

always be even

20.5.8 QUADSPI alternate-byte register (QUADSPI_ABR)

Address offset: 0x01C

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ALTERNATE[31:16]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ALTERNATE[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:0 ALTERNATE[31:0]: Alternate bytes

Optional data to be send to the external SPI device right after the address.

Note: This bitfield can be written only when BUSY

= 0

20.5.9 QUADSPI data register (QUADSPI_DR)

Address offset: 0x020

Reset value: 0x00000000

DATA[15:0]

Bits 31:0 DATA[31:0]: Data

Data to be sent/received to/from the external SPI device.

In indirect write mode, data written to this register is stored on the FIFO before it is sent to the flash memory during the data phase. If the FIFO is too full, a write operation is stalled until the FIFO has enough space to accept the amount of data being written.

In indirect read mode, reading this register gives (via the FIFO) the data which was received from the flash memory. If the FIFO does not have as many bytes as requested by the read operation and if BUSY=1, the read operation is stalled until enough data is present or until the transfer is complete, whichever happens first.

In automatic status-polling mode, this register contains the last data read from the flash memory (without masking).

Word, halfword, and byte accesses to this register are supported. In indirect write mode, a byte write adds 1 byte to the FIFO, a halfword write 2, and a word write 4. Similarly, in indirect read mode, a byte read removes 1 byte from the FIFO, a halfword read 2, and a word read 4. Accesses in indirect mode must be aligned to the bottom of this register: a byte read must read DATA[7:0] and a halfword read must read DATA[15:0].

20.5.10 QUADSPI polling status mask register (QUADSPI_PSMKR)

Address offset: 0x024

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MASK[31:16]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MASK[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:0 MASK[31:0]: Status mask

Mask to be applied to the status bytes received in automatic status-polling mode.

For bit n:

0 : Bit n of the data received in automatic status-polling mode is masked and its value is not considered in the matching logic

1: Bit n of the data received in automatic status-polling mode is unmasked and its value is considered in the matching logic

Note: This bitfield can be written only when BUSY

= 0

. 20.5.11 QUADSPI polling status match register (QUADSPI_PSMAR)

Address offset: 0x028

Reset value: 0x00000000

MATCHNO.01
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:0 MATCH[31:0]: Status match

Value to be compared with the masked status register to get a match.

Note: This bitfield can be written only when BUSY

= 0

20.5.12 QUADSPI polling interval register (QUADSPI_PIR)

Address offset: 0x02C

Reset value: 0x00000000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 INTERVAL[15:0]: Polling interval

Number of CLK cycles between two read during automatic status-polling phases.

Note: This bitfield can be written only when BUSY

= 0

20.5.13 QUADSPI low-power timeout register (QUADSPI_LPTR)

Address offset: 0x030

Reset value: 0x00000000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 TIMEOUT[15:0]: Timeout period

After each access in memory-mapped mode, the QUADSPI prefetches the subsequent bytes and holds these bytes in the FIFO. This bitfield indicates how many CLK cycles the QUADSPI waits after the FIFO becomes full until it raises NCS, putting the flash memory in a lower-consumption state.

Note: This bitfield can be written only when BUSY

= 0

20.5.14 QUADSPI register map

Table 157. QUADSPI register map and reset values

Offset	Register name	31	30	23	23	27	26	26	24	23	22	21	20	1.	1.	17	伯	1.5	14	1	12	11	10	9	8	7	6	5	4	3	2	1	O
0x000	QUADSPI_CR	PRESCALER[7:0]								Problem	Antonio	SUB	TOUT	Source	HE	TOUT	千港元	LUMB	Life	时	LIST	FTHRES [3:0]				ECCO	DEL	3	LHIHSS	For	NEWWO	Acta	五
0x000	Reset value	0	0	0	0	0	0	0	0	0	0		0	0	0	0	0					0	0	0	0	0	0		0	0	0	0	0
0x004	QUADSPI_DCR	a	W	of	u4 qu3	si	LUS	LUE	3	of	Let	新鲜	FSIZE[4:0]					中心	LIS	a	LUB	STA	CSHT			of	y3	y y	LUB	Let	y4	3	300W20
0x004	Reset value												0	0	0	0	0						0	0	0								0
0x008	QUADSPI SR		y	of	ai	3	W	y	中國	gi	ai	g	3	a	中华	y	3	好	3		FLEVEL[4:0]							BB	PO	Source	千港元	t	世
0x008	Reset value																				0	0	0	0	0			0	0	0	0	0	0
0x00C	QUADSPI FCR	奶茶	gi	：	COMP	3	S	3	的	gi	S	0	S	CHIP	：	3	3	坊	3	3	3	3	3	gi	S	3	SUB	3	CON	COMPER		TOUT	LUE
0x00C	Reset value																												0	0		0	0
0x010	QUADSPIDLR	DL[31:0]
0x010	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x014	QUADSPI CCR	WYCC	DEE		So	300W3	(1,191)	300W0	1.00	坊中	DCYC[4:0]					321S8V	(1,001)	300WAV(1,011)		32ISCV	1,010	300W(1,011)		300WI	1.19	INSTRUCTION(7:0)
0x014	Reset value	0	0		0	0	0	0	0		0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x018	QUADSPIAR	ADDRESSI31:01
0x018	Reset value	O	OOOOO00O0O0																														O
0x01C	QUADSPIABR	Al
0x01C	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x020	QUADSPIDR	DATA131:0
0x020	Reset value	OOOOOOO0OO0OO0OOO0OOO0OOOOOO00O0

21 Analog-to-digital converters (ADC)

21.1 Introduction

This section describes the implementation of up to 5 ADCs:

ADC1 and ADC2 are tightly coupled and can operate in dual mode (ADC1 is master).

ADC3 and ADC4 are tightly coupled and can operate in dual mode (ADC3 is master).

ADC5 is controlled independently.

Each ADC consists of a 12-bit successive approximation analog-to-digital converter.

Each ADC has up to 19 multiplexed channels. A/D conversion of the various channels can be performed in single, continuous, scan or discontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned 16-bit data register.

The ADCs are mapped on the AHB bus to allow fast data handling.

The analog watchdog features allow the application to detect if the input voltage goes outside the user-defined high or low thresholds.

A built-in hardware oversampler allows to improve analog performance while off-loading the related computational burden from the CPU.

An efficient low-power mode is implemented to allow very low consumption at low frequency.

21.2 ADC main features

High-performance features

Up to 5 ADCs, out of which four of them ((in pairs) can operate in dual mode:

ADC1 is connected to 14 external channels +4 internal channels

ADC2 is connected to 16 external channels +2 internal channels

ADC3 is connected to 15 external channels +3 internal channels

ADC4 is connected to 16 external channels + 2 internal channels

ADC5 is connected to 13 external channels +5 internal channels

12, 10, 8 or 6-bit configurable resolution

ADC conversion time is independent from the AHB bus clock frequency

Faster conversion time by lowering resolution

Manage single-ended or differential inputs

AHB slave bus interface to allow fast data handling

Self-calibration

Channel-wise programmable sampling time

Flexible sampling time control

Up to four injected channels (analog inputs assignment to regular or injected channels is fully configurable)

Hardware assistant to prepare the context of the injected channels to allow fast context switching

Data alignment with in-built data coherency

Data can be managed by DMA for regular channel conversions

4 dedicated data registers for the injected channels

Oversampler

16-bit data register

Oversampling ratio adjustable from 2 to 256

Programmable data shift up to 8-bit

Data preconditioning

Gain compensation

Offset compensation

Low-power features

Speed adaptive low-power mode to reduce ADC consumption when operating at low frequency

Allows slow bus frequency application while keeping optimum ADC performance

Provides automatic control to avoid ADC overrun in low AHB bus clock frequency

application (auto-delayed mode)

Number of external analog input channels per ADC

Up to 5 fast channels from GPIO pads

Up to 13 slow channels from GPIO pads

In addition, there are several internal dedicated channels

The internal reference voltage $(V_{REFINT})$ ,connected to ADC1,3,4 and 5

The internal temperature sensor $(V_{TS})$ ,connected to $ADC 1$ and 5

The $V_{BAT}$ monitoring channel $(V_{BAT} / 3)$ ,connected to ADC1,3 (for category 3

devices only) and 5

The OPAMP1 internal output connected to ADC1

The OPAMP2 and OPAMP3 internal outputs connected to ADC2

The OPAMP3 internal output connected to ADC3

The OPAMP6 internal output connected to ADC4 (for category 3 devices) or

ADC3 (for category 4 devices)

The OPAMP4 and OPAMP5 internal outputs connected to ADC5

Start-of-conversion can be initiated:

By software for both regular and injected conversions

By hardware triggers with configurable polarity (internal timers events or GPIO

input events) for both regular and injected conversions

Conversion modes

Each ADC can convert a single channel or can scan a sequence of channels

Single mode converts selected inputs once per trigger

Continuous mode converts selected inputs continuously

Discontinuous mode

Dual ADC mode for ADC1, ADC2, ADC3 and ADC4

Interrupt generation at ADC ready, the end of sampling, the end of conversion (regular or injected), end of sequence conversion (regular or injected), analog watchdog 1,2 or 3 or overrun events

3 analog watchdogs per ADC

Watchdog can perform filtering to ignore out-of-range data

ADC input range: $V_{REF -} \leq V_{IN} \leq V_{REF +}$

Figure 82 shows the block diagram of one ADC.

Refer to the OPAMP electrical characteristics section of the product datasheet for the ADC sampling time value to be applied when converting the OPAMP output voltage.

21.3 ADC implementation

Table 158. ADC features

ADC modes/features	ADC1	ADC2	ADC3	ADC4	ADC5
Dual mode	X (coupled together)		X (coupled together)		-

21.4.2 ADC pins and internal signals

Table 159. ADC internal input/output signals

Internal signal name	Signal type	Description
adc_ext_trg[31:0]	Inputs	Up to 32 external trigger inputs for the regular conversions (can be connected to on-chip timers). These inputs are shared between the ADC master and the ADC slave.
adc_jext_trg[31:0]	Inputs	Up to 31 external trigger inputs for the injected conversions (can be connected to on-chip timers). These inputs are shared between the ADC master and the ADC slave.
adc_awdx_out	Output	Internal analog watchdog output signal connected to on-chip timers (x = Analog watchdog number 1,2,3)
adc_ker_ck	Output	ADC kernel clock
adc_hclk	Input	ADC peripheral clock
adc_it	Output	ADC interrupt
adc_dma	Output	ADC DMA request
$V_{TS}$	Input	Output voltage from internal temperature sensor
VREFINT	Input	Output voltage from internal reference voltage
$V_{BAT}$	Input supply	External battery voltage supply

Table 160. ADC input/output pins

Pin name	Signal type	Comments
VREF+	Input, analog reference positive	The higher/positive reference voltage for the ADC
VDDA	Input, analog supply	Analog power supply equal V $_{DDA}$
VREF-	Input, analog reference negative	The lower/negative reference voltage for the ADC. $V_{REF}$ _ is internally connected to $V_{SSA}$
VSSA	Input, analog supply ground	Ground for analog power supply. On device package which do not have a dedicated $V_{SSA}$ pin, $V_{SSA}$ is internally connected to Vss.
$V_{INP} i$	Positive analog input channels for each ADC	Connected either to ADCx INPi external channels or to internal channels. This input is converted in single- ended mode
VINNI	Negative analog input channels for each ADC	Connected either to $V_{REF-}$ or to external channels: ADCx_INNi and ADCx_INP[i+1].

Table 160. ADC input/output pins (continued)

Pin name	Signal type	Comments
ADCx_INNi	Negative external analog input signals	Up to 19 analog input channels $(x = ADC$ number $= 1$ , 2, 3, 4 or 5). Refer to Section 21.4.4: ADC1/2/3/4/5 connectivity for details.
ADCx_INPi	Positive external analog input signals	Up to 19 analog input channels (x = ADC number = 1, 2, 3, 4 or 5). Refer to Section 21.4.4: ADC1/2/3/4/5 connectivity for details

21.4.3 ADC clocks

Dual clock domain architecture

The dual clock-domain architecture means that the ADC clock is independent from the AHB bus clock.

The input clock is the same for all ADCs and can be selected between two different clock sources (see Figure 83: ADC clock scheme):

The ADC clock can be a specific clock source, derived from the following clock sources:

The system clock

PLL "P" clock

Refer to RCC Section for more information on how to generate ADC dedicated clock. To select this scheme, bits CKMODE[1:0] of the ADCx_CCR register must be reset.

The ADC clock can be derived from the AHB clock of the ADC bus interface, divided by a programmable factor $(1, 2 or 4)$ . In this mode,a programmable divider factor can be selected (/1, 2 or 4 according to bits CKMODE[1:0]).

To select this scheme, bits CKMODE[1:0] of the ADCx_CCR register must be different from 00.

Note: e: For option 2), a prescaling factor of 1 (CKMODE[1:0] = 01) can be used only if the AHB prescaler is set (HPRE[3:0] = 0xxx in RCC_CFGR register).

Option 1) has the advantage of reaching the maximum ADC clock frequency whatever the AHB clock scheme selected. The ADC clock can eventually be divided by the following ratio:

1, 2, 4, 6, 8, 12, 16, 32, 64, 128, 256

; using the prescaler configured with bits PRESC[3:0] in the ADCx_CCR register.

Option 2) has the advantage of bypassing the clock domain resynchronizations. This can be useful when the ADC is triggered by a timer and if the application requires that the ADC is precisely triggered without any uncertainty (otherwise, an uncertainty of the trigger instant time is added by the resynchronizations between the two clock domains).

21.4.5 Slave AHB interface

The ADCs implement an AHB slave port for control/status register and data access. The features of the AHB interface are listed below:

Word (32-bit) accesses

Single cycle response

Response to all read/write accesses to the registers with zero wait states.

The AHB slave interface does not support split/retry requests, and never generates AHB errors.

21.4.6 ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN)

By default, the ADC is in Deep-power-down mode where its supply is internally switched off to reduce the leakage currents (the reset state of bit DEEPPWD is 1 in the ADC_CR register).

To start ADC operations, follow the sequence below:

Exit Deep-power-down mode by clearing DEEPPWD bit.

Enable the ADC voltage regulator by setting ADVREGEN.

Wait for the startup time to configure the ADC (refer to the device datasheet for the value of the startup time).

When ADC operations are complete,the ADC can be disabled (ADEN

= 0

). It is possible to save power by also disabling the ADC voltage regulator. This is done by writing bit ADVREGEN

= 0

Then, to save more power by reducing the leakage currents, it is also possible to re-enter in ADC Deep-power-down mode by setting bit DEEPPWD = 1 into ADC_CR register. This is particularly interesting before entering Stop mode.

Note: Writing DEEPPWD = 1 automatically disables the ADC voltage regulator and bit ADVREGEN is automatically cleared.

When the internal voltage regulator is disabled (ADVREGEN = 0), the internal analog

In ADC Deep-power-down mode (DEEPPWD = 1), the internal analog calibration is lost and it is necessary to either relaunch a calibration or re-apply the calibration factor which was previously saved (refer to Section 21.4.8: Calibration (ADCAL, ADCALDIF, conversions.

21.4.7	Single-ended and differential input channels
	Channels can be configured to be either single-ended input or differential input by programming DIFSEL[i] bits in the ADC_DIFSEL register. This configuration must be written while the ADC is disabled (ADEN = 0). Note that the DIFSEL[i] bits corresponding to single- ended channels are always programmed at 0.
	In single-ended input mode, the analog voltage to be converted for channel “i” is th difference between the ADCy_INPx external voltage equal to $V_{I N P I I}$ (positive input) and V $_{REF -}$ (negative input).
	In differential input mode, the analog voltage to be converted for channel “i” is the difference between the ADCy_INPx external voltage positive input equal to $V_{INPI}$ ,and the ADCy_INNx negative input equal to Vınınıi
	The input voltage in differential mode ranges from $V_{REF}$ to $V_{REF +}$ ,which makes a full scale range of $2 {xV}_{{REF}^{+}}$ . When $V_{INP [i]}$ equals $V_{REF} ., V_{INN [i]}$ equals $V_{{REF}^{+}}$ and the maximum negative input differential voltage ( $V_{REF}$ ) corresponds to 0x000 ADC output. When $V_{INPI}$ equals $V_{REF +}, V_{INNII}$ equals $V_{REF}$ and the maximum positive input differential voltage $(V_{REF +}) corresponds to 0 xFFF ADC output . When V_{INP [i]} and V_{INN [i]} are connected together,$ the zero input differential voltage corresponds to 0x800 ADC output.
	The ADC sensitivity in differential mode is twice smaller than in single-ended mode
	When ADC is configured as differential mode, both inputs should be biased at $(V_{REF +}) / 2$ voltage. Refer to the device datasheet for the allowed common mode input voltage $V_{CMI}$
	The input signals are supposed to be differential (common mode voltage should be fixed).
	Internal channels (such as $V_{TS}$ and $V_{REFINT}$ ) are used in single-ended mode only.
	For a complete description of how the input channels are connected for each ADC, refer to Section 21.4.4: ADC1/2/3/4/5 connectivity.
Caution:	When configuring the channel “i” in differential input mode, its negative input voltage $V_{INNIi}$ is connected to another channel. As a consequence, this channel is no longer usable in single-ended mode or in differential mode and must never be configured to be converted Some channels are shared between ADC1/ADC2/ADC3/ADC4/ADC5: this can make the channel on the other ADC unusable. The only exception is when ADC master and the slave operate in interleaved mode.
21.4.8	Calibration (ADCAL, ADCALDIF, ADC_CALFACT)
	Each ADC provides an automatic calibration procedure which drives all the calibration sequence including the power-on/off sequence of the ADC. During the procedure, the ADC calculates a calibration factor which is 7-bit wide and which is applied internally to the ADC until the next ADC power-off. During the calibration procedure, the application must not use the ADC and must wait until calibration is complete.
	Calibration is preliminary to any ADC operation. It removes the offset error which may vary from chip to chip due to process or bandgap variation
	The calibration factor to be applied for single-ended input conversions is different from the factor to be applied for differential input conversions:
	- Write ADCALDIF $= 0$ before launching a calibration to be applied for single-ended input conversions.
	Write ADCALDIF $= 1$ before launching a calibration to be applied for differential input

The calibration is then initiated by software by setting bit ADCAL = 1. Calibration can only be initiated when the ADC is disabled (when ADEN = 0). ADCAL bit stays at 1 during all the calibration sequence. It is then cleared by hardware as soon the calibration completes. At this time, the associated calibration factor is stored internally in the analog ADC and also in the bits CALFACT_S[6:0] or CALFACT_D[6:0] of ADC_CALFACT register (depending on single-ended or differential input calibration)

The internal analog calibration is kept if the ADC is disabled (ADEN = 0). However, if the ADC is disabled for extended periods, then it is recommended that a new calibration cycle is run before re-enabling the ADC.

The internal analog calibration is lost each time the power of the ADC is removed (example, when the product enters in Standby or VBAT mode). In this case, to avoid spending time recalibrating the ADC, it is possible to re-write the calibration factor into the ADC_CALFACT register without recalibrating, supposing that the software has previously saved the calibration factor delivered during the previous calibration.

The calibration factor can be written if the ADC is enabled but not converting (ADEN = 1 and ADSTART

= 0

and JADSTART

= 0

). Then,at the next start of conversion,the calibration factor is automatically injected into the analog ADC. This loading is transparent and does not add any cycle latency to the start of the conversion. It is recommended to recalibrate when

V_{REF +}

voltage changed more than

10 %

Software procedure to calibrate the ADC

Ensure DEEPPWD $= 0$ ,ADVREGEN $= 1$ and that ADC voltage regulator startup time has elapsed.

Ensure that $ADEN = 0$ .

Select the input mode for this calibration by setting ADCALDIF $= 0$ (single-ended input) or ADCALDIF $= 1$ (differential input).

Set ADCAL.

Wait until ADCAL $= 0$ .

The calibration factor can be read from ADC_CALFACT register.

Figure 89. ADC calibration

Software procedure to re-inject a calibration factor into the ADC

Ensure ADEN $= 1$ and ADSTART $= 0$ and JADSTART $= 0$ (ADC enabled and no conversion is ongoing).

Write CALFACT_S and CALFACT_D with the new calibration factors.

When a conversion is launched, the calibration factor is injected into the analog ADC only if the internal analog calibration factor differs from the one stored in bits CALFACT_S for single-ended input channel or bits CALFACT_D for differential input channel.

Figure 90. Updating the ADC calibration factor

Converting single-ended and differential analog inputs with a single ADC

If the ADC is supposed to convert both differential and single-ended inputs, two calibrations must be performed,one with ADCALDIF

= 0

and one with ADCALDIF

= 1

. The procedure is the following:

Disable the ADC.

Calibrate the ADC in single-ended input mode (with ADCALDIF = 0). This updates the register CALFACT_S[6:0].

Calibrate the ADC in differential input modes (with ADCALDIF = 1). This updates the register CALFACT_D[6:0].

Enable the ADC, configure the channels and launch the conversions. Each time there is a switch from a single-ended to a differential inputs channel (and vice-versa), the calibration is automatically injected into the analog ADC.

21.4.9 ADC on-off control (ADEN, ADDIS, ADRDY)

First of all, follow the procedure explained in Section 21.4.6: ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN)).

Once DEEPPWD

= 0

and ADVREGEN

= 1

,the ADC can be enabled and the ADC needs a stabilization time of

t_{STAB}

before it starts converting accurately,as shown in Figure 92. Two

ADEN = 1 enables the ADC. The flag ADRDY is set once the ADC is ready for

ADDIS = 1 disables the ADC. ADEN and ADDIS are then automatically cleared by

Regular conversion can then start either by setting ADSTART = 1 (refer to Section 21.4.18: or when an external trigger event occurs, if triggers are enabled.

Injected conversions start by setting JADSTART = 1 or when an external injected trigger

Set ADEN.

Wait until ADRDY $= 1$ (ADRDY is set after the ADC startup time). This can be done using the associated interrupt (setting ADRDYIE = 1).

Clear the ADRDY bit in the ADC_ISR register by writing 1 (optional).

Caution: ADEN bit cannot be set when ADCAL is set and during four ADC clock cycles after the ADCAL bit is cleared by hardware (end of the calibration).

Software procedure to disable the ADC

Check that both ADSTART $= 0$ and JADSTART $= 0$ to ensure that no conversion is ongoing. If required, stop any regular and injected conversion ongoing by setting ADSTP $= 1$ and JADSTP $= 1$ and then wait until ADSTP $= 0$ and JADSTP $= 0$ .

Set ADDIS.

If required by the application, wait until ADEN = 0 , until the analog ADC is effectively disabled (ADDIS is automatically reset once ADEN $= 0$ ).

21.4.10 Constraints when writing the ADC control bits

The software is allowed to write the RCC control bits to configure and enable the ADC clock (refer to RCC Section), the DIFSEL[i] control bits in the ADC_DIFSEL register and the control bits ADCAL and ADEN in the ADC_CR register, only if the ADC is disabled (ADEN must be equal to 0 ).

The software is then allowed to write the control bits ADSTART, JADSTART and ADDIS of the ADC_CR register only if the ADC is enabled and there is no pending request to disable the ADC (ADEN must be equal to 1 and ADDIS to 0 ).

For all the other control bits of the ADC_CFGR, ADC_SMPRx, ADC_TRy, ADC_SQRy, ADC_JDRy, ADC_OFRy, ADC_OFCHRy and ADC_IER registers:

For control bits related to configuration of regular conversions, the software is allowed to write them only if the ADC is enabled (ADEN = 1) and if there is no regular conversion ongoing (ADSTART must be equal to 0 ).

For control bits related to configuration of injected conversions, the software is allowed to write them only if the ADC is enabled (ADEN = 1) and if there is no injected conversion ongoing (JADSTART must be equal to 0 ).

ADC_TRy registers can be modified when an analog-to-digital conversion is ongoing (refer to Section 21.4.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)for details).

The software is allowed to write the ADSTP or JADSTP control bits of the ADC_CR register only if the ADC is enabled, possibly converting, and if there is no pending request to disable the ADC (ADSTART or JADSTART must be equal to 1 and ADDIS to 0 ).

The software can write the register ADC_JSQR at any time, when the ADC is enabled (ADEN = 1) and JADSTART is cleared. The software is allowed to modify on-the-fly the ADC_JSQR register when JADSTART is set (injected conversions are ongoing) only when the context queue is enabled (JQDIS

= 0

in the ADC_CFGR register). Refer to Section 21.7.16: ADC injected sequence register (ADC_JSQR) for additional details.

Note: There is no hardware protection to prevent these forbidden write accesses and ADC behavior may become in an unknown state. To recover from this situation, the ADC must be disabled (clear ADEN as well as all the bits of ADC_CR register).

21.4.11 Channel selection (SQRx, JSQRx)

There are up to 19 multiplexed channels per ADC:

Up to 13 slow analog inputs coming from GPIO pads (ADCx_INP/INN[6:18]) Depending on the products, not all of them are available on GPIO pads.

The ADCs are connected to the following internal analog inputs:

The internal reference voltage $(V_{REFINT})$ is connected to ADC1_INP18, ADC3_INP18, ADC4_INP18 and ADC5_INP18.

The internal temperature sensor $(V_{TS})$ is connected to $ADC 1_INP 16$ and ADC5_INP4.

The $V_{BAT}$ monitoring channel $(V_{BAT} / 3)$ is connected to ADC1_INP17, ADC3_INP17 and ADC5_INP17.

Note: To convert one of the internal analog channels, the corresponding analog sources must first be enabled by programming bits VREFEN, VBATSEL or VSENSESEL in the ADCx_CCR registers.

It is possible to organize the conversions in two groups: regular and injected. A group consists of a sequence of conversions that can be done on any channel and in any order. For instance, it is possible to implement the conversion sequence in the following order: ADCx_INP/INN3, ADCx_INP/INN8, ADCx_INP/INN2, ADCx_INN/INP2, ADCx_INP/INN0, ADCx_INP/INN2, ADCx_INP/INN2, ADCx_INP/INN15.

A regular group is composed of up to 16 conversions. The regular channels and their order in the conversion sequence must be selected in the ADC_SQRy registers. The total number of conversions in the regular group must be written in the L[3:0] bits in the ADC_SQR1 register.

An injected group is composed of up to 4 conversions. The injected channels and their order in the conversion sequence must be selected in the ADC_JSQR register. The total number of conversions in the injected group must be written in the L[1:0] bits in the ADC_JSQR register.

ADC_SQRy registers must not be modified while regular conversions can occur. For this, the ADC regular conversions must be first stopped by writing ADSTP = 1 (refer to Section 21.4.17: Stopping an ongoing conversion (ADSTP, JADSTP)).

The software is allowed to modify on-the-fly the ADC_JSQR register when JADSTART is set (injected conversions ongoing) only when the context queue is enabled (JQDIS = 0 in ADC_CFGR register). Refer to Section 21.4.21: Queue of context for injected conversions

21.4.12 Channel-wise programmable sampling time (SMPR1, SMPR2)

Before starting a conversion, the ADC must establish a direct connection between the voltage source under measurement and the embedded sampling capacitor of the ADC. This sampling time must be enough for the input voltage source to charge the embedded capacitor to the input voltage level.

Each channel can be sampled with a different sampling time which is programmable using the SMP[2:0] bits in the ADC_SMPR1 and ADC registers. It is therefore possible to select among the following sampling time values:

$SMP = 000 : 2.5 ADC$ clock cycles

SMP = 001: 6.5 ADC clock cycles

SMP = 010: 12.5 ADC clock cycles

SMP = 011: 24.5 ADC clock cycles

SMP = 100: 47.5 ADC clock cycles

SMP = 101: 92.5 ADC clock cycles

SMP = 110: 247.5 ADC clock cycles

SMP = 111: 640.5 ADC clock cycles

The total conversion time is calculated as follows:

T_{CONV} =

Sampling time +12.5 ADC clock cycles

Example:

With

F_{adc_ker_ck} = 30 MHz

and a sampling time of 2.5 ADC clock cycles:

T_{CONV} = (2.5 + 12.5) ADC

clock cycles

= 15 ADC

clock cycles

= 500 ns

The ADC notifies the end of the sampling phase by setting the status bit EOSMP (only for regular conversion).

Constraints on the sampling time

For each channel, SMP[2:0] bits must be programmed to respect a minimum sampling time as specified in the ADC characteristics section of the datasheets.

Bulb sampling mode

When the BULB bit is set in ADC register, the sampling period starts immediately after the last ADC conversion. A hardware or software trigger starts the conversion after the sampling time has been programmed in ADC_SMPR1 register. The very first ADC conversion, after the ADC is enabled, is performed with the sampling time programmed in SMP bits. The Bulb mode is effective starting from the second conversion.

The maximum sampling time is limited (refer to the ADC characteristics section of the datasheet).

The Bulb mode is neither compatible with the continuous conversion mode nor with the injected channel conversion.

When the BULB bit is set, it is not allowed to set SMPTRIG bit in ADC_CFGR2.

Figure 93. Bulb mode timing diagram

Sampling time control trigger mode

When the SMPTRIG bit is set, the sampling time programmed though SMPx bits is not applicable. The sampling time is controlled by the trigger signal edge.

When a hardware trigger is selected, each rising edge of the trigger signal starts the sampling period. A falling edge ends the sampling period and starts the conversion. The EXTEN[1:0] bits must be set to 01 . Hardware triggers with not defined rising and falling edges (one pulse event) cannot be used in Bulb mode.

When a software trigger is selected, the software trigger is not the ADSTART bit in ADC_CR but the SWTRIG bit. SWTRIG bit has to be set to start the sampling period, and the SWTRIG bit has to be cleared to end the sampling period and start the conversion. EXTEN[1:0] bits must be set to 00 .

The maximum sampling time is limited (refer to the ADC characteristics section of the datasheet).

This mode is neither compatible with the continuous conversion mode, nor with the injected channel conversion.

When SMPTRIG bit is set, it is not allowed to set BULB bit.

I/O analog switch voltage booster

The resistance of the I/O analog switches increases when the

V_{D D A}

voltage is too low. The sampling time must consequently be adapted accordingly (refer to the device datasheet for the corresponding electrical characteristics). This resistance can be minimized at low

V_{DDA}

voltage by enabling an internal voltage booster through the BOOSTEN bit of the SYSCFG_CFGR1 register.

SMPPLUS control bit

When a sampling time of 2.5 ADC clock cycles is selected, the total conversion time becomes 15 cycles in 12-bit mode. If the dual interleaved mode is used (see Section : Interleaved mode with independent injected), the sampling interval cannot be equal to the value specified since an even number of cycles is required for the conversion. The SMPPLUS bit can be used to change the sampling time 2.5 ADC clock cycles into 3.5 ADC clock cycles. In this way, the total conversion time becomes 16 clock cycles, thus making possible to interleave every 8 cycles.

21.4.13 Single conversion mode (CONT = 0)

In Single conversion mode, the ADC performs once all the conversions of the channels. This mode is started with the CONT bit at 0 by either:

Setting the ADSTART bit in the ADC_CR register (for a regular channel)

Setting the JADSTART bit in the ADC_CR register (for an injected channel)

External hardware trigger event (for a regular or injected channel)

Inside the regular sequence, after each conversion is complete:

The converted data are stored into the 16-bit ADC_DR register

The EOC (end of regular conversion) flag is set

An interrupt is generated if the EOCIE bit is set

Inside the injected sequence, after each conversion is complete:

The converted data are stored into one of the four 16-bit ADC_JDRy registers

The JEOC (end of injected conversion) flag is set

An interrupt is generated if the JEOCIE bit is set

After the regular sequence is complete:

The EOS (end of regular sequence) flag is set

An interrupt is generated if the EOSIE bit is set

After the injected sequence is complete:

The JEOS (end of injected sequence) flag is set

An interrupt is generated if the JEOSIE bit is set

Then the ADC stops until a new external regular or injected trigger occurs or until bit ADSTART or JADSTART is set again.

ote:

To convert a single channel,program a sequence with a length of 1.

21.4.14 Continuous conversion mode (CONT = 1)

This mode applies to regular channels only.

In continuous conversion mode, when a software or hardware regular trigger event occurs, the ADC performs once all the regular conversions of the channels and then automatically restarts and continuously converts each conversions of the sequence. This mode is started with the CONT bit at 1 either by external trigger or by setting the ADSTART bit in the

Inside the regular sequence, after each conversion is complete:

The converted data are stored into the 16-bit ADC_DR register

The EOC (end of conversion) flag is set

An interrupt is generated if the EOCIE bit is set

After the sequence of conversions is complete:

The EOS (end of sequence) flag is set

An interrupt is generated if the EOSIE bit is set

Then, a new sequence restarts immediately and the ADC continuously repeats the conversion sequence.

To convert a single channel, program a sequence with a length of 1.

It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1.

Injected channels cannot be converted continuously. The only exception is when an injected channel is configured to be converted automatically after regular channels in continuous mode (using JAUTO bit), refer to Auto-injection mode section).

21.4.15 Starting conversions (ADSTART, JADSTART)

Software starts ADC regular conversions by setting ADSTART = 1.

When ADSTART is set, the conversion starts:

Immediately: if EXTEN[1:0] = 00 (software trigger)

At the next active edge of the selected regular hardware trigger: if EXTEN[1:0] is not equal to 00

Software starts ADC injected conversions by setting JADSTART = 1.

When JADSTART is set, the conversion starts:

Immediately,if JEXTEN[1:0] = 00 (software trigger)

At the next active edge of the selected injected hardware trigger: if JEXTEN[1:0] is not equal to 00

Note: In auto-injection mode (JAUTO = 1), use ADSTART bit to start the regular conversions followed by the auto-injected conversions (JADSTART must be kept cleared).

ADSTART and JADSTART also provide information on whether any ADC operation is currently ongoing. It is possible to re-configure the ADC while ADSTART

= 0

and JADSTART

= 0

are both true,indicating that the ADC is idle.

ADSTART is cleared by hardware:

In single mode with software regular trigger (CONT = 0, EXTSEL = 0x0)

At any end of regular conversion sequence (EOS assertion) or at any end of subgroup processing if DISCEN = 1

In all cases (CONT=x, EXTSEL=x)

After execution of the ADSTP procedure asserted by the software.

Note: In continuous mode (CONT = 1), ADSTART is not cleared by hardware with the assertion of EOS because the sequence is automatically relaunched.

When a hardware trigger is selected in single mode (CONT = 0 and EXTSEL≠0x00), ADSTART is not cleared by hardware with the assertion of EOS to help the software which does not need to reset ADSTART again for the next hardware trigger event. This ensures that no further hardware triggers are missed.

JADSTART is cleared by hardware:

In single mode with software injected trigger (JEXTSEL = 0x0)

At any end of injected conversion sequence (JEOS assertion) or at any end of subgroup processing if JDISCEN = 1

in all cases (JEXTSEL=x)

After execution of the JADSTP procedure asserted by the software.

Note: When the software trigger is selected, ADSTART bit should not be set if the EOC flag is still high.

21.4.16 ADC timing

The elapsed time between the start of a conversion and the end of conversion is the sum of the configured sampling time plus the successive approximation time depending on data resolution:

T_{CONV} = T_{SMPL} + T_{SAR} = [2.5 Γ_{min} + 12.5 Γ_{12bit}] \times T_{ADC_CLK}

T_{CONV} = T_{SMPL} + T_{SAR} = 83.33 {ns}_{(min} + 416.67 {ns}_{∣ 12 bit} = 500.0 ns (for F_{ADC_CLK} = 30 MHz)

Figure 94. Analog-to-digital conversion time

$t_{SMPL}$ depends on $SMP [2 : 0]$ .

$t_{SAR}$ depends on RES[2:0].

21.4.17 Stopping an ongoing conversion (ADSTP, JADSTP)

The software can decide to stop regular conversions ongoing by setting ADSTP = 1 and injected conversions ongoing by setting JADSTP

= 1

Stopping conversions resets the ongoing ADC operation. Then the ADC can be reconfigured (ex: changing the channel selection or the trigger) ready for a new operation.

Note that it is possible to stop injected conversions while regular conversions are still operating and vice-versa. This allows, for instance, re-configuration of the injected conversion sequence and triggers while regular conversions are still operating (and vice-versa).

When the ADSTP bit is set by software, any ongoing regular conversion is aborted with partial result discarded (ADC_DR register is not updated with the current conversion).

When the JADSTP bit is set by software, any ongoing injected conversion is aborted with partial result discarded (ADC_JDRy register is not updated with the current conversion). The scan sequence is also aborted and reset (meaning that relaunching the ADC would restart a new sequence).

Once this procedure is complete, bits ADSTP/ADSTART (in case of regular conversion), or JADSTP/JADSTART (in case of injected conversion) are cleared by hardware and the software must poll ADSTART (or JADSTART) until the bit is reset before assuming the ADC is completely stopped.

21.4.18 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN)

A conversion or a sequence of conversions can be triggered either by software or by an external event (e.g. timer capture, input pins). If the EXTEN[1:0] control bits (for a regular conversion) or JEXTEN[1:0] bits (for an injected conversion) are different from 00 , then external events are able to trigger a conversion with the selected polarity.

When the Injected Queue is enabled (bit JQDIS = 0), injected software triggers are not possible.

The regular trigger selection is effective once software has set bit ADSTART = 1 and the injected trigger selection is effective once software has set bit JADSTART = 1.

Any hardware triggers which occur while a conversion is ongoing are ignored.

If bit ADSTART $= 0$ ,any regular hardware triggers which occur are ignored.

If bit JADSTART = 0, any injected hardware triggers which occur are ignored.

Table 161 provides the correspondence between the EXTEN[1:0] and JEXTEN[1:0] values and the trigger polarity.

Table 161. Configuring the trigger polarity for regular external triggers

EXTEN[1:0]	Source
00	Hardware Trigger detection disabled, software trigger detection enabled
01	Hardware Trigger with detection on the rising edge
10	Hardware Trigger with detection on the falling edge
11	Hardware Trigger with detection on both the rising and falling edges

Note: The polarity of the regular trigger cannot be changed on-the-fly.

Table 162. Configuring the trigger polarity for injected external triggers

JEXTEN[1:0]	Source
00	– If JQDIS = 1 (Queue disabled): Hardware trigger detection disabled, software trigger detection enabled – If JQDIS = 0 (Queue enabled), Hardware and software trigger detection disabled
01	Hardware Trigger with detection on the rising edge
10	Hardware Trigger with detection on the falling edge
11	Hardware Trigger with detection on both the rising and falling edges

Note: The polarity of the injected trigger can be anticipated and changed on-the-fly when the queue is enabled (JQDIS = 0). Refer to Section 21.4.21: Queue of context for injected conversions.

The EXTSEL and JEXTSEL control bits select which out of 32 possible events can trigger conversion for the regular and injected groups.

A regular group conversion can be interrupted by an injected trigger.

Note: The regular trigger selection cannot be changed on-the-fly.

The injected trigger selection can be anticipated and changed on-the-fly. Refer to

Section 21.4.21: Queue of context for injected conversions on page 624

Each ADC master shares the same input triggers with its ADC slave as described in Figure 97.

Figure 97. Triggers sharing between ADC master and ADC slave

Table 163 to Table 166 give all the possible external triggers of the three ADCs for regular and injected conversions.

Table 163. ADC1/2 - External triggers for regular channels

Name	Source	Type	EXTSEL[4:0]
adc_ext_trg	tim1_oc1	Internal signal from on-chip timers	00000
adc_ext_trg1	tim1_oc2	Internal signal from on-chip timers	00001
adc_ext_trg2	tim1_oc3	Internal signal from on-chip timers	00010
adc_ext_trg3	tim2_oc2	Internal signal from on-chip timers	00011
adc_ext_trg4	tim3_trgo	Internal signal from on-chip timers	00100
adc_ext_trg5	tim4_oc4	Internal signal from on-chip timers	00101
adc_ext_trg6	EXTI line 11	External pin	00110
adc_ext_trg7	tim8_trgo	Internal signal from on-chip timers	00111
adc_ext_trg8	tim8_trgo2	Internal signal from on-chip timers	01000

Table 163. ADC1/2 - External triggers for regular channels (continued)

Name	Source	Type	EXTSEL[4:0]
adc_ext_trg9	tim1_trgo	Internal signal from on-chip timers	01001
adc_ext_trg10	tim1_trgo2	Internal signal from on-chip timers	01010
adc_ext_trg11	tim2_trgo	Internal signal from on-chip timers	01011
adc_ext_trg12	tim4_trgo	Internal signal from on-chip timers	01100
adc_ext_trg13	tim6_trgo	Internal signal from on-chip timers	01101
adc_ext_trg14	tim15_trgo	Internal signal from on-chip timers	01110
adc_ext_trg15	tim3_oc4	Internal signal from on-chip timers	01111
adc_ext_trg16	tim20_trgo	Internal signal from on-chip timers	10000
adc_ext_trg17	tim20_trgo2	Internal signal from on-chip timers	10001
adc_ext_trg18	tim20_oc1	Internal signal from on-chip timers	10010
adc_ext_trg19	tim20_oc2	Internal signal from on-chip timers	10011
adc_ext_trg20	tim20_oc3	Internal signal from on-chip timers	10100
adc_ext_trg21	hrtim_adc_trg1	Internal signal from on-chip timers	10101
adc_ext_trg22	hrtim_adc_trg3	Internal signal from on-chip timers	10110
adc_ext_trg23	hrtim_adc_trg5	Internal signal from on-chip timers	10111
adc_ext_trg24	hrtim_adc_trg6	Internal signal from on-chip timers	11000
adc_ext_trg25	hrtim_adc_trg7	Internal signal from on-chip timers	11001
adc_ext_trg26	hrtim_adc_trg8	Internal signal from on-chip timers	11010
adc_ext_trg27	hrtim_adc_trg9	Internal signal from on-chip timers	11011
adc_ext_trg28	hrtim_adc_trg10	Internal signal from on-chip timers	11100
adc_ext_trg29	lptim_out	Internal signal from on-chip timers	11101
adc_ext_trg30	tim7_trgo	Internal signal from on-chip timers	11110
adc_ext_trg31	reserved	-	111111

Table 164. ADC1/2 - External trigger for injected channels

Name	Source	Type	JEXTSEL[4:0]
adc_jext_trg0	tim1_trgo	Internal signal from on-chip timers	00000
adc_jext_trg1	tim1_oc4	Internal signal from on-chip timers	00001
adc_jext_trg2	tim2_trgo	Internal signal from on-chip timers	00010
adc_jext_trg3	tim2_oc1	Internal signal from on-chip timers	00011
adc_jext_trg4	tim3_oc4	Internal signal from on-chip timers	00100
adc_jext_trg5	tim4_trgo	Internal signal from on-chip timers	00101
adc_jext_trg6	EXTI line 15	External pin	00110
adc_jext_trg7	tim8_oc4	Internal signal from on-chip timers	00111
adc_jext_trg8	tim1_trgo2	Internal signal from on-chip timers	01000

Table 164. ADC1/2 - External trigger for injected channels (continued)

Name	Source	Type	JEXTSEL[4:0]
adc_jext_trg9	tim8_trgo	Internal signal from on-chip timers	01001
adc_jext_trg10	tim8_trgo2	Internal signal from on-chip timers	01010
adc_jext_trg11	tim3_oc3	Internal signal from on-chip timers	01011
adc_jext_trg12	tim3_trgo	Internal signal from on-chip timers	01100
adc_jext_trg13	tim3_oc1	Internal signal from on-chip timers	01101
adc_jext_trg14	tim6_trgo	Internal signal from on-chip timers	01110
adc_jext_trg15	tim15_trgo	Internal signal from on-chip timers	01111
adc_jext_trg16	tim20_trgo	Internal signal from on-chip timers	10000
adc_jext_trg17	tim20_trgo2	Internal signal from on-chip timers	10001
adc_jext_trg18	tim20_oc4	Internal signal from on-chip timers	10010
adc_jext_trg19	hrtim_adc_trg2	Internal signal from on-chip timers	10011
adc_jext_trg20	hrtim_adc_trg4	Internal signal from on-chip timers	10100
adc_jext_trg21	hrtim_adc_trg5	Internal signal from on-chip timers	10101
adc_jext_trg22	hrtim_adc_trg6	Internal signal from on-chip timers	10110
adc_jext_trg23	hrtim_adc_trg7	Internal signal from on-chip timers	10111
adc_jext_trg24	hrtim_adc_trg8	Internal signal from on-chip timers	11000
adc_jext_trg25	hrtim_adc_trg9	Internal signal from on-chip timers	11001
adc_jext_trg26	hrtim_adc_trg10	Internal signal from on-chip timers	11010
adc_jext_trg27	tim16_oc1	Internal signal from on-chip timers	11011
adc_jext_trg28	reserved	-	11100
adc_iext_trg29	lptim_out	Internal signal from on-chip timers	11101
adc_jext_trg30	tim7_trgo	Internal signal from on-chip timers	11110
adc_jext_trg31	reserved	-	111111

Table 165. ADC3/4/5 - External triggers for regular channels

Name	Source	Type	EXTSEL[4:0]
adc_ext_trg0	tim3_oc1	Internal signal from on-chip timers	00000
adc_ext_trg1	tim2_oc3	Internal signal from on-chip timers	00001
adc_ext_trg2	tim1_oc3	Internal signal from on-chip timers	00010
adc_ext_trg3	tim8_oc1	Internal signal from on-chip timers	00011
adc_ext_trg4	tim3_trgo	Internal signal from on-chip timers	00100
adc_ext_trg5	EXTI line 2	External pin	00101
adc_ext_trg6	tim4_oc1	Internal signal from on-chip timers	00110
adc_ext_trg7	tim8_trgo	Internal signal from on-chip timers	00111

Table 165. ADC3/4/5 - External triggers for regular channels (continued)

Name	Source	Type	EXTSEL[4:0]
adc_ext_trg8	tim8_trgo2	Internal signal from on-chip timers	01000
adc_ext_trg9	tim1_trgo	Internal signal from on-chip timers	01001
adc_ext_trg10	tim1_trgo2	Internal signal from on-chip timers	01010
adc_ext_trg11	tim2_trgo	Internal signal from on-chip timers	01011
adc_ext_trg12	tim4_trgo	Internal signal from on-chip timers	01100
adc_ext_trg13	tim6_trgo	Internal signal from on-chip timers	01101
adc_ext_trg14	tim15_trgo	Internal signal from on-chip timers	01110
adc_ext_trg15	tim2_oc1	Internal signal from on-chip timers	01111
adc_ext_trg16	tim20_trgo	Internal signal from on-chip timers	10000
adc_ext_trg17	tim20_trgo2	Internal signal from on-chip timers	10001
adc_ext_trg18	tim20_oc1	Internal signal from on-chip timers	10010
adc_ext_trg19	hrtim_adc_trg2	Internal signal from on-chip timers	10011
adc_ext_trg20	hrtim_adc_trg4	Internal signal from on-chip timers	10100
adc_ext_trg21	hrtim_adc_trg1	Internal signal from on-chip timers	10101
adc_ext_trg22	hrtim_adc_trg3	Internal signal from on-chip timers	10110
adc_ext_trg23	hrtim_adc_trg5	Internal signal from on-chip timers	10111
adc_ext_trg24	hrtim_adc_trg6	Internal signal from on-chip timers	11000
adc_ext_trg25	hrtim_adc_trg7	Internal signal from on-chip timers	11001
adc_ext_trg26	hrtim_adc_trg8	Internal signal from on-chip timers	11010
adc_ext_trg27	hrtim_adc_trg9	Internal signal from on-chip timers	11011
adc_ext_trg28	hrtim_adc_trg10	Internal signal from on-chip timers	11100
adc_ext_trg29	lptim_out	Internal signal from on-chip timers	11101
adc_ext_trg30	tim7_trgo	Internal signal from on-chip timers	11110
adc_ext_trg31	reserved	-	11111

Table 166. ADC3/4/5 - External triggers for injected channels

Name	Source	Type	JEXTSEL[4:0]
adc_jext_trg0	tim1_trgo	Internal signal from on-chip timers	00000
adc_jext_trg1	tim1_oc4	Internal signal from on-chip timers	00001
adc_jext_trg2	tim2_trgo	Internal signal from on-chip timers	00010
adc_jext_trg3	tim8_oc2	Internal signal from on-chip timers	00011
adc_jext_trg4	tim4_oc3	Internal signal from on-chip timers	00100
adc_jext_trg5	tim4_trgo	Internal signal from on-chip timers	00101
adc_jext_trg6	tim4_oc4	Internal signal from on-chip timers	00110
adc_jext_trg7	tim8_oc4	Internal signal from on-chip timers	00111

Table 166. ADC3/4/5 - External triggers for injected channels (continued)

Name	Source	Type	JEXTSEL[4:0]
adc_jext_trg8	tim1_trgo2	Internal signal from on-chip timers	01000
adc_jext_trg9	tim8_trgo	Internal signal from on-chip timers	01001
adc_jext_trg10	tim8_trgo2	Internal signal from on-chip timers	01010
adc_jext_trg11	tim1_oc3	Internal signal from on-chip timers	01011
adc_jext_trg12	tim3_trgo	Internal signal from on-chip timers	01100
adc_jext_trg13	EXTI line 3	External pin	01101
adc_jext_trg14	tim6_trgo	Internal signal from on-chip timers	01110
adc_jext_trg15	tim15_trgo	Internal signal from on-chip timers	01111
adc_jext_trg16	tim20_trgo	Internal signal from on-chip timers	10000
adc_jext_trg17	tim20_trgo2	Internal signal from on-chip timers	10001
adc_jext_trg18	tim20_oc2	Internal signal from on-chip timers	10010
adc_jext_trg19	hrtim_adc_trg2	Internal signal from on-chip timers	10011
adc_jext_trg20	hrtim_adc_trg4	Internal signal from on-chip timers	10100
adc_jext_trg21	hrtim_adc_trg5	Internal signal from on-chip timers	10101
adc_jext_trg22	hrtim_adc_trg6	Internal signal from on-chip timers	10110
adc_jext_trg23	hrtim_adc_trg7	Internal signal from on-chip timers	10111
adc_jext_trg24	hrtim_adc_trg8	Internal signal from on-chip timers	11000
adc_jext_trg25	hrtim_adc_trg9	Internal signal from on-chip timers	11001
adc_jext_trg26	hrtim_adc_trg10	Internal signal from on-chip timers	11010
adc_jext_trg27	hrtim_adc_trg1	Internal signal from on-chip timers	11011
adc_jext_trg28	hrtim_adc_trg3	Internal signal from on-chip timers	11100
adc_jext_trg29	lptim_out	Internal signal from on-chip timers	11101
adc_jext_trg30	tim7_trgo	Internal signal from on-chip timers	11110
adc_jext_trg31	reserved	-	111111

21.4.19 Injected channel management

Triggered injection mode

To use triggered injection, the JAUTO bit in the ADC_CFGR register must be cleared.

Start the conversion of a group of regular channels either by an external trigger or by setting the ADSTART bit in the ADC_CR register.

If an external injected trigger occurs, or if the JADSTART bit in the ADC_CR register is set during the conversion of a regular group of channels, the current conversion is

	reset and the injected channel sequence switches are launched (all the injected channels are converted once).
	3. Then, the regular conversion of the regular group of channels is resumed from the las interrupted regular conversion.
	4. If a regular event occurs during an injected conversion, the injected conversion is not interrupted but the regular sequence is executed at the end of the injected sequence. Figure 98 shows the corresponding timing diagram.
Note:	When using triggered injection, one must ensure that the interval between trigger events is longer than the injection sequence. For instance, if the sequence length is 30 ADC cloud is a first real constant. cycles (that is two conversions with a sampling time of 2.5 clock periods), the minimum interval between triggers must be 31 ADC clock cycles.
	Auto-injection mode
	If the JAUTO bit in the ADC_CFGR register is set, then the channels in the injected group are automatically converted after the regular group of channels. This can be used to converted to converge to the convergence. a sequence of up to 20 conversions programmed in the ADC_SQRy and ADC_JSQR registers.
	In this mode, the ADSTART bit in the ADC_CR register must be set to start regula conversions, followed by injected conversions (JADSTART must be kept cleared). Se the ADSTP bit aborts both regular and injected conversions (JADSTP bit must not be used)
	In this mode, external trigger on injected channels must be disabled
	if the CONT bit is also set in addition to the JAUTO bit, regular channels followed by injecte channels are continuously converted.
Note:	It is not possible to use both the auto-injected and discontinuous modes simultaneously.
	When the DMA is used for exporting regular sequencer’s data in JAUTO mode, it is necessary to program it in circular mode (CIRC bit set in DMA_CCRx register). If the CIF bit is reset (single-shot mode), the JAUTO sequence is stopped upon DMA Transfer Complete event.

The maximum latency value can be found in the electrical characteristics of the device datasheet.

21.4.20 Discontinuous mode (DISCEN, DISCNUM, JDISCEN)

Regular group mode

This mode is enabled by setting the DISCEN bit in the ADC_CFGR register.

It is used to convert a short sequence (subgroup) of

n

conversions

(n \leq 8)

that is part of the sequence of conversions selected in the ADC_SQRy registers. The value of

n

is specified by writing to the DISCNUM[2:0] bits in the ADC_CFGR register.

When an external trigger occurs, it starts the next

n

conversions selected in the ADC_SQRy registers until all the conversions in the sequence are done. The total sequence length is defined by the L[3:0] bits in the ADC_SQR1 register.

Example:

DISCEN $= 1, n = 3$ ,channels to be converted $= 1, 2, 3, 6, 7, 8, 9, 10, 11$

first trigger: channels converted are $1, 2, 3$ (an EOC event is generated at each conversion).

second trigger: channels converted are 6,7,8 (an EOC event is generated at each conversion).

third trigger: channels converted are 9,10,11 (an EOC event is generated at each conversion) and an EOS event is generated after the conversion of channel 11.

fourth trigger: channels converted are 1, 2, 3 (an EOC event is generated at each conversion). $- \dots$

DISCEN $= 0$ ,channels to be converted $= 1, 2, 3, 6, 7, 8, 9, 10, 11$

first trigger: the complete sequence is converted: channel 1, then 2, 3, 6, 7, 8, 9, 10 and 11. Each conversion generates an EOC event and the last one also generates an EOS event.

All the next trigger events relaunch the complete sequence.

Note: The channel numbers referred to in the above example might not be available on all microcontrollers.

When a regular group is converted in discontinuous mode, no rollover occurs (the last subgroup of the sequence can have less than

n

conversions).

When all subgroups are converted, the next trigger starts the conversion of the first subgroup. In the example above, the fourth trigger reconverts the channels 1,2 and 3 in the first subgroup.

It is not possible to have both discontinuous mode and continuous mode enabled. In this case (if DISCEN = 1, CONT = 1), the ADC behaves as if continuous mode was disabled.

Injected group mode

This mode is enabled by setting the JDISCEN bit in the ADC_CFGR register. It converts the sequence selected in the ADC_JSQR register, channel by channel, after an external injected trigger event. This is equivalent to discontinuous mode for regular channels where ’

n

’ is fixed to 1 .

When an external trigger occurs, it starts the next channel conversions selected in the ADC_JSQR registers until all the conversions in the sequence are done. The total sequence length is defined by the JL[1:0] bits in the ADC_JSQR register. Example:

JDISCEN $= 1$ ,channels to be converted $= 1, 2, 3$

first trigger: channel 1 converted (a JEOC event is generated) - second trigger: channel 2 converted (a JEOC event is generated) - third trigger: channel 3 converted and a JEOC event + a JEOS event are generated - ...

Note: The channel numbers referred to in the above example might not be available on all microcontrollers.

When all injected channels have been converted, the next trigger starts the conversion of the first injected channel. In the example above, the fourth trigger reconverts the first injected channel 1.

It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set.

21.4.21 Queue of context for injected conversions

A queue of context is implemented to anticipate up to 2 contexts for the next injected sequence of conversions. JQDIS bit of ADC_CFGR register must be reset to enable this feature. Only hardware-triggered conversions are possible when the context queue is enabled.

This context consists of:

Configuration of the injected triggers (bits JEXTEN[1:0] and JEXTSEL bits in ADC_JSQR register)

Definition of the injected sequence (bits JSQx[4:0] and JL[1:0] in ADC_JSQR register)

All the parameters of the context are defined into a single register ADC_JSQR and this register implements a queue of 2 buffers, allowing the bufferization of up to 2 sets of parameters:

The JSQR register can be written at any moment even when injected conversions are ongoing.

Each data written into the JSQR register is stored into the Queue of context.

At the beginning, the Queue is empty and the first write access into the JSQR register immediately changes the context and the ADC is ready to receive injected triggers.

Once an injected sequence is complete, the Queue is consumed and the context changes according to the next JSQR parameters stored in the Queue. This new context is applied for the next injected sequence of conversions.

A Queue overflow occurs when writing into register JSQR while the Queue is full. This overflow is signaled by the assertion of the flag JQOVF. When an overflow occurs, the write access of JSQR register which has created the overflow is ignored and the queue of context is unchanged. An interrupt can be generated if bit JQOVFIE is set.

Two possible behaviors are possible when the Queue becomes empty, depending on the value of the control bit JQM of register ADC_CFGR:

If JQM = 0, the Queue is empty just after enabling the ADC, but then it can never be empty during run operations: the Queue always maintains the last active context and any further valid start of injected sequence is served according to the last active context.

If JQM = 1, the Queue can be empty after the end of an injected sequence or if the Queue is flushed. When this occurs, there is no more context in the queue and hardware triggers are disabled. Therefore, any further hardware injected triggers are ignored until the software re-writes a new injected context into JSQR register.

Reading JSQR register returns the current JSQR context which is active at that moment. When the JSQR context is empty, JSQR is read as 0x0000.

The Queue is flushed when stopping injected conversions by setting JADSTP = 1 or when disabling the ADC by setting ADDIS = 1:

If JQM = 0, the Queue is maintained with the last active context.

If JQM = 1, the Queue becomes empty and triggers are ignored.

Note: When configured in discontinuous mode (bit JDISCEN = 1), only the last trigger of the injected sequence changes the context and consumes the Queue. The first trigger only consumes the queue but others are still valid triggers as shown by the discontinuous mode example below (length

= 3

for both contexts):

$1^{st}$ trigger,discontinuous. Sequence 1: context 1 consumed, $1^{st}$ conversion carried out

$2^{n d}$ trigger,discontinuous. Sequence 1: $2^{n d}$ conversion.

$3^{r d}$ trigger,discontinuous. Sequence 1: $3^{r d}$ conversion.

4th trigger,discontinuous. Sequence 2: context 2 consumed, $1^{s t}$ conversion carried out.

$5^{th}$ trigger,discontinuous. Sequence 2: $2^{nd}$ conversion.

$6^{th}$ trigger,discontinuous. Sequence 2: $3^{rd}$ conversion.

Queue of context: Behavior when a queue overflow occurs

The Figure 101 and Figure 102 show the behavior of the context Queue if an overflow occurs before or during a conversion.

Figure 101. Example of JSQR queue of context with overflow before conversion

Parameters:

P1: sequence of 2 conversions, hardware trigger 1

P2: sequence of 1 conversion, hardware trigger 2

P3: sequence of 3 conversions, hardware trigger 1

P4: sequence of 4 conversions, hardware trigger 1

Figure 102. Example of JSQR queue of context with overflow during conversion

Parameters:

P1: sequence of 2 conversions, hardware trigger 1

P3: sequence of 3 conversions, hardware trigger 1

P4: sequence of 4 conversions, hardware trigger 1

It is recommended to manage the queue overflows as described below:

After each $P$ context write into JSQR register,flag JQOVF shows if the write has been ignored or not (an interrupt can be generated).

Avoid Queue overflows by writing the third context (P3) only once the flag JEOS of the previous context $P 2$ has been set. This ensures that the previous context has been consumed and that the queue is not full.

Queue of context: Behavior when the queue becomes empty

Figure 103 and Figure 104 show the behavior of the context Queue when the Queue

becomes empty in both cases JQM

= 0

or 1 .

Figure 103. Example of JSQR queue of context with empty queue (case JQM = 0)

Parameters:

P1: sequence of 1 conversion, hardware trigger 1

P2: sequence of 1 conversion, hardware trigger 1

P3: sequence of 1 conversion, hardware trigger 1

Note: When writing P3, the context changes immediately. However, because of internal resynchronization, there is a latency and if a trigger occurs just after or before writing P3, it can happen that the conversion is launched considering the context P2. To avoid this situation, the user must ensure that there is no ADC trigger happening when writing a new context that applies immediately.

Figure 110. Flushing JSQR queue of context by setting ADDIS

= 1 (JQM = 1)

MS30547V1

Parameters:

P1: sequence of 1 conversion, hardware trigger 1

P2: sequence of 1 conversion, hardware trigger 1

P3: sequence of 1 conversion, hardware trigger 1

Queue of context: Starting the ADC with an empty queue

The following procedure must be followed to start ADC operation with an empty queue, in case the first context is not known at the time the ADC is initialized. This procedure is only applicable when JQM bit is reset:

Write a dummy JSQR with JEXTEN[1:0] not equal to 00 (otherwise triggering a software conversion).

Set JADSTART.

Set JADSTP.

Wait until JADSTART is reset.

Set JADSTART.

Disabling the queue

It is possible to disable the queue by setting bit JQDIS = 1 into the ADC_CFGR register.

21.4.22 Programmable resolution (RES) Fast conversion mode

It is possible to perform faster conversion by reducing the ADC resolution.

The resolution can be configured to be either

12, 10, 8

,or 6 bits by programming the control bits RES[1:0]. Figure 115, Figure 116, Figure 117 and Figure 118 show the conversion result format with respect to the resolution as well as to the data alignment.

Lower resolution allows faster conversion time for applications where high-data precision is not required. It reduces the conversion time spent by the successive approximation steps according to Table 167.

Table 167.

T_{S A R}

timings depending on resolution

RES (bits)	$T_{SAR}$ (ADC clock cycles)	Tsar (ns) at $F_{ADC} = 30 MHz$	$τ_{conv}$ (ADC clock cycles) (with Sampling Time= 2.5 ADC clock cycles)	Tconv (ns) at $F_{ADC} = 30 MHz$
12	12.5 ADC clock cycles	416.67 ns	15 ADC clock cycles	500.0 ns
10	10.5 ADC clock cycles	350.0 ns	13 ADC clock cycles	433.33 ns
8	8.5 ADC clock cycles	203.33 ns	11 ADC clock cycles	366.67 ns
6	6.5 ADC clock cycles	216.67 ns	9 ADC clock cycles	300.0 ns

21.4.23 End of conversion, end of sampling phase (EOC, JEOC, EOSMP)

The ADC notifies the application for each end of regular conversion (EOC) event and each injected conversion (JEOC) event.

The ADC sets the EOC flag as soon as a new regular conversion data is available in the ADC_DR register. An interrupt can be generated if bit EOCIE is set. EOC flag is cleared by the software either by writing 1 to it or by reading ADC_DR.

The ADC sets the JEOC flag as soon as a new injected conversion data is available in one of the ADC_JDRy register. An interrupt can be generated if bit JEOCIE is set. JEOC flag is cleared by the software either by writing 1 to it or by reading the corresponding ADC_JDRy register.

The ADC also notifies the end of Sampling phase by setting the status bit EOSMP (for regular conversions only). EOSMP flag is cleared by software by writing 1 to it. An interrupt can be generated if bit EOSMPIE is set.

21.4.24 End of conversion sequence (EOS, JEOS)

The ADC notifies the application for each end of regular sequence (EOS) and for each end of injected sequence (JEOS) event.

The ADC sets the EOS flag as soon as the last data of the regular conversion sequence is available in the ADC_DR register. An interrupt can be generated if bit EOSIE is set. EOS flag is cleared by the software either by writing 1 to it.

The ADC sets the JEOS flag as soon as the last data of the injected conversion sequence is complete. An interrupt can be generated if bit JEOSIE is set. JEOS flag is cleared by the software either by writing 1 to it.

21.4.26 Data management

	Data register, data alignment and offset (ADC_DR, OFFSETy, OFFSETy_CH, ALIGN)
	Data and alignment
	At the end of each regular conversion channel (when EOC event occurs), the result of the converted data is stored into the ADC_DR data register which is 16 bits wide.
	At the end of each injected conversion channel (when JEOC event occurs), the result converted data is stored into the corresponding ADC_JDRy data register which is 16 bits wide.
	The ALIGN bit in the ADC_CFGR register selects the alignment of the data stored a conversion. Data can be right- or left-aligned as shown in Figure 115, Figure 116, Figure 11 and Figure 118.
	Special case: when left-aligned, the data are aligned on a half-word basis except when the resolution is set to 6-bit. In that case, the data are aligned on a byte basis as shown in Figure 117 and Figure 118.
Note:	Left -alignment is not supported in oversampling mode. When ROVSE and/or JOVSE bit is set, the ALIGN bit value is ignored and the ADC only provides right-aligned data.
	Offset
	An offset y (y = 1,2,3,4) can be applied to a channel by setting the bit OFFSETy_EN = 1 into ADC_OFRy register. The channel to which the offset is applied is programmed into the bits OFFSETy_CH[4:0] of ADC_OFRy register. In this case, the converted value is decreased by the user-defined offset written in the bits OFFSETy[11:0]. The result may be a negativ value so the read data is signed and the SEXT bit represents the extended sign value.
Note:	Offset correction is not supported in oversampling mode. When ROVSE and/or JOVSE bit i set, the value of the OFFSETy_EN bit in ADC_OFRy register is ignored (considered as reset).
	Table 170 describes how the comparison is performed for all the possible resolutions for analog watchdog 1.

Table 168. Offset computation versus data resolution

Resolution (bits RES[1:0])	Subtraction between raw converted data and offset		Result	Comments
Resolution (bits RES[1:0])	Raw converted Data, left aligned	Offset	Result	Comments
00: 12-bit	DATA[11:0]	OFFSET[11:0]	Signed 12-bit data	-
01: 10-bit	DATA[11:2],00	OFFSET[11:0]	Signed 10-bit data	The user must configure OFFSET[1:0] to 00

Table 168. Offset computation versus data resolution (continued)

Resolution (bits RES[1:0])	Subtraction between raw converted data and offset		Result	Comments
Resolution (bits RES[1:0])	Raw converted Data, left aligned	Offset	Result	Comments
10: 8-bit	DATA[11:4],00 00	OFFSET[11:0]	Signed 8-bit data	The user must configure OFFSET[3:0] to 0000
11: 6-bit	DATA[11:6],00 0000	OFFSET[11:0]	Signed 6-bit data	The user must configure OFFSET[5:0] to 000000

When reading data from ADC_DR (regular channel) or from ADC_JDRy (injected channel, y

= 1, 2, 3, 4)

corresponding to the channel "i":

If one of the offsets is enabled (bit OFFSETy_EN = 1) for the corresponding channel, the read data is signed.

If none of the four offsets is enabled for this channel, the read data is not signed.

Figure 115, Figure 116, Figure 117 and Figure 118 show alignments for signed and unsigned data.

Figure 115. Right alignment (offset disabled, unsigned value)

Figure 118. Left alignment (offset enabled, signed value)

Gain compensation

When GCOMP bit is set in ADC_CFGR2 register, the gain compensation is activated on all the converted data. After each conversion, data is calculated with the following formula.

DATA = DATA(adc result) × (GCOMPCOEFF)/ 4096

As GCOMPCOEFF can be programmed from 0 to 16383 , the actual gain compensation factor can range from 0 to 3.999756 .

Before storing the resulting data in RDATA or JDATAx registers, the LSB-1 value is evaluated to round up the data and minimize the error.

The gain compensation is also effective for the oversampling. When the gain compensation is used for the oversampling mode, the gain calculation is performed after the accumulation and right-shift operations to minimize the power consumption (the gain calculation is done only once instead of at each conversion).

Offset compensation

When SATEN bit is set in ADC_OFRy register during offset operation, data are unsigned. All the offset data saturate at

0 \times 000

(in 12-bit mode). When OFFSETPOS bit is set,the offset direction is positive and the data saturate at 0xFFF (in 12-bit mode). In 8-bit mode, data saturate at

0 \times 00

and

0 \times FF

,respectively.

The analog watchdog comparison is performed on unsigned values, after offset and gain compensation. For correct watchdog operation, the data after offset compensation must be in unsigned format (SATEN bit set in ADC_OFRy register).

ADC overrun (OVR, OVRMOD)

The overrun flag (OSR) notifies of that a buffer overrun event occurred when the regular converted data has not been read (by the CPU or the DMA) before new converted data became available.

The OVR flag is set if the EOC flag is still 1 at the time when a new conversion completes. An interrupt can be generated if bit OVRIE

= 1

When an overrun condition occurs, the ADC is still operating and can continue converting unless the software decides to stop and reset the sequence by setting bit ADSTP = 1 .

OVR flag is cleared by software by writing 1 to it.

It is possible to configure if data is preserved or overwritten when an overrun event occurs by programming the control bit OVRMOD:

OVRMOD $= 0$ : The overrun event preserves the data register from being overrun: the old data is maintained and the new conversion is discarded and lost. If OVR remains at 1 , any further conversions occur but the result data is also discarded.

OVRMOD = 1: The data register is overwritten with the last conversion result and the previous unread data is lost. If OVR remains at 1 , any further conversions operate normally and the ADC_DR register always contains the latest converted data.

Figure 119. Example of overrun (OVR)

Note: There is no overrun detection on the injected channels since there is a dedicated data register for each of the four injected channels.

Managing a sequence of conversions without using the DMA

If the conversions are slow enough, the conversion sequence can be handled by the software. In this case the software must use the EOC flag and its associated interrupt to handle each data. Each time a conversion is complete, EOC is set and the ADC_DR register can be read. OVRMOD should be configured to 0 to manage overrun events as an error.

Managing conversions without using the DMA and without overrun

It may be useful to let the ADC convert one or more channels without reading the data each time (if there is an analog watchdog for instance). In this case, the OVRMOD bit must be configured to 1 and OVR flag should be ignored by the software. An overrun event does not prevent the ADC from continuing to convert and the ADC_DR register always contains the latest conversion.

Managing conversions using the DMA

Since converted channel values are stored into a unique data register, it is useful to use DMA for conversion of more than one channel. This avoids the loss of the data already stored in the ADC_DR register.

When the DMA mode is enabled (DMAEN bit set in the ADC_CFGR register in single ADC mode or MDMA different from 00 in dual ADC mode), a DMA request is generated after each conversion of a channel. This allows the transfer of the converted data from the ADC_DR register to the destination location selected by the software.

Despite this,if an overrun occurs

(OVR = 1)

because the DMA could not serve the DMA transfer request in time, the ADC stops generating DMA requests and the data corresponding to the new conversion is not transferred by the DMA. Which means that all the data transferred to the RAM can be considered as valid.

Depending on the configuration of OVRMOD bit, the data is either preserved or overwritten (refer to Section : ADC overrun (OVR, OVRMOD)).

The DMA transfer requests are blocked until the software clears the OVR bit.

Two different DMA modes are proposed depending on the application use and are configured with bit DMACFG of the ADC_CFGR register in single ADC mode, or with bit

DMACFG of the ADC_CCR register in dual ADC mode:

DMA one shot mode (DMACFG = 0).

This mode is suitable when the DMA is programmed to transfer a fixed number of data.

DMA circular mode (DMACFG = 1)

This mode is suitable when programming the DMA in circular mode.

DMA one shot mode (DMACFG = 0)

In this mode, the ADC generates a DMA transfer request each time a new conversion data is available and stops generating DMA requests once the DMA has reached the last DMA transfer (when a transfer complete interrupt occurs - refer to DMA section) even if a conversion has been started again.

When the DMA transfer is complete (all the transfers configured in the DMA controller have been done):

The content of the ADC data register is frozen.

Any ongoing conversion is aborted with partial result discarded.

No new DMA request is issued to the DMA controller. This avoids generating an overrun error if there are still conversions which are started.

Scan sequence is stopped and reset.

The DMA is stopped.

	DMA circular mode (DMACFG = 1)
	In this mode, the ADC generates a DMA transfer request each time a new conversion data is available in the data register, even if the DMA has reached the last DMA transfer. This allows configuring the DMA in circular mode to handle a continuous analog input data stream.
21.4.27	Dynamic low-power features
	Auto-delayed conversion mode (AUTDLY)
	The ADC implements an auto-delayed conversion mode controlled by the AUTDLY configuration bit. Auto-delayed conversions are useful to simplify the software as well as to optimize performance of an application clocked at low frequency where there would be risk of encountering an ADC overrun.
	When AUTDLY = 1, a new conversion can start only if all the previous data of the same group has been treated:
	For a regular conversion: once the ADC_DR register has been read or if the EOC bi has been cleared (see Figure 120).
	- For an injected conversion: when the JEOS bit has been cleared (see Figure 121).
	This is a way to automatically adapt the speed of the ADC to the speed of the system which reads the data.
	The delay is inserted after each regular conversion (whatever DISCEN = 0 or 1) and after each sequence of injected conversions (whatever JDISCEN = 0 or 1).
Note:	There is no delay inserted between each conversions of the injected sequence, except after the last one.
Note:	During a conversion, a hardware trigger event (for the same group of conversions) occurring during this delay is ignored.
Note:	This is not true for software triggers where it remains possible during this delay to set the bits ADSTART or JADSTART to restart a conversion: it is up to the software to read the data to the same constant. before launching a new conversion.
	No delay is inserted between conversions of different groups (a regular conversion followed by an injected conversion or conversely):
	’ If an injected trigger occurs during the automatic delay of a regular conversion, the injected conversion starts immediately (see Figure 121)
	Once the injected sequence is complete, the ADC waits for the delay (if not ended) of the previous regular conversion before launching a new regular conversion (see Figure 123).
	The behavior is slightly different in auto-injected mode (JAUTO = 1) where a new regular conversion can start only when the automatic delay of the previous injected sequence of conversion has ended (when JEOS has been cleared). This is to ensure that the software can read all the data of a given sequence before starting a new sequence (see Figure 124

To stop a conversion in continuous auto-injection mode combined with autodelay mode (JAUTO = 1, CONT = 1 and AUTDLY = 1), follow the following procedure:

Wait until JEOS $= 1$ (no more conversions are restarted)

Clear JEOS.

Set ADSTP.

Read the regular data.

If this procedure is not respected, a new regular sequence can restart if JEOS is cleared after ADSTP has been set.

In AUTDLY mode, a hardware regular trigger event is ignored if it occurs during an already ongoing regular sequence or during the delay that follows the last regular conversion of the sequence. It is however considered pending if it occurs after this delay, even if it occurs during an injected sequence of the delay that follows it. The conversion then starts at the end of the delay of the injected sequence.

In AUTDLY mode, a hardware injected trigger event is ignored if it occurs during an already ongoing injected sequence or during the delay that follows the last injected conversion of the sequence.

Figure 120. AUTODLY = 1, regular conversion in continuous mode, software trigger

AUTDLY $= 1$ .

Regular configuration: EXTEN $[1 : 0] = 00$ (SW trigger),CONT $= 1$ ,CHANNELS $= 1, 2, 3$ .

Injected configuration DISABLED.

21.4.28 Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)

The three AWD analog watchdogs monitor whether some channels remain within a configured voltage range (window). MS45396V1

Figure 125. Analog watchdog guarded area

AWDx flag and interrupt

An interrupt can be enabled for each of the 3 analog watchdogs by setting AWDxIE in the ADC_IER register

(x = 1, 2, 3)

AWDx

(x = 1, 2, 3)

flag is cleared by software by writing 1 to it.

The ADC conversion result is compared to the lower and higher thresholds before alignment.

Description of analog watchdog 1

The AWD analog watchdog 1 is enabled by setting the AWD1EN bit in the ADC_CFGR register. This watchdog monitors whether either one selected channel or all enabled channels

^{(1)}

remain within a configured voltage range (window).

Table 169 shows how the ADC_CFGR registers should be configured to enable the analog watchdog on one or more channels.

Table 169. Analog watchdog channel selection

Channels guarded by the analog watchdog	AWD1SGL bit	AWD1EN bit	JAWD1EN bit
None	X	0	0
All injected channels	0	0	1
All regular channels	0	1	0
All regular and injected channels	0	1	1
Single(1) injected channel	1	0	1
Single(1) regular channel	1	1	0
Single(1) regular or injected channel	1	1	1

Selected by the AWD1CH[4:0] bits. The channels must also be programmed to be converted in the

appropriate regular or injected sequence.

The AWD1 analog watchdog status bit is set if the analog voltage converted by the ADC is below a lower threshold or above a higher threshold.

These thresholds are programmed in bits HT1[11:0] and LT1[11:0] of the ADC_TR1 register for the analog watchdog 1 . When converting data with a resolution of less than 12 bits (according to bits RES[1:0]), the LSB of the programmed thresholds must be kept cleared because the internal comparison is always performed on the full 12-bit raw converted data (left aligned).

Table 170 describes how the comparison is performed for all the possible resolutions for analog watchdog 1.

Table 170. Analog watchdog 1 comparison

Resolution( bit RES[1:0])	Analog watchdog comparison between:		Comments
Resolution( bit RES[1:0])	Raw converted data, left aligned(1)	Thresholds	Comments
00: 12-bit	DATA[11:0]	LT1[11:0] and HT1[11:0]	-
01: 10-bit	DATA[11:2],00	LT1[11:0] and HT1[11:0]	User must configure LT1[1:0] and HT1[1:0] to 00
10: 8-bit	DATA[11:4],0000	LT1[11:0] and HT1[11:0]	User must configure LT1[3:0] and HT1[3:0] to 0000
11: 6-bit	DATA[11:6],000000	LT1[11:0] and HT1[11:0]	User must configure LT1[5:0] and HT1[5:0] to 000000

Refer to Section : Gain compensation for additional details on analog watchdog comparison.

Analog watchdog filter for watchdog 1

When an ADC is configured with only one input channel (selecting several channels in Scan mode not allowed), a valid ADC conversion data interval can be configured through the ADC_TR1 register:

When converted data belong to the interval defined in ADC_TR1, a DMA request is generated.

Otherwise, no DMA request is issued. RDATA register is updated at each conversion. If data are out-of-range a number of times higher than the value specified in AWDFILT bit of ADC_TR1, the AWDx flag is set an the corresponding interrupt is issued.

Description of analog watchdog 2 and 3

The second and third analog watchdogs are more flexible and can guard several selected channels by programming the corresponding bits in AWDxCH[18:0]

(x = 2, 3)

The corresponding watchdog is enabled when any bit of AWDxCH[18:0] (x=2,3) is set.

They are limited to a resolution of 8 bits and only the 8 MSBs of the thresholds can be programmed into

HTx [7 : 0]

and

LTx [7 : 0]

. Table 171 describes how the comparison is performed for all the possible resolutions.

Table 171. Analog watchdog 2 and 3 comparison

Resolution (bits RES[1:0])	Analog watchdog comparison between:		Comments
Resolution (bits RES[1:0])	Raw converted data, left aligned(1)	Thresholds	Comments
00: 12-bit	DATA[11:4]	LTx[7:0] and HTx[7:0]	DATA[3:0] are not relevant for the comparison
01: 10-bit	DATA[11:4]	LTx[7:0] and HTx[7:0]	DATA[3:2] are not relevant for the comparison
10: 8-bit	DATA[11:4]	LTx[7:0] and HTx[7:0]	-
11: 6-bit	DATA[11:6],00	LTx[7:0] and HTx[7:0]	User must configure LTx[1:0] and HTx[1:0] to 00

Refer to Section : Gain compensation for additional details on analog watchdog comparison.

ADCy_AWDx_OUT signal output generation

Each analog watchdog is associated to an internal hardware signal ADCy_AWDx_OUT (y=ADC number, x=watchdog number) which is directly connected to the ETR input (external trigger) of some on-chip timers. Refer to the on-chip timers section to understand how to select the ADCy_AWDx_OUT signal as ETR.

ADCy_AWDx_OUT is activated when the associated analog watchdog is enabled:

ADCy_AWDx_OUT is set when a guarded conversion is outside the programmed thresholds.

ADCy_AWDx_OUT is reset after the end of the next guarded conversion which is inside the programmed thresholds (It remains at 1 if the next guarded conversions are still outside the programmed thresholds).

ADCy_AWDx_OUT is also reset when disabling the ADC (when setting ADDIS = 1). Note that stopping regular or injected conversions (setting ADSTP $= 1$ or JADSTP $= 1$ ) has no influence on the generation of ADCy_AWDx_OUT.

Note: AWDx flag is set by hardware and reset by software: AWDx flag has no influence on the generation of ADCy_AWDx_OUT (ex: ADCy_AWDx_OUT can toggle while AWDx flag remains at 1 if the software did not clear the flag).

Figure 126. ADCy_AWDx_OUT signal generation (on all regular channels)

Analog watchdog with gain and offset compensation

When gain and offset compensation are enabled, the analog watchdog compares the threshold after the compensated data.

Note:

When the offset compensation is enabled (OFFSETy_EN set in ADC_OFRy register), data overflow or underflow can result in a wrong watchdog result. When the saturation is enabled (SATEN set in ADC_OFRy), the watchdog provides a correct result. However this prevents from using the signed data format.

21.4.29 Oversampler

The oversampling unit performs data pre-processing to offload the CPU. It is able to handle multiple conversions and average them into a single data with increased data width, up to 16-bit.

It provides a result with the following form,where

N

and

M

can be adjusted:

Result = \frac{1}{M} \times \sum_{n = 0}^{n = N - 1} Conversion (t_{n})

It allows to perform by hardware the following functions: averaging, data rate reduction, SNR improvement, basic filtering.

The oversampling ratio

N

is defined using the OVFS[2:0] bits in the ADC_CFGR2 register, and can range from

2 x

256 x

. The division coefficient

M

consists of a right bit shift up to 8 bits, and is defined using the OVSS[3:0] bits in the ADC_CFGR2 register.

The summation unit can yield a result up to 20 bits (256x 12-bit results), which is first shifted right. It is then truncated to the 16 least significant bits, rounded to the nearest value using the least significant bits left apart by the shifting, before being finally transferred into the ADC_DR data register.

Note: If the intermediary result after the shifting exceeds 16-bit, the result is truncated as is, without saturation. maintained equal during the whole oversampling sequence. A new data is provided every

N

Figure 130. 20-bit to 16-bit result truncation

Figure 131 gives a numerical example of the processing, from a raw 20-bit accumulated data to the final 16-bit result.

Figure 131. Numerical example with 5-bit shift and rounding

Table 172 gives the data format for the various

N

and

M

combinations,for a raw conversion data equal to

0 xFFF

Table 172. Maximum output results versus

N

and

M

(gray cells indicate truncation)

Over sampling ratio	Max Raw data	No-shift OVSS = 0000	1-bit shift OVSS = 0001	2-bit shift OVSS = 0010	3-bit shift OVSS = 0011	4-bit shift OVSS = 0100	5-bit shift OVSS = 0101	6-bit shift OVSS = 0110	7-bit shift OVSS = 0111	8-bit shift OVSS = 1000
2x	0x1FFE	0x1FFE	0x0FFF	0x0800	0x0400	0x0200	0x0100	0x0080	0x0040	0x020
4x	0x3FFC	0x3FFC	0x1FFE	0x0FFF	0x0800	0x0400	0x0200	0x0100	0x0080	0x0040
8x	0x7FF8	0x7FF8	0x3FFC	0x1FFE	0x0FFF	0x0800	0x0400	0x0200	0x0100	0x0080
16x	0xFFF0	0xFFF0	0x7FF8	0x3FFC	0x1FFE	0x0FFF	0x0800	0x0400	0x0200	0x0100
32x	0x1FFE0	0xFFE0	0xFFF0	0x7FF8	0x3FFC	0x1FFE	0x0FFF	0x0800	0x0400	0x0200
64x	0x3FFC0	0xFFC0	0xFFE0	0xFFF0	0x7FF8	0x3FFC	0x1FFE	0x0FFF	0x0800	0x0400
128x	0x7FF80	0xFF80	0xFFC0	0xFFE0	0xFFF0	0x7FF8	0x3FFC	0x1FFE	0x0FFF	0x0800
256x	0xFFF00	0xFF00	0xFF80	0xFFC0	0xFFE0	0xFFF0	0x7FF8	0x3FFC	0x1FFE	0x0FFF

There are no changes for conversion timings in oversampled mode: the sample time is

RM0440	Analog-to-digital converters (ADC
	conversions,with an equivalent delay equal to $N \times T_{CONV} = N \times (t_{SMPL} + t_{SAR})$ . The flags are set as follows:
	- The end of the sampling phase (EOSMP) is set after each sampling phase
	The end of conversion (EOC) occurs once every N conversions, when the oversampled result is available
	The end of sequence (EOS) occurs once the sequence of oversampled data i completed (i.e. after $N \times$ sequence length conversions total)
	ADC operating modes supported when oversampling (single ADC mode
	In oversampling mode, most of the ADC operating modes are maintained
	- Single or continuous mode conversions
	- ADC conversions start either by software or with triggers
	- ADC stop during a conversion (abort
	- Data read via CPU or DMA with overrun detection
	- Low-power modes (AUTDLY
	- Programmable resolution: in this case, the reduced conversion values (as per RES[1:0 bits in ADC_CFGR1 register) are accumulated, truncated, rounded and shifted in the same way as 12-bit conversions are
Note:	The alignment mode is not available when working with oversampled data. The ALIGN bit in ADC_CFGR1 is ignored and the data are always provided right-aligned
	Offset correction is not supported in oversampling mode. When ROVSE and/or JOVSE bit is set, the value of the OFFSETy_EN bit in ADC_OFRy register is ignored (considered a. reset).
	Analog watchdog
	The analog watchdog functionality is maintained, with the following difference - The RES[1:0] bits are ignored, comparison is always done using the full 12-bit values HT[11:0] and LT[11:0]
	’ the comparison is performed on the most significant 12-bit of the 16-bit oversampled results ADC_DR[15:4]
Note:	Care must be taken when using high shifting values, since this reduces the comparison range. For instance, if the oversampled result is shifted by 4 bits, thus yielding a 12-bit data right-aligned, the effective analog watchdog comparison can only be performed on 8 bits. The comparison is done between ADC_DR[11:4] and HT[0:7] / LT[[0:7], and HT[11:8] / LT[11:8] must be kept reset.
	Triggered mode
	The averager can also be used for basic filtering purpose. Although not a very powerful filt (slow roll-off and limited stop band attenuation), it can be used as a notch filter to reject constant parasitic frequencies (typically coming from the mains or from a switched mode power supply). For this purpose, a specific discontinuous mode can be enabled with TROVS bit in ADC_CFGR2, to be able to have an oversampling frequency defined by a user and independent from the conversion time itself.
	Figure 132 below shows how conversions are started in response to triggers during discontinuous mode.
	If the TROVS bit is set, the content of the DISCEN bit is ignored and considered as 1

Figure 132. Triggered regular oversampling mode (TROVS bit

= 1

)

Injected and regular sequencer management when oversampling

In oversampling mode, it is possible to have differentiated behavior for injected and regular sequencers. The oversampling can be enabled for both sequencers with some limitations if they have to be used simultaneously (this is related to a unique accumulation unit).

Oversampling regular channels only

The regular oversampling mode bit ROVSM defines how the regular oversampling sequence is resumed if it is interrupted by injected conversion:

In continued mode, the accumulation restarts from the last valid data (prior to the conversion abort request due to the injected trigger). This ensures that oversampling is complete whatever the injection frequency (providing at least one regular conversion can be complete between triggers);

In resumed mode, the accumulation restarts from 0 (previous conversion results are ignored). This mode allows to guarantee that all data used for oversampling were converted back-to-back within a single timeslot. Care must be taken to have a injection trigger period above the oversampling period length. If this condition is not respected, the oversampling cannot be complete and the regular sequencer is blocked.

Figure 133 gives examples for a

4 x

oversampling ratio.

Triggered regular oversampling with injected conversions

It is possible to have triggered regular mode with injected conversions. In this case, the injected mode oversampling mode must be disabled, and the ROVSM bit is ignored (resumed mode is forced). The JOVSE bit must be reset. The behavior is represented on Figure 135 below.

Figure 135. Triggered regular oversampling with injection

MS34458V4

Auto-injected mode

It is possible to oversample auto-injected sequences and have all conversions results stored in registers to save a DMA resource. This mode is available only with both regular and injected oversampling active: JAUTO = 1, ROVSE = 1 and JOVSE = 1, other combinations are not supported. The ROVSM bit is ignored in auto-injected mode. The Figure 136 below shows how the conversions are sequenced. It is possible to have also the triggered mode enabled, using the TROVS bit. In this case, the ADC must be configured as following: JAUTO = 1, DISCEN = 0, JDISCEN = 0, ROVSE

= 1

,JOVSE

= 1

and TROVSE

= 1

Figure 136. Oversampling in auto-injected mode

Dual ADC modes supported when oversampling

It is possible to have oversampling enabled when working in dual ADC configuration, for the injected simultaneous mode and regular simultaneous mode. In this case, the two ADCs must be programmed with the very same settings (including oversampling).

All other dual ADC modes are not supported when either regular or injected oversampling is enabled (ROVSE

= 1

or JOVSE

= 1

Combined modes summary

The Table 173 below summarizes all combinations, including modes not supported.

Table 173. Oversampler operating modes summary

Regular Oversampling ROVSE	Injected Oversampling JOVSE	Oversampler mode ROVSM 0 = continued 1 = resumed	Triggered Regular mode TROVS	Comment
1	0	0	0	Regular continued mode
1	0	0	1	Not supported
1	0	1	0	Regular resumed mode
1	0	1	1	Triggered regular resumed mode
1	1	0	X	Not supported
1	1	1	0	Injected and regular resumed mode
1	1	1	1	Not supported
0	1	X	X	Injected oversampling

21.4.30 Dual ADC modes

Dual ADC modes can be used in devices with two ADCs or more (see Figure 137).

In dual ADC mode the start of conversion is triggered alternately or simultaneously by the ADCx master to the ADC slave, depending on the mode selected by the bits DUAL[4:0] in the ADCx_CCR register.

Four possible modes are implemented:

Injected simultaneous mode

Regular simultaneous mode

Interleaved mode

Alternate trigger mode

It is also possible to use these modes combined in the following ways:

Injected simultaneous mode + Regular simultaneous mode

Regular simultaneous mode + Alternate trigger mode

Injected simultaneous mode + Interleaved mode

In dual ADC mode (when bits DUAL[4:0] in ADCx_CCR register are not equal to zero), the bits CONT, AUTDLY, DISCEN, DISCNUM[2:0], JDISCEN, JQM, JAUTO of the ADC_CFGR register are shared between the master and slave ADC: the bits in the slave ADC are always equal to the corresponding bits of the master ADC.

To start a conversion in dual mode, the user must program the bits EXTEN[1:0], EXTSEL, JEXTEN[1:0], JEXTSEL of the master ADC only, to configure a software or hardware trigger, and a regular or injected trigger. (the bits EXTEN[1:0] and JEXTEN[1:0] of the slave ADC are don't care).

In regular simultaneous or interleaved modes: once the user sets bit ADSTART or bit ADSTP of the master ADC, the corresponding bit of the slave ADC is also automatically set. However, bit ADSTART or bit ADSTP of the slave ADC is not necessary cleared at the same time as the master ADC bit.

In injected simultaneous or alternate trigger modes: once the user sets bit JADSTART or bit JADSTP of the master ADC, the corresponding bit of the slave ADC is also automatically set. However, bit JADSTART or bit JADSTP of the slave ADC is not necessary cleared at the same time as the master ADC bit.

In dual ADC mode, the converted data of the master and slave ADC can be read in parallel, by reading the ADC common data register (ADCx_CDR). The status bits can be also read in parallel by reading the dual-mode status register (ADCx_CSR).

Injected simultaneous mode

This mode is selected by programming bits DUAL[4:0]

= 00101

This mode converts an injected group of channels. The external trigger source comes from the injected group multiplexer of the master ADC (selected by the JEXTSEL bits in the ADC_JSQR register).

Note: : Do not convert the same channel on the two ADCs (no overlapping sampling times for the two ADCs when converting the same channel).

In simultaneous mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the longer of the 2 sequences. Otherwise, the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions.

Regular conversions can be performed on one or all ADCs. In that case, they are independent of each other and are interrupted when an injected event occurs. They are resumed at the end of the injected conversion group.

At the end of injected sequence of conversion event (JEOS) on the master ADC, the converted data is stored into the master ADC_JDRy registers and a JEOS interrupt is generated (if enabled)

At the end of injected sequence of conversion event (JEOS) on the slave ADC, the converted data is stored into the slave ADC_JDRy registers and a JEOS interrupt is generated (if enabled)

If the duration of the master injected sequence is equal to the duration of the slave injected one (like in Figure 138), it is possible for the software to enable only one of the two JEOS interrupt (ex: master JEOS) and read both converted data (from master ADC_JDRy and slave ADC_JDRy registers). injected trigger event to occur.

Figure 138. Injected simultaneous mode on 4 channels: dual ADC mode

MS31900V1

If JDISCEN = 1, each simultaneous conversion of the injected sequence requires an

This mode can be combined with AUTDLY mode:

Once a simultaneous injected sequence of conversions has ended, a new injected trigger event is accepted only if both JEOS bits of the master and the slave ADC have been cleared (delay phase). Any new injected trigger events occurring during the ongoing injected sequence and the associated delay phase are ignored.

Once a regular sequence of conversions of the master ADC has ended, a new regular trigger event of the master ADC is accepted only if the master data register (ADC_DR) has been read. Any new regular trigger events occurring for the master ADC during the

ongoing regular sequence and the associated delay phases are ignored.

There is the same behavior for regular sequences occurring on the slave ADC.

Regular simultaneous mode with independent injected

This mode is selected by programming bits DUAL[4:0] = 00110.

This mode is performed on a regular group of channels. The external trigger source comes from the regular group multiplexer of the master ADC (selected by the EXTSEL bits in the ADC_CFGR register). A simultaneous trigger is provided to the slave ADC.

In this mode, independent injected conversions are supported. An injection request (either on master or on the slave) aborts the current simultaneous conversions, which are restarted once the injected conversion is completed.

Note:

Do not convert the same channel on the two ADCs (no overlapping sampling times for the two ADCs when converting the same channel).

In regular simultaneous mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the longer conversion time of the 2

sequences. Otherwise, the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions.

Software is notified by interrupts when it can read the data:

At the end of each conversion event (EOC) on the master ADC, a master EOC interrupt is generated (if EOCIE is enabled) and software can read the ADC_DR of the master ADC.

At the end of each conversion event (EOC) on the slave ADC, a slave EOC interrupt is generated (if EOCIE is enabled) and software can read the ADC_DR of the slave ADC.

If the duration of the master regular sequence is equal to the duration of the slave one (like in Figure 139), it is possible for the software to enable only one of the two EOC interrupt (ex: master EOC) and read both converted data from the Common Data register (ADCx_CDR).

It is also possible to read the regular data using the DMA. Two methods are possible:

Using two DMA channels (one for the master and one for the slave). In this case bits MDMA[1:0] must be kept cleared.

Configure the DMA master ADC channel to read ADC_DR from the master. DMA requests are generated at each EOC event of the master ADC.

Configure the DMA slave ADC channel to read ADC_DR from the slave. DMA requests are generated at each EOC event of the slave ADC.

Using MDMA mode, which leaves one DMA channel free for other uses:

Configure MDMA[1:0] = 10 or 11 (depending on resolution).

A single DMA channel is used (the one of the master). Configure the DMA master ADC channel to read the common ADC register (ADCx_CDR)

A single DMA request is generated each time both master and slave EOC events have occurred. At that time, the slave ADC converted data is available in the upper half-word of the ADCx_CDR 32-bit register and the master ADC converted data is available in the lower half-word of ADCx_CDR register.

Both EOC flags are cleared when the DMA reads the ADCx_CDR register.

Note: In MDMA mode (MDMA[1:0] = 10 or 11), the user must program the same number of conversions in the master's sequence as in the slave's sequence. Otherwise, the remaining conversions does not generate a DMA request.

Figure 139. Regular simultaneous mode on 16 channels: dual ADC mode

If DISCEN

= 1

then each "

n

" simultaneous conversions of the regular sequence require a regular trigger event to occur ("n" is defined by DISCNUM).

This mode can be combined with AUTDLY mode:

Once a simultaneous conversion of the sequence has ended, the next conversion in the sequence is started only if the common data register, ADCx_CDR (or the regular data register of the master ADC) has been read (delay phase).

Once a simultaneous regular sequence of conversions has ended, a new regular trigger event is accepted only if the common data register (ADCx_CDR) has been read (delay phase). Any new regular trigger events occurring during the ongoing regular sequence and the associated delay phases are ignored.

It is possible to use the DMA to handle data in regular simultaneous mode combined with AUTDLY mode, assuming that multiple-DMA mode is used: bits MDMA must be set to 10 or 11.

When regular simultaneous mode is combined with AUTDLY mode, it is mandatory for the user to ensure that:

The number of conversions in the master's sequence is equal to the number of conversions in the slave's.

For each simultaneous conversions of the sequence, the length of the conversion of the slave ADC is inferior to the length of the conversion of the master ADC. Note that the length of the sequence depends on the number of channels to convert and the sampling time and the resolution of each channels.

Note: This combination of regular simultaneous mode and AUTDLY mode is restricted to the use case when only regular channels are programmed: it is forbidden to program injected channels in this combined mode.

Interleaved mode with independent injected

This mode is selected by programming bits DUAL[4:0]

= 00111

This mode can be started only on a regular group (usually one channel). The external trigger source comes from the regular channel multiplexer of the master ADC.

After an external trigger occurs:

The master ADC starts immediately.

The slave ADC starts after a delay of several-ADC clock cycles after the sampling phase of the master ADC has complete.

The minimum delay which separates two conversions in interleaved mode is configured in the DELAY bits in the ADCx_CCR register. This delay starts counting one half cycle after the end of the sampling phase of the master conversion. This way, an ADC cannot start a conversion if the complementary ADC is still sampling its input (only one ADC can sample the input signal at a given time).

The minimum possible DELAY is 1 to ensure that there is at least one cycle time between the opening of the analog switch of the master ADC sampling phase and the closing of the analog switch of the slave ADC sampling phase.

The maximum DELAY is equal to the number of cycles corresponding to the selected resolution. However the user must properly calculate this delay to ensure that an ADC does not start a conversion while the other ADC is still sampling its input.

If the CONT bit is set on both master and slave ADCs, the selected regular channels of both ADCs are continuously converted.

The software is notified by interrupts when it can read the data at the end of each conversion event (EOC) on the slave ADC. A slave and master EOC interrupts are generated (if EOCIE is enabled) and the software can read the ADC_DR of the slave/master ADC.

Iote: It is possible to enable only the EOC interrupt of the slave and read the common data register (ADCx_CDR). But in this case, the user must ensure that the duration of the conversions are compatible to ensure that inside the sequence, a master conversion is always followed by a slave conversion before a new master conversion restarts. It is recommended to use the MDMA mode.

It is also possible to have the regular data transferred by DMA. In this case, individual DMA requests on each ADC cannot be used and it is mandatory to use the MDMA mode, as following:

Configure MDMA[1:0] = 10 or 11 (depending on resolution).

A single DMA channel is used (the one of the master). Configure the DMA master ADC channel to read the common ADC register (ADCx_CDR).

A single DMA request is generated each time both master and slave EOC events have occurred. At that time, the slave ADC converted data is available in the upper half-word of the ADCx_CDR 32-bit register and the master ADC converted data is available in the lower half-word of ADCx_CCR register.

Both EOC flags are cleared when the DMA reads the ADCx_CCR register.

Figure 140. Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode

Figure 141. Interleaved mode on 1 channel in single conversion mode: dual ADC mode

If DISCEN

= 1

,each "

n

" simultaneous conversions ("

n

" is defined by DISCNUM) of the regular sequence require a regular trigger event to occur.

In this mode, injected conversions are supported. When injection is done (either on master or on slave), both the master and the slave regular conversions are aborted and the sequence is restarted from the master (see Figure 142 below).

Figure 142. Interleaved conversion with injection

Alternate trigger mode

This mode is selected by programming bits DUAL[4:0] = 01001.

This mode can be started only on an injected group. The source of external trigger comes from the injected group multiplexer of the master ADC.

This mode is only possible when selecting hardware triggers: JEXTEN[1:0] must not be 00.

Injected discontinuous mode disabled (JDISCEN = 0 for both ADC)

When the first trigger occurs, all injected master ADC channels in the group are converted.

When the second trigger occurs, all injected slave ADC channels in the group are converted.

And so on.

A JEOS interrupt, if enabled, is generated after all injected channels of the master ADC in the group have been converted.

A JEOS interrupt, if enabled, is generated after all injected channels of the slave ADC in the group have been converted.

JEOC interrupts, if enabled, can also be generated after each injected conversion.

If another external trigger occurs after all injected channels in the group have been converted then the alternate trigger process restarts by converting the injected channels of the master ADC in the group.

Figure 143. Alternate trigger: injected group of each ADC

Note: Regular conversions can be enabled on one or all ADCs. In this case the regular conversions are independent of each other. A regular conversion is interrupted when the ADC has to perform an injected conversion. It is resumed when the injected conversion is finished.

The time interval between 2 trigger events must be greater than or equal to 1 ADC clock period. The minimum time interval between 2 trigger events that start conversions on the same ADC is the same as in the single ADC mode.

Injected discontinuous mode enabled (JDISCEN = 1 for both ADC)

If the injected discontinuous mode is enabled for both master and slave ADCs:

When the first trigger occurs, the first injected channel of the master ADC is converted.

When the second trigger occurs, the first injected channel of the slave ADC is converted.

And so on.

A JEOS interrupt, if enabled, is generated after all injected channels of the master ADC in the group have been converted.

A JEOS interrupt, if enabled, is generated after all injected channels of the slave ADC in the group have been converted.

JEOC interrupts, if enabled, can also be generated after each injected conversions.

If another external trigger occurs after all injected channels in the group have been converted then the alternate trigger process restarts.

Figure 144. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode

Combined regular/injected simultaneous mode

This mode is selected by programming bits DUAL[4:0] = 00001.

It is possible to interrupt the simultaneous conversion of a regular group to start the simultaneous conversion of an injected group.

Note: In combined regular/injected simultaneous mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the long conversion time of the 2 sequences. Otherwise, the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions.

Combined regular simultaneous + alternate trigger mode

This mode is selected by programming bits DUAL[4:0]

= 00010

It is possible to interrupt the simultaneous conversion of a regular group to start the alternate trigger conversion of an injected group. Figure 145 shows the behavior of an alternate trigger interrupting a simultaneous regular conversion.

The injected alternate conversion is immediately started after the injected event. If a regular conversion is already running, in order to ensure synchronization after the injected conversion, the regular conversion of all (master/slave) ADCs is stopped and resumed synchronously at the end of the injected conversion.

Note: In combined regular simultaneous + alternate trigger mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the long conversion time of the 2 sequences. Otherwise, the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions. trigger is ignored because the associated alternate conversion is not complete).

Figure 145. Alternate + regular simultaneous

ai16062V2-m

If a trigger occurs during an injected conversion that has interrupted a regular conversion, the alternate trigger is served. Figure 146 shows the behavior in this case (note that the 6th

Figure 146. Case of trigger occurring during injected conversion

Combined injected simultaneous plus interleaved

This mode is selected by programming bits DUAL[4:0] = 00011

It is possible to interrupt an interleaved conversion with a simultaneous injected event.

In this case the interleaved conversion is interrupted immediately and the simultaneous injected conversion starts. At the end of the injected sequence the interleaved conversion is resumed. When the interleaved regular conversion resumes, the first regular conversion which is performed is alway the master's one. Figure 147, Figure 148 and Figure 149 show the behavior using an example.

Caution: In this mode, it is mandatory to use the Common Data Register to read the regular data with a single read access. On the contrary, master-slave data coherency is not guaranteed.

DMA requests in dual ADC mode

In all dual ADC modes, it is possible to use two DMA channels (one for the master, one for the slave) to transfer the data, like in single mode (refer to Figure 150: DMA Requests in regular simultaneous mode when MDMA = 00).

Figure 150. DMA Requests in regular simultaneous mode when MDMA = 00

Configuration where each sequence contains only one conversion MSv31032V2

In simultaneous regular and interleaved modes, it is also possible to save one DMA channel and transfer both data using a single DMA channel. For this MDMA bits must be configured in the ADCx_CCR register:

MDMA = 10: A single DMA request is generated each time both master and slave EOC events have occurred. At that time, two data items are available and the 32-bit register ADCx_CDR contains the two half-words representing two ADC-converted data items. The slave ADC data take the upper half-word and the master ADC data take the lower half-word.

This mode is used in interleaved mode and in regular simultaneous mode when resolution is 10-bit or 12-bit.

Example:

Interleaved dual mode: a DMA request is generated each time 2 data items are available:

first DMA request: ADCx_CDR[31:0] = SLV_ADC_DR[15:0] | MST_ADC_DR[15:0] second DMA request: ADCx_CDR[31:0] = SLV_ADC_DR[15:0] | MST_ADC_DR[15:0]

Note: When using MDMA mode, the user must take care to configure properly the duration of the master and slave conversions so that a DMA request is generated and served for reading both data (master + slave) before a new conversion is available.

MDMA = 11: This mode is similar to the MDMA = 10. The only differences are that on each DMA request (two data items are available), two bytes representing two ADC converted data items are transferred as a half-word.

This mode is used in interleaved and regular simultaneous mode when resolution is 6- bit or when resolution is 8-bit and data is not signed (offsets must be disabled for all the involved channels).

Example:

Interleaved dual mode: a DMA request is generated each time 2 data items are available:

first DMA request: ADCx_CDR[15:0] = SLV_ADC_DR[7:0] | MST_ADC_DR[7:0] second DMA request: ADCx_CDR[15:0] = SLV_ADC_DR[7:0] | MST_ADC_DR[7:0]

Overrun detection

In dual ADC mode (when DUAL[4:0] is not equal to 00000), if an overrun is detected on one of the ADCs, the DMA requests are no longer issued to ensure that all the data transferred to the RAM are valid (this behavior occurs whatever the MDMA configuration). It may happen that the EOC bit corresponding to one ADC remains set because the data register of this ADC contains valid data.

DMA one shot mode/ DMA circular mode when MDMA mode is selected

When MDMA mode is selected (10 or 11), bit DMACFG of the ADCx_CCR register must also be configured to select between DMA one shot mode and circular mode, as explained in section Section : Managing conversions using the DMA (bits DMACFG of master and slave ADC_CFGR are not relevant).

Stopping the conversions in dual ADC modes

The user must set the control bits ADSTP/JADSTP of the master ADC to stop the conversions of both ADC in dual ADC mode. The other ADSTP control bit of the slave ADC has no effect in dual ADC mode.

Once both ADC are effectively stopped, the bits ADSTART/JADSTART of the master and slave ADCs are both cleared by hardware.

21.4.31 Temperature sensor

The temperature sensor can be used to measure the junction temperature (Tj) of the device. The temperature sensor is internally connected to the ADC input channels which are used to convert the sensor output voltage to a digital value. When not in use, the sensor can be put in power down mode. It support the temperature range -40 to

125^{\circ} C

Figure 153 shows the block diagram of connections between the temperature sensor and the ADC.

The temperature sensor output voltage changes linearly with temperature. The offset of this line varies from chip to chip due to process variation (up to

45^{\circ} C

from one chip to another).

The uncalibrated internal temperature sensor is more suited for applications that detect temperature variations instead of absolute temperatures. To improve the accuracy of the temperature sensor measurement, calibration values are stored in system memory for each device by ST during production.

During the manufacturing process, the calibration data of the temperature sensor and the internal voltage reference are stored in the system memory area. The user application can then read them and use them to improve the accuracy of the temperature sensor or the internal reference (refer to the datasheet for additional information).

The temperature sensor is internally connected to the ADC input channel which is used to convert the sensor's output voltage to a digital value. Refer to the electrical characteristics section of the device datasheet for the sampling time value to be applied when converting the internal temperature sensor.

When not in use, the sensor can be put in power-down mode.

Figure 153 shows the block diagram of the temperature sensor.

Figure 153. Temperature sensor channel block diagram

Reading the temperature

To use the sensor:

Select the ADC input channels that is connected to $V_{TS}$ .

Program with the appropriate sampling time (refer to electrical characteristics section of the device datasheet).

Set the VSENSESEL bit in the ADCx_CCR register to wake up the temperature sensor from power-down mode.

Start the ADC conversion.

Read the resulting $V_{TS}$ data in the ADC data register.

Calculate the actual temperature using the following formula: Where:

emperature (in^{\circ} C) = \frac{TS_CAL2_TEMP - TS_CAL1_TEMP}{TS_CAL2-TS_CAL1} \times (TS_DATA-TS_CAL1) + TS_CAL1_TEMP

TS_CAL2 is the temperature sensor calibration value acquired at TS_CAL2_TEMP.

TS_CAL1 is the temperature sensor calibration value acquired at TS_CAL1_TEMP.

TS_DATA is the actual temperature sensor output value converted by ADC. Refer to the device datasheet for more information about TS_CAL1 and TS_CAL2 calibration points.

Note: The sensor has a startup time after waking from power-down mode before it can output

V_{T S}

at the correct level. The ADC also has a startup time after power-on, so to minimize the delay, the ADEN and VSENSESEL bits should be set at the same time.

The above formula is given for TS_DATA measurement done with the same

V_{REF +}

voltage as TS_CAL1/TS_CAL2 values. If

V_{REF +}

is different,the formula must be adapted. For example if

V_{REF +} = 3.3 V

and TS_CAL data are acquired at

V_{REF +} = 3.0 V

,TS_DATA must be replaced by TS_DATA x (3.3/3.0).

21.4.32 $V_{BAT}$ supply monitoring

The VBATSEL bit in the ADCx_CCR register is used to switch to the battery voltage. As the

V_{BAT}

voltage could be higher than

V_{DDA}

,to ensure the correct operation of the

ADC

,the

V_{BAT}

pin is internally connected to a bridge divider by 3 . This bridge is automatically enabled when VBATSEL is set,to connect

V_{BAT} / 3

to the ADC input channels. As a consequence,the converted digital value is one third of the

V_{BAT}

voltage. To prevent any unwanted consumption on the battery, it is recommended to enable the bridge divider only when needed, for ADC conversion.

Refer to the electrical characteristics of the device datasheet for the sampling time value to be applied when converting the

V_{BAT} / 3

voltage.

The figure below shows the block diagram of the

V_{BAT}

sensing feature.

Figure 154.

V_{B A T}

channel block diagram

The VBATSEL bit must be set to enable the conversion of internal channel for $V_{BAT} / 3$ .

21.4.33 Monitoring the internal voltage reference

It is possible to monitor the internal voltage reference

(V_{REFINT})

to have a reference point for evaluating the ADC

V_{REF +}

voltage level.

The internal reference voltage

(V_{REFINT})

is internally connected to ADC1_INP18,

ADC3_INP18, ADC4_INP18 and ADC5_INP18.

Refer to the electrical characteristics section of the product datasheet for the sampling time value to be applied when converting the internal voltage reference voltage.

Figure 155 shows the block diagram of the

V_{REFINT}

sensing feature.

Figure 155.

V_{REFINT}

channel block diagram

The VREFEN bit into ADCx_CCR register must be set to enable the conversion of internal channels (Vrefint).

Calculating the actual $v_{R E F +}$ voltage using the internal reference voltage

The power supply voltage applied to the device may be subject to variations or not precisely known. When

V_{D D A}

is connected to

V_{R E F +}

,it is possible to compute the actual

V_{D D A}

voltage using the embedded internal reference voltage

(V_{REFINT}) . V_{REFINT}

and its calibration data, acquired by the ADC during the manufacturing process at

V_{DDA}

Charac,can be used to evaluate the actual

V_{DDA}

voltage level.

The following formula gives the actual

V_{REF +}

voltage supplying the device:

V_{REF +} = V_{REF +_Charac} \times VREFINT_CAL / VREFINT_DATA

Where:

$V_{REF + Charac}$ is the value of $V_{REF +}$ voltage characterized at $V_{REFINT}$ during the manufacturing process. It is specified in the device datasheet.

VREFINT_CAL is the $V_{REFINT}$ calibration value

VREFINT_DATA is the actual $V_{REFINT}$ output value converted by ADC

Converting a supply-relative ADC measurement to an absolute voltage value

The ADC is designed to deliver a digital value corresponding to the ratio between

V_{R E F +}

and the voltage applied on the converted channel.

For most applications

V_{D D A}

value is unknown and ADC converted values are right-aligned. In this case,it is necessary to convert this ratio into a voltage independent from

V_{D D A}

V_{CHANNELx} = \frac{V_{REF +}}{FULL_SCALE} \times ADC_DATA

By replacing

V_{REF +}

by the formula provided above,the absolute voltage value is given by the following formula

V_{CHANNEL x} = \frac{V_{REF +_Charac} \times VREFINT_CAL \times ADC_DATA}{VREFINT_DATA \times FULL_SCALE}

For applications where

V_{{REF}^{+}}

is known and ADC converted values are right-aligned,the absolute voltage value can be obtained by using the following formula:

V_{CHANNELx} = \frac{V_{REF +}}{FULL_SCALE} \times ADC_DATA

Where:

$V_{REF + Charac}$ is the value of $V_{REF +}$ voltage characterized at $V_{REFINT}$ during the manufacturing process.

VREFINT_CAL is the $V_{REFINT}$ calibration value

ADC_DATA is the value measured by the ADC on channel $x$ (right-aligned)

VREFINT_DATA is the actual $V_{REFINT}$ output value converted by the ADC

FULL_SCALE is the maximum digital value of the ADC output. For example with 12-bit resolution,it is $2^{12} - 1 = 4095$ or with 8-bit resolution, $2^{8} - 1 = 255$ .

Note: If ADC measurements are done using an output format other than 16-bit right-aligned, all the parameters must first be converted to a compatible format before the calculation is done.

21.5 ADC in low-power mode

Table 174. Effect of low-power modes on the ADC

Mode	Description
Sleep	No effect. DMA requests are functional.
Low-power run	No effect.
Low-power sleep	No effect. DMA requests are functional.
Stop 0/Stop 1	The ADC is not operational. Its state is kept The ADC consumes the static current recommended to disable the peripheral in advance in order to reduce power consumption
Standby	The ADC is powered down and must be reinitialized after exiting Standby or Shutdown mode.
Shutdown

21.6 ADC interrupts

For each ADC, an interrupt can be generated:

After ADC power-up, when the ADC is ready (flag ADRDY)

On the end of any conversion for regular groups (flag EOC)

On the end of a sequence of conversion for regular groups (flag EOS)

On the end of any conversion for injected groups (flag JEOC)

On the end of a sequence of conversion for injected groups (flag JEOS)

When an analog watchdog detection occurs (flag AWD1, AWD2 and AWD3)

When the end of sampling phase occurs (flag EOSMP)

When the data overrun occurs (flag OVR)

When the injected sequence context queue overflows (flag JQOVF)

Separate interrupt enable bits are available for flexibility.

Table 175. ADC interrupts per each ADC

Interrupt event	Event flag	Enable control bit
ADC ready	ADRDY	ADRDYIE
End of conversion of a regular group	EOC	EOCIE
End of sequence of conversions of a regular group	EOS	EOSIE
End of conversion of a injected group	JEOC	JEOCIE
End of sequence of conversions of an injected group	JEOS	JEOSIE
Analog watchdog 1 status bit is set	AWD1	AWD1IE
Analog watchdog 2 status bit is set	AWD2	AWD2IE
Analog watchdog 3 status bit is set	AWD3	AWD3IE
End of sampling phase	EOSMP	EOSMPIE
Overrun	OVR	OVRIE
Injected context queue overflows	JQOVF	JQOVFIE

21.7 ADC registers (for each ADC)

Refer to Section 1.2 on page 73 for a list of abbreviations used in register descriptions.

21.7.1 ADC interrupt and status register (ADC_ISR)

Address offset: 0x00

Reset value: 0x00000000

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 JQOVF: Injected context queue overflow

This bit is set by hardware when an Overflow of the Injected Queue of Context occurs. It is cleared by software writing 1 to it. Refer to Section 21.4.21: Queue of context for injected conversions for more information.

0: No injected context queue overflow occurred (or the flag event was already acknowledged and cleared by software)

1: Injected context queue overflow has occurred

Bit 9 AWD3: Analog watchdog 3 flag

This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT3[7:0] and HT3[7:0] of ADC_TR3 register. It is cleared by software writing 1 to it.

0 : No analog watchdog 3 event occurred (or the flag event was already acknowledged and cleared by software)

1: Analog watchdog 3 event occurred

Bit 8 AWD2: Analog watchdog 2 flag

This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT2[7:0] and HT2[7:0] of ADC_TR2 register. It is cleared by software writing 1 to it.

0 : No analog watchdog 2 event occurred (or the flag event was already acknowledged and cleared by software)

1: Analog watchdog 2 event occurred

Bit 7 AWD1: Analog watchdog 1 flag

This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT1[11:0] and HT1[11:0] of ADC_TR1 register. It is cleared by software. writing 1 to it.

0: No analog watchdog 1 event occurred (or the flag event was already acknowledged and cleared by software)

1: Analog watchdog 1 event occurred

Bit 6 JEOS: Injected channel end of sequence flag

This bit is set by hardware at the end of the conversions of all injected channels in the group. It is cleared by software writing 1 to it.

0: Injected conversion sequence not complete (or the flag event was already acknowledged and cleared by software)

1: Injected conversions complete

Bit 5 JEOC: Injected channel end of conversion flag

This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADC_JDRy register

0: Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software)

1: Injected channel conversion complete

Bit 4 OVR: ADC overrun

This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to it.

0 : No overrun occurred (or the flag event was already acknowledged and cleared by software)

1: Overrun has occurred

Bit 3 EOS: End of regular sequence flag

This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is cleared by software writing 1 to it.

0: Regular Conversions sequence not complete (or the flag event was already acknowledged and cleared by software)

1: Regular Conversions sequence complete

Bit 2 EOC: End of conversion flag

This bit is set by hardware at the end of each regular conversion of a channel when a new data is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register

0 : Regular channel conversion not complete (or the flag event was already acknowledged and cleared by software)

1: Regular channel conversion complete

Bit 1 EOSMP: End of sampling flag

This bit is set by hardware during the conversion of any channel (only for regular channels), at the end of the sampling phase.

0 : not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)

1: End of sampling phase reached

Bit 0 ADRDY: ADC ready

This bit is set by hardware after the ADC has been enabled (bit ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests.

It is cleared by software writing 1 to it.

0: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)

1: ADC is ready to start conversion

21.7.2 ADC interrupt enable register (ADC_IER)

Address offset: 0x04

Reset value: 0x00000000

Res.

Res:

Res.

JQOVF IE

AWD31E

AWD21E

AWD1IE

JEOSIE

JEOCIE

OVRIE

EOSIE

EOCIE

EOSMP IE

ADRDY IE

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 JQOVFIE: Injected context queue overflow interrupt enable

This bit is set and cleared by software to enable/disable the Injected Context Queue Overflow interrupt.

0: Injected Context Queue Overflow interrupt disabled

1: Injected Context Queue Overflow interrupt enabled. An interrupt is generated when the JQOVF bit is set.

Note: The software is allowed to write this bit only when JADSTART

= 0

(which ensures that no

injected conversion is ongoing).

Bit 9 AWD3IE: Analog watchdog 3 interrupt enable

This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt.

0 : Analog watchdog 3 interrupt disabled

1: Analog watchdog 3 interrupt enabled

Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

Bit 8 AWD2IE: Analog watchdog 2 interrupt enable

This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt.

0 : Analog watchdog 2 interrupt disabled

1: Analog watchdog 2 interrupt enabled

Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

Bit 7 AWD1IE: Analog watchdog 1 interrupt enable

This bit is set and cleared by software to enable/disable the analog watchdog 1 interrupt.

0 : Analog watchdog 1 interrupt disabled

1: Analog watchdog 1 interrupt enabled

Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

Bit 6 JEOSIE: End of injected sequence of conversions interrupt enable

This bit is set and cleared by software to enable/disable the end of injected sequence of conversions interrupt.

0: JEOS interrupt disabled

1: JEOS interrupt enabled. An interrupt is generated when the JEOS bit is set.

Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing).

Bit 5 JEOCIE: End of injected conversion interrupt enable

This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt.

0: JEOC interrupt disabled.

1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.

Note: The software is allowed to write this bit only when JADSTART

= 0

(which ensures that no

injected conversion is ongoing).

Bit 4 OVRIE: Overrun interrupt enable

This bit is set and cleared by software to enable/disable the Overrun interrupt of a regular

conversion.

0: Overrun interrupt disabled

1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

Bit 3 EOSIE: End of regular sequence of conversions interrupt enable

This bit is set and cleared by software to enable/disable the end of regular sequence of conversions interrupt.

0: EOS interrupt disabled

1: EOS interrupt enabled. An interrupt is generated when the EOS bit is set.

Note: The software is allowed to write this bit only when ADSTART

= 0

(which ensures that no regular conversion is ongoing).

Bit 2 EOCIE: End of regular conversion interrupt enable

This bit is set and cleared by software to enable/disable the end of a regular conversion interrupt.

0: EOC interrupt disabled.

1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

Bit 1 EOSMPIE: End of sampling flag interrupt enable for regular conversions

This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt for regular conversions.

0: EOSMP interrupt disabled.

1: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

Bit 0 ADRDYIE: ADC ready interrupt enable

This bit is set and cleared by software to enable/disable the ADC Ready interrupt.

0: ADRDY interrupt disabled

1: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.

Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

21.7.3 ADC control register (ADC_CR)

Address offset: 0x08

Reset value: 0x2000 0000

Res.	Res.	Res.	Res:	Res.	Res.	Res.	Resu	Res.	Res.	JADST P	ADSTP	JADST ART	ADSTA RT	ADDIS	ADEN
										rs	rs	rs	rs	rs	rs

Bit 31 ADCAL: ADC calibration

This bit is set by software to start the calibration of the ADC. Program first the bit ADCALDIF to determine if this calibration applies for single-ended or differential inputs mode. It is cleared by hardware after calibration is complete.

0 : Calibration complete

1: Write 1 to calibrate the ADC. Read at 1 means that a calibration in progress.

Note: The software is allowed to launch a calibration by setting ADCAL only when ADEN = 0. The software is allowed to update the calibration factor by writing ADC_CALFACT only when

A D E N = 1

and

A D S T A R T = 0

and JADSTART

= 0

(ADC enabled and no conversion is ongoing)

Bit 30 ADCALDIF: Differential mode for calibration

This bit is set and cleared by software to configure the single-ended or differential inputs mode for the calibration.

0: Writing ADCAL launches a calibration in single-ended inputs mode.

1: Writing ADCAL launches a calibration in differential inputs mode.

Note: The software is allowed to write this bit only when the ADC is disabled and is not calibrating (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS

= 0

and ADEN

= 0

Bit 29 DEEPPWD: Deep-power-down enable

This bit is set and cleared by software to put the ADC in Deep-power-down mode.

0: ADC not in Deep-power down

1: ADC in Deep-power-down (default reset state)

Note: The software is allowed to write this bit only when the ADC is disabled (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).

Bit 28 ADVREGEN: ADC voltage regulator enable

This bits is set by software to enable the ADC voltage regulator.

Before performing any operation such as launching a calibration or enabling the ADC, the ADC voltage regulator must first be enabled and the software must wait for the regulator start-up time.

0: ADC Voltage regulator disabled

1: ADC Voltage regulator enabled.

For more details about the ADC voltage regulator enable and disable sequences, refer to

Section 21.4.6: ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN).

The software can program this bit field only when the ADC is disabled (ADCAL = 0,

JADSTART

= 0

,ADSTART

= 0

,ADSTP

= 0

,ADDIS

= 0

and ADEN

= 0

Bits 27:6 Reserved, must be kept at reset value.

Bit 5 JADSTP: ADC stop of injected conversion command

This bit is set by software to stop and discard an ongoing injected conversion (JADSTP Command).

It is cleared by hardware when the conversion is effectively discarded and the ADC injected sequence and triggers can be re-configured. The ADC is then ready to accept a new start of injected conversions (JADSTART command).

0 : No ADC stop injected conversion command ongoing

1: Write 1 to stop injected conversions ongoing. Read 1 means that an ADSTP command is in progress.

Note: The software is allowed to set JADSTP only when JADSTART = 1 and ADDIS = 0 (ADC is enabled and eventually converting an injected conversion and there is no pending request to disable the ADC)

In Auto-injection mode (JAUTO = 1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP)

Bit 4 ADSTP: ADC stop of regular conversion command

This bit is set by software to stop and discard an ongoing regular conversion (ADSTP Command).

It is cleared by hardware when the conversion is effectively discarded and the ADC regular

sequence and triggers can be re-configured. The ADC is then ready to accept a new start of regular conversions (ADSTART command).

0 : No ADC stop regular conversion command ongoing

1: Write 1 to stop regular conversions ongoing. Read 1 means that an ADSTP command is in progress.

Note: The software is allowed to set ADSTP only when ADSTART = 1 and ADDIS = 0 (ADC is enabled and eventually converting a regular conversion and there is no pending request to disable the ADC).

In auto-injection mode (JAUTO = 1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP).

In dual ADC regular simultaneous mode and interleaved mode, the bit ADSTP of the

master ADC must be used to stop regular conversions. The other ADSTP bit is inactive.

Bit 3 JADSTART: ADC start of injected conversion

This bit is set by software to start ADC conversion of injected channels. Depending on the configuration bits JEXTEN[1:0], a conversion starts immediately (software trigger configuration) or once an injected hardware trigger event occurs (hardware trigger configuration).

It is cleared by hardware:

in single conversion mode when software trigger is selected (JEXTSEL = 0x0): at the assertion of the End of Injected Conversion Sequence (JEOS) flag.

in all cases: after the execution of the JADSTP command, at the same time that JADSTP is cleared by hardware.

0 : No ADC injected conversion is ongoing.

1: Write 1 to start injected conversions. Read 1 means that the ADC is operating and eventually converting an injected channel.

Note: The software is allowed to set JADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC).

In auto-injection mode (JAUTO = 1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared)

Bit 2 ADSTART: ADC start of regular conversion

This bit is set by software to start ADC conversion of regular channels. Depending on the configuration bits EXTEN[1:0], a conversion starts immediately (software trigger configuration) or once a regular hardware trigger event occurs (hardware trigger configuration).

It is cleared by hardware:

in single conversion mode when software trigger is selected (EXTSEL = 0x0): at the assertion of the End of Regular Conversion Sequence (EOS) flag.

in all cases: after the execution of the ADSTP command, at the same time that ADSTP is cleared by hardware.

0 : No ADC regular conversion is ongoing.

1: Write 1 to start regular conversions. Read 1 means that the ADC is operating and eventually converting a regular channel.

Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC)

In auto-injection mode (JAUTO = 1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared)

Bit 1 ADDIS: ADC disable command

This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state).

It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time).

0: no ADDIS command ongoing

1: Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress.

Note: The software is allowed to set ADDIS only when ADEN = 1 and both ADSTART = 0 and JADSTART

= 0

(which ensures that no conversion is ongoing)

Bit 0 ADEN: ADC enable control

This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the flag ADRDY has been set.

It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command.

0: ADC is disabled (OFF state)

1: Write 1 to enable the ADC.

Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0) except for bit ADVREGEN which must be 1 (and the software must have wait for the startup time of the voltage regulator)

21.7.4 ADC configuration register (ADC_CFGR)

Address offset: 0x0C

Reset value: 0x80000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
JQDIS	AWD1CH[4:0]					JAUTO	JAWD1 EN	AWD1 EN	AWD1S GL	JQM	JDISC EN	DISCNUM[2:0]			DISC EN
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ALIGN	AUT DLY	CONT	OVR MOD	EXTEN[1:0]		EXTSEL[4:0]					RES[1:0]		Res.	DMA CFG	DMA EN
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw		rw	rw

Bit 31 JQDIS: Injected Queue disable

These bits are set and cleared by software to disable the Injected Queue mechanism :

0 : Injected Queue enabled

1: Injected Queue disabled

Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no regular nor injected conversion is ongoing).

A set or reset of JQDIS bit causes the injected queue to be flushed and the JSQR register is cleared.

Bits 30:26 AWD1CH[4:0]: Analog watchdog 1 channel selection

These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog.

00000: ADC analog input channel 0 monitored by AWD1 (available on ADC1 only)

00001: ADC analog input channel 1 monitored by AWD1

\dots

10010: ADC analog input channel 18 monitored by AWD1

others: reserved, must not be used

Note: Some channels are not connected physically. Keep the corresponding AWD1CH[4:0] setting to the reset value.

The channel selected by AWD1CH must be also selected into the SQRi or JSQRi registers.

The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

Bit 25 JAUTO: Automatic injected group conversion

This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion.

0: Automatic injected group conversion disabled

1: Automatic injected group conversion enabled

Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no regular nor injected conversion is ongoing).

When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit JAUTO of the slave ADC is no more writable and its content is equal to the bit JAUTO of the master ADC.

Bit 24 JAWD1EN: Analog watchdog 1 enable on injected channels

This bit is set and cleared by software

0 : Analog watchdog 1 disabled on injected channels

1: Analog watchdog 1 enabled on injected channels

Note: The software is allowed to write this bit only when JADSTART

= 0

(which ensures that no

injected conversion is ongoing).

Bit 23 AWD1EN: Analog watchdog 1 enable on regular channels

This bit is set and cleared by software

0 : Analog watchdog 1 disabled on regular channels

1: Analog watchdog 1 enabled on regular channels

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

Bit 22 AWD1SGL: Enable the watchdog 1 on a single channel or on all channels

This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWD1CH[4:0] bits or on all the channels

0 : Analog watchdog 1 enabled on all channels

1: Analog watchdog 1 enabled on a single channel

Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

Bit 21 JQM: JSQR queue mode

This bit is set and cleared by software.

It defines how an empty Queue is managed.

0: JSQR mode 0: The Queue is never empty and maintains the last written configuration into JSQR. 1: JSQR mode 1: The Queue can be empty and when this occurs, the software and hardware triggers of the injected sequence are both internally disabled just after the completion of the last valid injected sequence.

Refer to Section 21.4.21: Queue of context for injected conversions for more information.

Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing).

When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit JQM of the slave ADC is no more writable and its content is equal to the bit JQM of the master

A D C

Bit 20 JDISCEN: Discontinuous mode on injected channels

This bit is set and cleared by software to enable/disable discontinuous mode on the injected channels of a group.

0: Discontinuous mode on injected channels disabled

1: Discontinuous mode on injected channels enabled

Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing).

It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. When dual mode is enabled (bits DUAL of ADCx_CCR register are not equal to zero), the bit JDISCEN of the slave ADC is no more writable and its content is equal to the bit JDISCEN of the master ADC.

Bits 19:17 DISCNUM[2:0]: Discontinuous mode channel count

These bits are written by software to define the number of regular channels to be converted in discontinuous mode, after receiving an external trigger.

000: 1 channel

001: 2 channels

111: 8 channels

Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bits DISCNUM[2:0] of the slave ADC are no more writable and their content is equal to the bits DISCNUM[2:0] of the master ADC.

Bit 16 DISCEN: Discontinuous mode for regular channels

This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels.

0: Discontinuous mode for regular channels disabled

1: Discontinuous mode for regular channels enabled

Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1.

It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set.

The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit

DISCEN of the slave ADC is no more writable and its content is equal to the bit DISCEN of the master ADC.

Bit 15 ALIGN: Data alignment

This bit is set and cleared by software to select right or left alignment. Refer to Data register, data alignment and offset (ADC_DR, OFFSETy, OFFSETy_CH, ALIGN).

0 : Right alignment

1: Left alignment

Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

Bit 14 AUTDLY: Delayed conversion mode

This bit is set and cleared by software to enable/disable the Auto Delayed Conversion mode.

0: Auto-delayed conversion mode off

1: Auto-delayed conversion mode on

Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit AUTDLY of the slave ADC is no more writable and its content is equal to the bit AUTDLY of the master ADC.

Bit 13 CONT: Single / continuous conversion mode for regular conversions

This bit is set and cleared by software. If it is set, regular conversion takes place continuously until it is cleared.

0 : Single conversion mode

1: Continuous conversion mode

Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1.

The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit

CONT of the slave ADC is no more writable and its content is equal to the bit CONT of the

master ADC.

Bit 12 OVRMOD: Overrun mode

This bit is set and cleared by software and configure the way data overrun is managed.

0: ADC_DR register is preserved with the old data when an overrun is detected.

1: ADC_DR register is overwritten with the last conversion result when an overrun is detected.

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular

conversion is ongoing).

Bits 11:10 EXTEN[1:0]: External trigger enable and polarity selection for regular channels

These bits are set and cleared by software to select the external trigger polarity and enable the

trigger of a regular group.

00: Hardware trigger detection disabled (conversions can be launched by software)

01: Hardware trigger detection on the rising edge

10: Hardware trigger detection on the falling edge

11: Hardware trigger detection on both the rising and falling edges

Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

Bits 9:5 EXTSEL[4:0]: External trigger selection for regular group

These bits select the external event used to trigger the start of conversion of a regular group:

00000: Event 0

00001: Event 1

00010: Event 2

00011: Event 3

00100: Event 4

00101: Event 5

00110: Event 6

00111: Event 7

11111: Event 31

Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

Bits 4:3 RES[1:0]: Data resolution

These bits are written by software to select the resolution of the conversion.

00: 12-bit

01: 10-bit

10: 8-bit

11: 6-bit

Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

Bit 2 Reserved, must be kept at reset value.

Bit 1 DMACFG: Direct memory access configuration

This bit is set and cleared by software to select between two DMA modes of operation and is

effective only when DMAEN

= 1

0: DMA One Shot mode selected

1: DMA Circular mode selected

For more details, refer to Section : Managing conversions using the DMA

Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

In dual-ADC modes, this bit is not relevant and replaced by control bit DMACFG of the ADCx_CCR register.

Bit 0 DMAEN: Direct memory access enable

This bit is set and cleared by software to enable the generation of DMA requests. This allows to use the DMA to manage automatically the converted data. For more details, refer to Section : Managing conversions using the DMA.

0: DMA disabled

1: DMA enabled

Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

In dual-ADC modes, this bit is not relevant and replaced by control bits MDMA[1:0] of the

ADCx_CCR register.

21.7.5 ADC configuration register 2 (ADC_CFGR2)

Address offset: 0x10

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	SMPTRI G	BULB	SWTRI G	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	GCOM P
				rw	rw	rw									rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	ROV SM	TROVS	OVSS[3:0]				OVSR[2:0]			JOVSE	ROVSE
					rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:28 Reserved, must be kept at reset value.

Bit 27 SMPTRIG: Sampling time control trigger mode

This bit is set and cleared by software to enable the sampling time control trigger mode.

0 : Sampling time control trigger mode disabled

1: Sampling time control trigger mode enabled

The sampling time starts on the trigger rising edge, and the conversion on the trigger falling edge. EXTEN[1:0] bits should be set to 01. BULB bit must not be set when the SMPTRIG bit is set. When EXTEN[1:0] bits are set to 00 , set SWTRIG to start the sampling and clear SWTRIG bit to start the conversion.

Note: The software is allowed to write this bit only when ADSTART

= 0

(which ensures that no conversion is ongoing).

Bit 26 BULB: Bulb sampling mode

This bit is set and cleared by software to enable the bulb sampling mode.

0 : Bulb sampling mode disabled

1: Bulb sampling mode enabled. The sampling period starts just after the previous end of conversion.

SAMPTRIG bit must not be set when the BULB bit is set.

The very first ADC conversion is performed with the sampling time specified in SMPx bits.

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

Bit 25 SWTRIG: Software trigger bit for sampling time control trigger mode

This bit is set and cleared by software to enable the bulb sampling mode.

0 : Software trigger starts the conversion for sampling time control trigger mode

1: Software trigger starts the sampling for sampling time control trigger mode

Note: The software is allowed to write this bit only when ADSTART

= 0

(which ensures that no conversion is ongoing).

Bits 24:17 Reserved, must be kept at reset value.

Bit 16 GCOMP: Gain compensation mode

This bit is set and cleared by software to enable the gain compensation mode.

0: Regular ADC operating mode

1: Gain compensation enabled and applied on all channels

Note: The software is allowed to write this bit only when ADSTART

= 0

(which ensures that no conversion is ongoing).

Bits 15:11 Reserved, must be kept at reset value.

Bit 10 ROVSM: Regular Oversampling mode

This bit is set and cleared by software to select the regular oversampling mode.

0: Continued mode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)

1: Resumed mode: When injected conversions are triggered, the current oversampling is aborted

and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

Bit 9 TROVS: Triggered Regular Oversampling

This bit is set and cleared by software to enable triggered oversampling

0: All oversampled conversions for a channel are done consecutively following a trigger

1: Each oversampled conversion for a channel needs a new trigger

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no

conversion is ongoing).

Bits 8:5 OVSS[3:0]: Oversampling shift

This bitfield is set and cleared by software to define the right shifting applied to the raw oversampling result.

0000: No shift

0001: Shift 1-bit

0010: Shift 2-bits

0011: Shift 3-bits

0100: Shift 4-bits

0101: Shift 5-bits

0110: Shift 6-bits

0111: Shift 7-bits

1000: Shift 8-bits

Other codes reserved

Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing).

Bits 4:2 OVSR[2:0]: Oversampling ratio

This bitfield is set and cleared by software to define the oversampling ratio.

000: 2x

001: 4x

010: 8x

011: 16x

100: 32x

101: 64x

110: 128x

111: 256x

Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing).

Bit 1 JOVSE: Injected Oversampling Enable

This bit is set and cleared by software to enable injected oversampling.

0: Injected Oversampling disabled

1: Injected Oversampling enabled

Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)

Bit 0 ROVSE: Regular Oversampling Enable

This bit is set and cleared by software to enable regular oversampling.

0: Regular Oversampling disabled

1: Regular Oversampling enabled

Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)

21.7.6 ADC sample time register 1 (ADC_SMPR1)

Address offset: 0x14

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SMPPL US	Res:	SMP9[2:0]			SMP8[2:0]			SMP7[2:0]			SMP6[2:0]			SMP5[2:1]
rw		rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

SMP5[ 0]	SMP4[2:0]			SMP3[2:0]			SMP2[2:0]			SMP1[2:0]			SMP0[2:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bit 31 SMPPLUS: Addition of one clock cycle to the sampling time

1: 2.5 ADC clock cycle sampling time becomes 3.5 ADC clock cycles for the ADC_SMPR1 and ADC_SMPR2 registers.

0 : The sampling time remains set to 2.5 ADC clock cycles remains

To make sure no conversion is ongoing, the software is allowed to write this bit only when ADSTART

= 0

and JADSTART

= 0

Bit 30 Reserved, must be kept at reset value.

Bits 29:0 SMPx[2:0]: Channel x sampling time selection

(x = 9 to 0)

These bits are written by software to select the sampling time individually for each channel.

During sample cycles, the channel selection bits must remain unchanged.

000: 2.5 ADC clock cycles

001: 6.5 ADC clock cycles

010: 12.5 ADC clock cycles

011: 24.5 ADC clock cycles

100: 47.5 ADC clock cycles

101: 92.5 ADC clock cycles

110: 247.5 ADC clock cycles

111: 640.5 ADC clock cycles

Note: The software is allowed to write these bits only when ADSTART = 0 and

JADSTART = 0 (which ensures that no conversion is ongoing).

Some channels are not connected physically. Keep the corresponding SMPx[2:0]

setting to the reset value.

21.7.7 ADC sample time register 2 (ADC_SMPR2)

Address offset: 0x18

Reset value: 0x00000000

SMP15[0]	SMP14[2:0]			SMP13[2:0]			SMP12[2:0]			SMP11[2:0]			SMP10[2:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:27 Reserved, must be kept at reset value.

Bits 26:0 SMPx[2:0]: Channel x sampling time selection

(x = 18 to 10)

These bits are written by software to select the sampling time individually for each channel.

During sampling cycles, the channel selection bits must remain unchanged.

000: 2.5 ADC clock cycles

001: 6.5 ADC clock cycles

010: 12.5 ADC clock cycles

011: 24.5 ADC clock cycles

100: 47.5 ADC clock cycles

101: 92.5 ADC clock cycles

110: 247.5 ADC clock cycles

111: 640.5 ADC clock cycles

Note: The software is allowed to write these bits only when ADSTART = 0 and

JADSTART = 0 (which ensures that no conversion is ongoing).

Some channels are not connected physically. Keep the corresponding SMPx[2:0]

setting to the reset value.

21.7.8 ADC watchdog threshold register 1 (ADC_TR1)

Address offset: 0x20 Reset value: 0x0FFF 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	HT1[11:0]
				rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	AWDFILT[2:0]			LT1[11:0]
	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 HT1[11:0]: Analog watchdog 1 higher threshold

These bits are written by software to define the higher threshold for the analog watchdog 1.

Refer to Section 21.4.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx).

Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

Bit 15 Reserved, must be kept at reset value.

Bits 14:12 AWDFILT: Analog watchdog filtering parameter

This bit is set and cleared by software.

000: No filtering

001: two consecutive detection generates an AWDx flag or an interrupt

\dots

111: Eight consecutive detection generates an AWDx flag or an interrupt

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no

conversion is ongoing).

Bits 11:0 LT1[11:0]: Analog watchdog 1 lower threshold

These bits are written by software to define the lower threshold for the analog watchdog 1.

Refer to Section 21.4.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,

AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)

Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

21.7.9 ADC watchdog threshold register 2 (ADC_TR2)

Address offset: 0x24

Reset value: 0x00FF 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	HT2[7:0]
								rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	LT2[7:0]
								rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 HT2[7:0]: Analog watchdog 2 higher threshold

These bits are written by software to define the higher threshold for the analog watchdog 2. Refer to Section 21.4.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)

Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

Bits 15:8 Reserved, must be kept at reset value.

Bits 7:0 LT2[7:0]: Analog watchdog 2 lower threshold

These bits are written by software to define the lower threshold for the analog watchdog 2. Refer to Section 21.4.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)

Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

21.7.10 ADC watchdog threshold register 3 (ADC_TR3)

Address offset: 0x28

Reset value: 0x00FF 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Resr	Res.	Res.	HT3[7:0]
								rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Resr	Res.	Res.	Res.	Res.	Res.	Res.	LT3[7:0]
								rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 HT3[7:0]: Analog watchdog 3 higher threshold

These bits are written by software to define the higher threshold for the analog watchdog 3. Refer to Section 21.4.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)

Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

Bits 15:8 Reserved, must be kept at reset value.

Bits 7:0 LT3[7:0]: Analog watchdog 3 lower threshold

These bits are written by software to define the lower threshold for the analog watchdog 3.

This watchdog compares the 8-bit of LT3 with the 8 MSB of the converted data.

Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

21.7.11 ADC regular sequence register 1 (ADC_SQR1)

Address offset: 0x30

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	SQ4[4:0]					Res.	SQ3[4:0]					Res.	SQ2[4]
			rw	rw	rw	rw	rw		rw	rw	rw	rw	rw		rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ2[3:0]				Res.	SQ1[4:0]					Res.	Res.	L[3:0]
rw	rw	rw	rw		rw	rw	rw	rw	rw			rw	rw	rw	rw

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:24 SQ4[4:0]: fourth conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the fourth in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

Bit 23 Reserved, must be kept at reset value. Bits 22:18 SQ3[4:0]: third conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the third in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

Bit 17 Reserved, must be kept at reset value.

Bits 16:12 SQ2[4:0]: second conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the second in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

Bit 11 Reserved, must be kept at reset value.

Bits 10:6 SQ1[4:0]: first conversion in regular sequence

These bits are written by software with the channel number ( 0 to 18 ) assigned as the first in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

Bits 5:4 Reserved, must be kept at reset value.

Bits 3:0 L[3:0]: Regular channel sequence length

These bits are written by software to define the total number of conversions in the regular channel conversion sequence.

0000: 1 conversion

0001: 2 conversions

\dots

1111: 16 conversions

Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

Note:

Some channels are not connected physically and must not be selected for conversion.

21.7.12 ADC regular sequence register 2 (ADC_SQR2)

Address offset: 0x34

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	SQ9[4:0]					Res.	SQ8[4:0]					Res.	SQ7[4]
			rw	rw	rw	rw	rw		rw	rw	rw	rw	rw		rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ7[3:0]				Res.	SQ6[4:0]					Res.	SQ5[4:0]
rw	rw	rw	rw		rw	rw	rw	rw	rw		rw	rw	rw	rw	rw

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:24 SQ9[4:0]: 9th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 9th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

Bit 23 Reserved, must be kept at reset value.

Bits 22:18 SQ8[4:0]: 8th conversion in regular sequence

These bits are written by software with the channel number ( 0 to 18 ) assigned as the 8th in the regular conversion sequence

Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

Bit 17 Reserved, must be kept at reset value.

Bits 16:12 SQ7[4:0]: 7th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 7th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

Bit 11 Reserved, must be kept at reset value.

Bits 10:6 SQ6[4:0]: 6th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 6th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

Bit 5 Reserved, must be kept at reset value.

Bits 4:0 SQ5[4:0]: 5th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 5th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

Note:

Some channels are not connected physically and must not be selected for conversion.

21.7.13 ADC regular sequence register 3 (ADC_SQR3)

Address offset: 0x38

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	SQ14[4:0]					Res.	SQ13[4:0]					Res.	SQ12[4]
			rw	rw	rw	rw	rw		rw	rw	rw	rw	rw		rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ12[3:0]				Res.	SQ11[4:0]					Res.	SQ10[4:0]
rw	rw	rw	rw		rw	rw	rw	rw	rw		rw	rw	rw	rw	rw

Bits 31:29 Reserved, must be kept at reset value. Bits 28:24 SQ14[4:0]: 14th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 14th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

Bit 23 Reserved, must be kept at reset value.

Bits 22:18 SQ13[4:0]: 13th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 13th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

Bit 17 Reserved, must be kept at reset value.

Bits 16:12 SQ12[4:0]: 12th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 12th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

Bit 11 Reserved, must be kept at reset value.

Bits 10:6 SQ11[4:0]: 11th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 11th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

Bit 5 Reserved, must be kept at reset value.

Bits 4:0 SQ10[4:0]: 10th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 10th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

Note:

Some channels are not connected physically and must not be selected for conversion.

21.7.14 ADC regular sequence register 4 (ADC_SQR4)

Address offset: 0x3C Reset value: 0x00000000

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:6 SQ16[4:0]: 16th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 16th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

Bit 5 Reserved, must be kept at reset value.

Bits 4:0 SQ15[4:0]: 15th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 15th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

Note:

Some channels are not connected physically and must not be selected for conversion.

21.7.15 ADC regular data register (ADC_DR)

Address offset: 0x40

Reset value: 0x00000000

RDATA[10:0]
$r$	r	r	r	r	r	r	r	$r$	r	r	r	r	r	r	r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 RDATA[15:0]: Regular data converted

These bits are read-only. They contain the conversion result from the last converted regular channel. The data are left- or right-aligned as described in Section 21.4.26: Data management.

21.7.16 ADC injected sequence register (ADC_JSQR)

Address offset: 0x4C

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
JSQ4[4:0]					Res	JSQ3[4:0]					Res.	JSQ2[4:1]
rw	rw	rw	rw	rw		rw	rw	rw	rw	rw		rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JSQ20	Res.	JSQ1[4:0]					JEXTEN[1:0]		JEXTSEL[4:0]					JL[1:0]
rw		rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:27 JSQ4[4:0]: fourth conversion in the injected sequence

These bits are written by software with the channel number ( 0 to 18 ) assigned as the fourth in the injected conversion sequence.c

Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing), unless the context queue is enabled (JQDIS = 0 in the ADC_CFGR register).

Bit 26 Reserved, must be kept at reset value.

Bits 25:21 JSQ3[4:0]: third conversion in the injected sequence

These bits are written by software with the channel number ( 0 to 18 ) assigned as the third in the injected conversion sequence.

Bit 20 Reserved, must be kept at reset value.

Bits 19:15 JSQ2[4:0]: second conversion in the injected sequence

These bits are written by software with the channel number (0 to 18) assigned as the second in the injected conversion sequence.

Bit 14 Reserved, must be kept at reset value.

Bits 13:9 JSQ1[4:0]: first conversion in the injected sequence

These bits are written by software with the channel number (0 to 18) assigned as the first in the injected conversion sequence.

Bits 8:7 JEXTEN[1:0]: External Trigger Enable and Polarity Selection for injected channels

These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group.

00: If JQDIS

= 0

(queue enabled),Hardware and software trigger detection disabled

00: If JQDIS = 1 (queue disabled), Hardware trigger detection disabled (conversions can be launched by software)

01: Hardware trigger detection on the rising edge

10: Hardware trigger detection on the falling edge

11: Hardware trigger detection on both the rising and falling edges

Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing).

J Q M = 1

and if the Queue of Context becomes empty,the software and hardware triggers of the injected sequence are both internally disabled (refer to Section 21.4.21: Queue of context for injected conversions)

Bits 6:2 JEXTSEL[4:0]: External Trigger Selection for injected group

These bits select the external event used to trigger the start of conversion of an injected

group:

00000: Event 0

00001: Event 1

00010: Event 2

00011: Event 3

00100: Event 4

00101: Event 5

00110: Event 6

00111: Event 7

\dots

11111: Event 31

Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing).

Bits 1:0 JL[1:0]: Injected channel sequence length

These bits are written by software to define the total number of conversions in the injected channel conversion sequence.

00: 1 conversion

01: 2 conversions

10: 3 conversions

11: 4 conversions

Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing).

Note:

Some channels are not connected physically and must not be selected for conversion.

21.7.17 ADC offset y register (ADC_OFRy)

Address offset:

0 \times 60 + 0 \times 04 * (y - 1), (y = 1 to 4)

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OFFSET EN	OFFSET_CH[4:0]					SATEN	OFFSE TPOS	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Res.	Res.	Res.	Res.	OFFSET[11:0]
				rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bit 31 OFFSET_EN: Offset y enable

This bit is written by software to enable or disable the offset programmed into bits

OFFSETy[11:0].

Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

Bits 30:26 OFFSET_CH[4:0]: Channel selection for the data offset y

These bits are written by software to define the channel to which the offset programmed into

bits OFFSETy[11:0] applies.

Note: The software is allowed to write these bits only when ADSTART = 0 and

JADSTART

= 0

(which ensures that no conversion is ongoing).

Some channels are not connected physically and must not be selected for the data

offset

y

Bit 25 SATEN: Saturation enable

This bit is set and cleared by software to enable the saturation at

0 \times 000

and

0 \times F F F

for the

offset function.

0 : No saturation control, offset result can be signed

1: Saturation enabled, offset result unsigned and saturated at 0x000 and 0xFFF

Note: The software is allowed to write these bits only when ADSTART = 0 and

JADSTART

= 0

(which ensures that no conversion is ongoing).

Bit 24 OFFSETPOS: Positive offset

This bit is set and cleared by software to enable the positive offset.

0 : Negative offset

1: Positive offset

Note: The software is allowed to write these bits only when ADSTART = 0 and

JADSTART = 0 (which ensures that no conversion is ongoing).

Bits 23:12 Reserved, must be kept at reset value.

Bits 11:0 OFFSET[11:0]: Data offset

y

for the channel programmed into bits OFFSETy_CH[4:0] These bits are written by software to define the offset

y

to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offsety must be programmed in the bits OFFSETy_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion).

Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART

= 0

(which ensures that no conversion is ongoing).

If several offset (OFFSETy) point to the same channel,only the offset with the lowest

x

value is considered for the subtraction.

Ex: if OFFSET1_CH[4:0]=4 and OFFSET2_CH[4:0]=4, this is OFFSET1[11:0] which is

subtracted when converting channel 4.

21.7.18 ADC injected channel y data register (ADC_JDRy)

Address offset:

0 \times 80 + 0 \times 04 * (y - 1), (y = 1 to 4)

Reset value: 0x00000000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 JDATA[15:0]: Injected data

These bits are read-only. They contain the conversion result from injected channel

y

. The

data are left -or right-aligned as described in Section 21.4.26: Data management.

21.7.19 ADC analog watchdog 2 configuration register (ADC_AWD2CR)

Address offset: 0xA0

Reset value: 0x00000000

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:0 AWD2CH[18:0]: Analog watchdog 2 channel selection

These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2 .

AWD2CH[i]

= 0

: ADC analog input channel i is not monitored by AWD2

AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2

When AWD2CH[18:0]

= 000 . .0

,the analog watchdog 2 is disabled

Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

Some channels are not connected physically and must not be selected for the analog watchdog.

21.7.20 ADC analog watchdog 3 configuration register (ADC_AWD3CR)

Address offset: 0xA4

Reset value: 0x00000000

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:0 AWD3CH[18:0]: Analog watchdog 3 channel selection

These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3.

AWD3CH[i]

= 0

: ADC analog input channel i is not monitored by AWD3

AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3

When

AWD 3 CH [18 : 0] = 000 . .0

,the analog watchdog 3 is disabled

Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers.

The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

Some channels are not connected physically and must not be selected for the analog

watchdog.

21.7.21 ADC differential mode selection register (ADC_DIFSEL)

Address offset: 0xB0

Reset value: 0x00000000

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:0 DIFSEL[18:0]: Differential mode for channels 18 to 0 .

These bits are set and cleared by software. They allow to select if a channel is configured as single-ended or differential mode.

DIFSEL[i] = 0: ADC analog input channel is configured in single ended mode

DIFSEL[i] = 1: ADC analog input channel i is configured in differential mode

Note: The DIFSEL bits corresponding to channels that are either connected to a single-ended I/O port or to an internal channel must be kept their reset value (single-ended input mode).

The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0,

JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).

21.7.22 ADC calibration factors (ADC_CALFACT)

Address offset: 0xB4

Reset value: 0x00000000

Resr	Res.	Resr	Res.	Res.	Res.	Res.	Rest	Resr	CALFACT_S[6:0]
									rw	rw	rw	rw	rw	rw	rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:16 CALFACT_D[6:0]: Calibration Factors in differential mode

These bits are written by hardware or by software.

Once a differential inputs calibration is complete, they are updated by hardware with the calibration factors.

Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new differential calibration is launched.

Note: The software is allowed to write these bits only when

A D E N = 1

A D S T A R T = 0

and JADSTART = 0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing).

Bits 15:7 Reserved, must be kept at reset value.

Bits 6:0 CALFACT_S[6:0]: Calibration Factors In single-ended mode

These bits are written by hardware or by software.

Once a single-ended inputs calibration is complete, they are updated by hardware with the calibration factors.

Software can write these bits with a new calibration factor. If the new calibration factor is different

from the current one stored into the analog ADC, it is then applied once a new single-ended calibration is launched.

Note: The software is allowed to write these bits only when

A D E N = 1

,ADSTART

= 0

and

JADSTART = 0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing).

21.7.23 ADC Gain compensation Register (ADC_GCOMP)

Address offset: 0xC0

Reset value: 0x00000000

Bits 31:14 Reserved, must be kept at reset value.

Bits 13:0 GCOMPCOEFF[13:0]: Gain compensation coefficient

These bits are set and cleared by software to program the gain compensation coefficient.

0010000000000: gain factor of 0.5

0100000000000: gain factor of 1

1000000000000: gain factor of 2

1100000000000: gain factor of 3

The coefficient is divided by 4096 to get the gain factor ranging from 0 to 3.999756.

Note: This gain compensation is only applied when GCOMP bit of ADC_CFGR2 register is 1 .

21.8 ADC common registers

These registers define the control and status registers common to master and slave ADCs:

21.8.1 ADCx common status register (ADCx_CSR) (x = 12 or 345)

Address offset: 0x300

Reset value: 0x00000000

This register provides an image of the status bits of the different ADCs. Nevertheless it is read-only and does not allow to clear the different status bits. Instead each status bit must be cleared by writing 0 to it in the corresponding ADC_ISR register.

One interface controls ADC1 and ADC2, while the other interface controls ADC3, ADC4 and ADC5.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	JQOVF SLV	AWD3 SLV	AWD2 SLV	AWD1 SLV	JEOS SLV	JEOC SLV	OVR_	EOS_	EOC_	EOSMP SLV	ADRDY SLV
					r	r	r	r	r	r	r	r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Res	Res.	Res.	Res.	Res.	JQOVF MST	AWD3 MST	AWD2 MST	AWD1 MST	JEOS MST	JEOC MST	OVR MST	EOS MST	EOC MST	EOSMP MST	ADRDY MST
					r	r	r	r	r	r	r	r	r	r	r

Bits 31:27 Reserved, must be kept at reset value.

Bit 26 JQOVF_SLV: Injected Context Queue Overflow flag of the slave ADC

This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register.

Bit 25 AWD3_SLV: Analog watchdog 3 flag of the slave ADC

This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register.

Bit 24 AWD2_SLV: Analog watchdog 2 flag of the slave ADC

This bit is a copy of the AWD2 bit in the corresponding ADC_ISR register.

Bit 23 AWD1_SLV: Analog watchdog 1 flag of the slave ADC

This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register.

Bit 22 JEOS_SLV: End of injected sequence flag of the slave ADC

This bit is a copy of the JEOS bit in the corresponding ADC_ISR register.

Bit 21 JEOC_SLV: End of injected conversion flag of the slave ADC

This bit is a copy of the JEOC bit in the corresponding ADC_ISR register.

Bit 20 OVR_SLV: Overrun flag of the slave ADC

This bit is a copy of the OVR bit in the corresponding ADC_ISR register.

Bit 19 EOS_SLV: End of regular sequence flag of the slave ADC. This bit is a copy of the EOS bit in the corresponding ADC_ISR register.

Bit 18 EOC_SLV: End of regular conversion of the slave ADC

This bit is a copy of the EOC bit in the corresponding ADC_ISR register.

Bit 17 EOSMP_SLV: End of Sampling phase flag of the slave ADC

This bit is a copy of the EOSMP2 bit in the corresponding ADC_ISR register.

Bit 16 ADRDY_SLV: Slave ADC ready

This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register.

Bits 15:11 Reserved, must be kept at reset value.

Bit 10 JQOVF_MST: Injected Context Queue Overflow flag of the master ADC

This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register.

Bit 9 AWD3_MST: Analog watchdog 3 flag of the master ADC

This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register.

Bit 8 AWD2_MST: Analog watchdog 2 flag of the master ADC

This bit is a copy of the AWD2 bit in the corresponding ADC_ISR register.

Bit 7 AWD1_MST: Analog watchdog 1 flag of the master ADC

This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register.

Bit 6 JEOS_MST: End of injected sequence flag of the master ADC

This bit is a copy of the JEOS bit in the corresponding ADC_ISR register.

Bit

5

JEOC_MST: End of injected conversion flag of the master ADC

This bit is a copy of the JEOC bit in the corresponding ADC_ISR register.

Bit 4 OVR_MST: Overrun flag of the master ADC

This bit is a copy of the OVR bit in the corresponding ADC_ISR register.

Bit

3

EOS_MST: End of regular sequence flag of the master ADC

This bit is a copy of the EOS bit in the corresponding ADC_ISR register.

Bit 2 EOC_MST: End of regular conversion of the master ADC

This bit is a copy of the EOC bit in the corresponding ADC_ISR register.

Bit 1 EOSMP_MST: End of Sampling phase flag of the master ADC

This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register.

Bit 0 ADRDY_MST: Master ADC ready

This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register.

21.8.2 ADCx common control register (ADCx_CCR) (x = 12 or 345)

Address offset: 0x308

Reset value: 0x00000000

One interface controls ADC1 and ADC2, while the other interface controls ADC3, ADC4 and ADC5.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	VBATS EL	VSENSES EL	VREF EN	PRESC[3:0]				CKMODE[1:0]
							rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MDMA[1:0]		DMA CFG	Res.	DELAY[3:0]				Res.	Res.	Res.	DUAL[4:0]
rw	rw	rw		rw	rw	rw	rw				rw	rw	rw	rw	rw

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 VBATSEL: VBAT selection

This bit is set and cleared by software to control VBAT.

0 : V_{BAT}

channel disabled.

V_{BAT}

channel enabled

Bit 23 VSENSESEL:

V_{TS}

selection

This bit is set and cleared by software to control

V_{TS}

0: Temperature sensor channel disabled

1: Temperature sensor channel enabled

Bit 22 VREFEN:

V_{REFINT}

enable

This bit is set and cleared by software to enable/disable the

V_{REFINT}

channel.

V_{REFINT}

channel disabled

V_{REFINT}

channel enabled

Bits 21:18 PRESC[3:0]: ADC prescaler

These bits are set and cleared by software to select the frequency of the clock to the ADC.

The clock is common for all the ADCs.

0000: input ADC clock not divided

0001: input ADC clock divided by 2

0010: input ADC clock divided by 4

0011: input ADC clock divided by 6

0100: input ADC clock divided by 8

0101: input ADC clock divided by 10

0110: input ADC clock divided by 12

0111: input ADC clock divided by 16

1000: input ADC clock divided by 32

1001: input ADC clock divided by 64

1010: input ADC clock divided by 128

1011: input ADC clock divided by 256

other: reserved

Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The ADC

prescaler value is applied only when CKMODE[1:0] = 00.

Bits 17:16 CKMODE[1:0]: ADC clock mode

These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs):

00: adc_ker_ck (x = 123) (Asynchronous clock mode), generated at product level (refer to Section 6: Reset and clock control (RCC))

01: adc_hclk/1 (Synchronous clock mode). This configuration must be enabled only if the AHB clock prescaler is set (HPRE[3:0] = 0xxx in RCC_CFGR register) and if the system clock has a

50 %

duty cycle.

10: adc_hclk/2 (Synchronous clock mode)

11: adc_hclk/4 (Synchronous clock mode)

In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion.

Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).

Bits 15:14 MDMA[1:0]: Direct memory access mode for dual ADC mode

This bitfield is set and cleared by software. Refer to the DMA controller section for more details.

00: MDMA mode disabled

01: Reserved

10: MDMA mode enabled for 12 and 10-bit resolution

11: MDMA mode enabled for 8 and 6-bit resolution

Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

Bit 13 DMACFG: DMA configuration (for dual ADC mode)

This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1.

0: DMA One Shot mode selected

1: DMA Circular mode selected

For more details, refer to Section : Managing conversions using the DMA

Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

Bit 12 Reserved, must be kept at reset value.

Bits 11:8 DELAY: Delay between 2 sampling phases

These bits are set and cleared by software. These bits are used in dual interleaved modes.

Refer to Table 176 for the value of ADC resolution versus DELAY bits values.

Note: The software is allowed to write these bits only when the ADCs are disabled

(ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).

Bits 7:5 Reserved, must be kept at reset value.

Bits 4:0 DUAL[4:0]: Dual ADC mode selection

These bits are written by software to select the operating mode.

All the ADCs independent:

0000: Independent mode

00001 to 01001: Dual mode, master and slave ADCs working together

00001: Combined regular simultaneous + injected simultaneous mode

00010: Combined regular simultaneous + alternate trigger mode

00011: Combined Interleaved mode + injected simultaneous mode

00100: Reserved

00101: Injected simultaneous mode only

00110: Regular simultaneous mode only

00111: Interleaved mode only

01001: Alternate trigger mode only

All other combinations are reserved and must not be programmed

Note: The software is allowed to write these bits only when the ADCs are disabled

(ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).

Table 176. DELAY bits versus ADC resolution

DELAY bits	12-bit resolution	10-bit resolution	8-bit resolution	6-bit resolution
0000	1 * Tadc_ker_ck	1 * Tadc_ker_ck	1 * Tadc_ker_ck	1 * Tadc_ker_ck
0001	2 * Tadc_ker_ck	2 * Tadc_ker_ck	2 * Tadc_ker_ck	2 * Tadc_ker_ck
0010	3 * Tadc_ker_ck	3 * Tadc_ker_ck	3 * Tadc_ker_ck	3 * Tadc_ker_ck

Table 176. DELAY bits versus ADC resolution (continued)

DELAY bits	12-bit resolution	10-bit resolution	8-bit resolution	6-bit resolution
0011	4 * Tadc_ker_ck	4 * Tadc_ker_ck	4 * Tadc_ker_ck	4 * Tadc_ker_ck
0100	5 * Tadc_ker_ck	5 * Tadc_ker_ck	5 * Tadc_ker_ck	5 * Tadc_ker_ck
0101	6 * Tadc_ker_ck	6 * Tadc_ker_ck	6 * Tadc_ker_ck	6 * Tadc_ker_ck
0110	7 * Tadc_ker_ck	7 * Tadc_ker_ck	7 * Tadc_ker_ck	6 * Tadc_ker_ck
0111	8 * Tadc_ker_ck	8 * Tadc_ker_ck	8 * Tadc_ker_ck	6 * Tadc_ker_ck
1000	9 * Tadc_ker_ck	9 * Tadc_ker_ck	8 * Tadc_ker_ck	6 * Tadc_ker_ck
1001	10 * Tadc_ker_ck	10 * Tadc_ker_ck	8 * Tadc_ker_ck	6 * Tadc_ker_ck
1010	11 * Tadc_ker_ck	10 * Tadc_ker_ck	8 * Tadc_ker_ck	6 * Tadc_ker_ck
1011	12 * Tadc_ker_ck	10 * Tadc_ker_ck	8 * Tadc_ker_ck	6 * Tadc_ker_ck
others	12 * Tadc_ker_ck	10 * Tadc_ker_ck	8 * Tadc_ker_ck	6 * Tadc_ker_ck

21.8.3 ADCx common regular data register for dual mode (ADCx_CDR) (x = 12 or 345)

Address offset: 0x30C

Reset value: 0x00000000

One interface controls ADC1 and ADC2, while the other interface controls ADC3, ADC4 and ADC5.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RDATA_SLV[15:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RDATA_MST[15:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:16 RDATA_SLV[15:0]: Regular data of the slave ADC

In dual mode, these bits contain the regular data of the slave ADC. Refer to Section 21.4.30: Dual ADC modes.

The data alignment is applied as described in Section : Data register, data alignment and offset (ADC_DR, OFFSETy, OFFSETy_CH, ALIGN))

Bits 15:0 RDATA_MST[15:0]: Regular data of the master ADC.

In dual mode, these bits contain the regular data of the master ADC. Refer to Section 21.4.30: Dual ADC modes.

The data alignment is applied as described in Section : Data register, data alignment and offset (ADC_DR, OFFSETy, OFFSETy_CH, ALIGN))

In MDMA = 11 mode, bits 15:8 contains SLV_ADC_DR[7:0], bits 7:0 contains

MST_ADC_DR[7:0].

21.9 ADC register map

The following table summarizes the ADC registers.

Table 177. ADC global register map

Offset	Register
0x000 - 0x0FC	Master ADC1/ADC3
0x100 - 0x1FC	Slave ADC2/ADC4
0x200 - 0x2FC	Reserved/single ADC5
0x300 - 0x30C	Master and slave ADCs common registers

Table 178. ADC register map and reset values for each ADC (offset

= 0 \times 000

for master ADC, 0x100 for slave ADC)

Offset	Register name reset value	31	30	2328	27	2623	24	23	22	21	20	1.91.8	仍	1.61.5	4	1.3	1211	10	9	∞7	6	5	43	2	1	0
0x00	ADC_ISR	8	o	33	COMP	SON时	S	5	3	a	Proof.	SLet	1.00	COND新时	中华	S	：	HAOOR	Average of the figure 3	AvenAverage	Jun-20	Jour	OverEO O	Europe	dWSO3	人口ＹＯＶ
0x00	Reset value																	0	0	0	0	0	00	0	0	0
0x04	ADC_IER	粉色	8	BUDE	3	3面	新	3	(a)	1.0	REPH	STASTA	8	好y	5	SHIPE	BALL	3.1. JAOON	$\exists$ IECIMV	312QMV	311.0MValsoar	31003r	Over Current CounterEurope	Europe	3IdWSO3	31人QUIV
0x04	Reset value																	0	0	0	00	0	00	0	0	0
0x08	ADC_CR	7VOCV	JIATVOAV	CMdd330N353WACV	a	33	34	：	33	: a	13	813	RECT	33	MA	Suppose	33	y	3	Y	4：	d.LSCY	d1SCVlaviscivi	IVVISAV	SIGCV	AUG
0x08	Reset value	0	010																			0	00	0	0	0
0x0C	ADC_CFGR	190,013	AWD1CH[4:0]			Jun-17	NELOMY	NELOMY	7.5.1 GMV	Jun-20	N30SIGR	DISCNUM [2:0]		NEOSICAuto	人10.1.NV	SQUE	GOWYAO	[O'1]N3.1X3	EXTSEL[4:0]				RES [1:0]	(a)	9.104	NEVWA
0x0C	Reset value	1	0	00	0	00	0	0	0	0	0	00	0	00	0	0	00	0	00000				00		0	0
0x10	ADC_CFGR2	3	8	S3	5181dWS	BullDIYIMS		3	COMP	8	PUL	：粉	PRO	dW009	5	新	ELL	WSAOY	IG	OVSS[3:0]			OVSR [2:0]		195, 193	3SAOY
0x10	Reset value				0	00								0				0	0	000		0	00	0	0	0
0x14	ADC_SMPR1	SN7ddWS		SMP9 [2:0]		SMP8 [2:0]		SMP7 [2:0]			SMP6 [2:0]		SMP5 $[2 : 0]$		SMP4 $[2 : 0]$			SMP3 [2:0]		SMP2 [2:0]		SMP1 $[2 : 0]$		SMP0 [2:0]
0x14	Reset value	0		00	0	00	0	000			000			00	0000			00		00		000		0		0
0x18	ADC_SMPR2			PU		SMP18 [2:0]		SMP17 [2:0]			SMP16 [2:0]		SMP1 15 [2:0]		SMP14 [2:0]			SMP13 [2:0]		SMP12 [2:0]		SMP1 [2:0]		SMP10 [2:0]
0x18	Reset value					00	0	0	0	0	0	00		00	0	0	00	0	0	0	0	0	00	0	0	0
0x1C	Reserved
0x20	ADC_TR1		好好		HT1[11:0]										AWDFILT [2:0]			LT1[11:0]
0x20	Reset value				1	11	1111111							1			0	0	0	0	00	0	00	0	0	0
0x24	ADC_TR2		0	(a)	(a)	5	HT2[[7:0]							8							LT2[7:0]
0x24	Reset value						111111							1							00000000
0x28	ADC_TR3				3		HT3[[7:0]													a	LT3[7:0]
0x28	Reset value		1111111100000000
0x2C	Reserved
0x30	ADC_SQR1				SQ4[4:0]				SQ3[4:0]					SQ2[4:0]				SQ1[4:0]						L[3:0]
0x30	Reset value			0	0	00	0		00000					00	0	0	0	00000					0	0	0	0
0x34	ADC_SQR2				SQ9[4:0]				SQ8[4:0]					SQ7[4:0]				SQ6[4:0]				出	SQ5[4:0]
0x34	Reset value			0	0000				00000					00000				00000					00000
0x38	ADC_SQR3				SQ14[4:0]				SQ13[4:0]					SQ12[4:0]				SQ11[4:0]					SQ10[4:0]
0x38	Reset value			0	0	00	0		0	0	0	00		00	0	0	0	00000					00000
0x3C	ADC_SQR4			福	串										y	a	出	SQ16[4:0]					SQ15[4:0]
0x3C	Reset value																	0	0	0	00		00	0	0	0
0x40	ADC_DR				8									regular RDATA[15:0]
0x40	Reset value													0000000000000000

Table 178. ADC register map and reset values for each ADC (offset

= 0 \times 000

for master ADC, 0x100 for slave ADC) (continued)

Offset	Register name reset value	31	3023	2827	26	25	24	23	22	21	20	1.9	1.8	亿	伯	伯	14	13	12	伯109	87	65432	10
0x44- 0x48	ReservedRes.
0x4C	ADC_JSQR	JSQ4[4:0]			3	JSQ3[4:0]					商品	JSQ2[4:0]						JSQ1[4:0]			[0:1]na1X3r	JEXTSEL [4:0]	JL[1:0]
0x4C	Reset value	00 \| 0 \| 00				00000						0	0	0	0	0		0	0	000	00	00000	00
0x50- 0x5CReservedRes.
0x60	ADC_OFR1	N3~1.13S3.30	OFFSET1 CH[4:0]			NELVS	SODILISHO	Proof.	3	8	股本	8	串串	3	好好	：	8	好	时	OFFSET1[11:0]
0x60	Reset value	0	00			0	0													000	00	00000	00
0x64	ADC_OFR2	N3TZ13SH0	OFFSET2 CH[4:0]			NELVS	SODILESHO	:	(a)	5,679	：	S	0	8	SU	SCO	(a)	S	: '8	OFFSET2[11:0]
0x64	Reset value	0	0000			0	0													000	00	00000	00
0x68	ADC_OFR3	N3" <ISH JO	OFFSET3 CH[4:0]			NELLVS	SODILISHO	3	B	5,133	B	S	BUB	(3,450)	3	SHUM	TALL	SHUM	5,053		OFFSET3[11:0]
0x68	Reset value	0	0\| 0 \| 0 \| 00			0	0													000	00	00000	00
0x6C	ADC_OFR4	N3~t13S3B0	OFFSET4 CH[4:0]			NELVS	SODILESHK	500	as	中国	千港元	S	好	BUS	Let	新鲜	PRO	SHU	BUS	OFFSET4[11:0]
0x6C	Reset value	0	00	00	0	0	0													000	00	00000	00
0x70- 0x7C	ReservedRes.
0x80	ADC_JDR1		0	83	8		8	8	8	郎	a			8	a		JDATA1[15:0]
0x80	Reset value															0	0	0	0	000	00	00000	00
0x84	ADC_JDR2		的	3	3		8	好	5,959	好						JDATA2[15:0]
0x84	Reset value															0	0	0	0	000	00	00000	00
0x88	ADC_JDR3		8	3				3							:	JDATA3[15:0]
0x88	Reset value															0000000000000000
0x8C	ADC_JDR4		郎a	8:												JDATA4[15:0]
0x8C	Reset value															0	0	0	0	000	00	00000	00
0x8C- 0x9C	Reserved	Resi
0xA0	ADC_AWD2CR		a3	a名	a	8	馮	3	8		炒		AWD2CH[18:0]
0xA0	Reset value												000000000000000000
0xA4	ADC_AWD3CR		3a	38	a路31388(a)								AWD3CH[18:0]
0xA4	Reset value												0	0	0	0	0	0	0	000	00	00000	00
0xA8- 0xAC	Reserved		8	36							好	8			33	S		y2		83	8	aga“	好(4)
0xA8- 0xAC	Reserved

Table 178. ADC register map and reset values for each ADC (offset

= 0 \times 000

for master ADC, 0x100 for slave ADC) (continued)

Offset	Register name reset value	30	28	27	25	23	22	21	2023	19	1.8	17	伯	16	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0xB0	ADC_DIFSEL										DIFSEL[18:0]
0xB0	Reset value										0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0xB4	ADC_CALFACT	8			a	8	CALFACT_D[6:0]							3		y	8	a	g	y	y	等	CALFACT_S[6:0]
0xB4	Reset value						0	0	0	0	0	0	0										0	0	0	0	0	0	0
0xC0	ADC_GCOMP	8	34	3		福	3	3	3	S	3	8	y	3	8	GCOMP[13:0]
0xC0	Reset value															0	0	0	0	0	0	0	0	0	0	0	0	0	0

Table 179. ADC register map and reset values (master and slave ADC

common registers) offset

= 0 \times 300

Offset	Register name reset value	31	30	23	2Q3	27	26	23	24	23	22	21	2023	1.	1.	17	伯	1.5	14	13	12	11	10	9	8	7	6	5	4	3	21	0
0x00	ADCx_CSR	SCON	(1)	1,000	时	Proof.	ats that	atsTeamV	^TSTZCIMV	msTiamy	ats *soar	ats oder	ats and	ATSTSO3	ATSTOOE	/) $^{-}$ dWSO3	ATSTACHIV	分	SCON	COND	STROP	E	LSW HAODR	ISW EGMV	ISW ZAMY	ISW LAMV	isw soar	iswhoder	ISW YAO	.LSW SO3	LSW 0031SWTdWSO3	ISW AGY
	ADCx_CSR						slave ADC2																	master ADC1
	Reset value						0	0	0	0	0	0	0	0	0	0	0						0	0	0	0	0	0	0	0	00	0
0x04	ReservedRes.
0x08	ADCx_CCR	S	S	For	B	HK$’000	BUR	BUG	73S1V9A	73S3SN3SA	NBJ38A	PRESC[3:0]				[0:1]300WX0		[0:1] $\forall$ waw		5.10.7.0	2023年	DELAY[3:0]				3	好	8	DUAL[4:0]
0x08	Reset value								0	0	0	0	0	0	0	0	0	0	0	0		0	0	0	0				0	0	00	0
0x0C	ADCX CDR	RDATA SLV[15:0]																RDATA MST[15:0]
0x0C	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	00	0

Refer to Section 2.2 on page 81 for the register boundary addresses.

22 Digital-to-analog converter (DAC)

22.1 Introduction

The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data can be left- or right-aligned. The DAC features up to two output channels, each with its own converter. In dual DAC channel mode, conversions can be done independently or simultaneously when both channels are grouped together for synchronous update operations. An input reference pin,

V_{REF +}

(shared with others analog peripherals) is available for better resolution. An internal reference can also be set on the same input. Refer to voltage reference buffer (VREFBUF) section.

The DACx_OUTy pin can be used as general purpose input/output (GPIO) when the DAC output is disconnected from output pad and connected to on chip peripheral. The DAC output buffer can be optionally enabled to obtain a high drive output current. An individual calibration can be applied on each DAC output channel. The DAC output channels support a low power mode, the Sample and hold mode.

22.2 DAC main features

The DAC main features are the following (see Figure 156: Dual-channel DAC block diagram)

Up to four DAC interfaces, maximum two output channels each

Left or right data alignment in 12-bit mode

Synchronized update capability

Noise-wave and Triangular-wave generation

Sawtooth wave generation

Dual DAC channel for independent or simultaneous conversions

DMA capability for each channel including DMA underrun error detection

Double data DMA capability to reduce the bus activity

External triggers for conversion

DAC output channel buffered/unbuffered modes

Buffer offset calibration

Each DAC output can be disconnected from the DACx_OUTy output pin

DAC output connection to on-chip peripherals

Sample and hold mode for low power operation in Stop mode

Input voltage reference from $V_{REF +}$ pin or internal VREFBUF reference

Figure 156 shows the block diagram of a DAC channel and Table 181 gives the pin description.

MODEx bits in the DAC_MCR control the output mode and allow switching between the Normal mode in buffer/unbuffered configuration and the Sample and hold mode.

Refer to Section 22.3: DAC implementation for channel2 availability.

DAC channel2 is available only on DAC1, DAC3 and DAC4.

22.4.2 DAC pins and internal signals

The DAC includes:

Up to two output channels

The DACx_OUTy can be disconnected from the output pin and used as an ordinary GPIO

The dac_outx can use an internal pin connection to on-chip peripherals such as comparator, operational amplifier and ADC (if available).

DAC output channel buffered or non buffered

Sample and hold block and registers operational in Stop mode, using the LSI/LSE clock source (dac_hold_ck) for static conversion.

The DAC includes up to two separate output channels. Each output channel can be connected to on-chip peripherals such as comparator, operational amplifier and ADC (if available). In this case, the DAC output channel can be disconnected from the DACx_OUTy output pin and the corresponding GPIO can be used for another purpose.

The DAC output can be buffered or not. The Sample and hold block and its associated registers can run in Stop mode using the LSI/LSE clock source (dac_hold_ck).

Table 181. DAC input/output pins

Pin name	Signal type	Remarks
VREF+	Input, analog reference positive	The higher/positive reference voltage for the DAC, $V_{REF +} \leq V_{DDAmax} (refer to datasheet)$
VDDA	Input, analog supply	Analog power supply
VSSA	Input, analog supply ground	Ground for analog power supply
DACx_OUTy	Analog output signal	DACx channely analog output

Table 182. DAC input/output signals

Internal signal name	Signal type	Description
dac_ch1_dma	Bidirectional	DAC channel1 DMA request/acknowledge
dac_ch2_dma	Bidirectional	DAC channel2 DMA request/acknowledge
dac_ch1_trgx (x = 1 to 15)	Inputs	DAC channel1 trigger inputs
dac_ch2_trgx (x = 1 to 15)	Inputs	DAC channel2 trigger inputs
dac_ch1_inc_trgx (x = 1 to 15)	Inputs	DAC channel1 sawtooth increment trigger inputs
dac_chn2_inc_trgx (x = 1 to 15)	Inputs	DAC channel1 sawtooth increment trigger inputs
dac_unr_it	Output	DAC underrun interrupt
dac_hclk	Input	DAC peripheral clock
dac_hold_ck	Input	DAC low-power clock used in Sample and hold mode

Table 182. DAC input/output signals (continued)

Internal signal name	Signal type	Description
dac_out1	Analog output	DAC channel1 output for on-chip peripherals
dac_out2	Analog output	DAC channel2 output for on-chip peripherals

Table 183. DAC1 interconnection

Signal name	Source	Source type
dac_hold_ck	ck_lsi or ck_lse (selected in the RCC)	LSI or LSE clock selected in the RCC
dac_chx_trg1 (x = 1, 2)	TIM8_TRGO	Internal signal from on-chip timers
dac_chx_trg2 (x = 1, 2)	TIM7_TRGO	Internal signal from on-chip timers
dac_chx_trg3 (x = 1, 2)	TIM15_TRGO	Internal signal from on-chip timers
dac_chx_trg4 (x = 1, 2)	TIM2_TRGO	Internal signal from on-chip timers
dac_chx_trg5 (x = 1, 2)	TIM4_TRGO	Internal signal from on-chip timers
dac_chx_trg6 (x = 1, 2)	EXTI9	External pin
dac_chx_trg7 (x = 1, 2)	TIM6_TRGO	Internal signal from on-chip timers
dac_chx_trg8 (x = 1, 2)	TIM3_TRGO	Internal signal from on-chip timers
dac_chx_trg9 (x = 1, 2)	hrtim_dac_reset_trg1	Internal signal from on-chip timers
dac_chx_trg10 (x = 1, 2)	hrtim_dac_reset_trg2	Internal signal from on-chip timers
dac_chx_trg11 (x = 1, 2)	hrtim_dac_reset_trg3	Internal signal from on-chip timers
dac_chx_trg12 (x = 1, 2)	hrtim_dac_reset_trg4	Internal signal from on-chip timers
dac_chx_trg13 (x = 1, 2)	hrtim_dac_reset_trg5	Internal signal from on-chip timers
dac_chx_trg14 (x = 1, 2)	hrtim_dac_reset_trg6	Internal signal from on-chip timers
dac_chx_trg15 (x = 1, 2)	hrtim_dac_trg1	Internal signal from on-chip timers
dac_inc_chx_trg1 (x = 1, 2)	TIM8_TRGO	Internal signal from on-chip timers
dac_inc_chx_trg2 (x = 1, 2)	TIM7_TRGO	Internal signal from on-chip timers
dac_inc_chx_trg3 (x = 1, 2)	TIM15_TRGO	Internal signal from on-chip timers
dac_inc_chx_trg4 (x = 1, 2)	TIM2_TRGO	Internal signal from on-chip timers
dac_inc_chx_trg5 (x = 1, 2)	TIM4_TRGO	Internal signal from on-chip timers
dac_inc_chx_trg6 (x = 1, 2)	EXTI10	External pin
dac_inc_chx_trg7 (x = 1, 2)	TIM6_TRGO	Internal signal from on-chip timers
dac_inc_chx_trg8 (x = 1, 2)	TIM3_TRGO	Internal signal from on-chip timers
dac_inc_chx_trg9 (x = 1, 2)	hrtim_dac_step_trg1	Internal signal from on-chip timers
dac_inc_chx_trg10 (x = 1, 2)	hrtim_dac_step_trg2	Internal signal from on-chip timers
dac_inc_chx_trg11 (x = 1, 2)	hrtim_dac_step_trg3	Internal signal from on-chip timers
dac_inc_chx_trg12 (x = 1, 2)	hrtim_dac_step_trg4	Internal signal from on-chip timers

Table 183. DAC1 interconnection (continued)

Signal name	Source	Source type
dac_inc_chx_trg13 (x = 1, 2)	hrtim_dac_step_trg5	Internal signal from on-chip timers
dac_inc_chx_trg14 (x = 1, 2)	hrtim_dac_step_trg6	Internal signal from on-chip timers

Table 184. DAC2 interconnection

Signal name	Source	Source type
dac_hold_ck	ck_lsi or ck_lse (selected in the RCC)	LSI or LSE clock selected in the RCC
dac_ch1_trg1	TIM8_TRGO	Internal signal from on-chip timers
dac_ch1_trg2	TIM7_TRGO	Internal signal from on-chip timers
dac_ch1_trg3	TIM15_TRGO	Internal signal from on-chip timers
dac_ch1_trg4	TIM2_TRGO	Internal signal from on-chip timers
dac_ch1_trg5	TIM4_TRGO	Internal signal from on-chip timers
dac_ch1_trg6	EXTI9	External pin
dac_ch1_trg7	TIM6_TRGO	Internal signal from on-chip timers
dac_ch1_trg8	TIM3_TRGO	Internal signal from on-chip timers
dac_ch1_trg9	hrtim_dac_reset_trg1	Internal signal from on-chip timers
dac_ch1_trg10	hrtim_dac_reset_trg2	Internal signal from on-chip timers
dac_ch1_trg11	hrtim_dac_reset_trg3	Internal signal from on-chip timers
dac_ch1_trg12	hrtim_dac_reset_trg4	Internal signal from on-chip timers
dac_ch1_trg13	hrtim_dac_reset_trg5	Internal signal from on-chip timers
dac_ch1_trg14	hrtim_dac_reset_trg6	Internal signal from on-chip timers
dac_ch1_trg15	hrtim_dac_trg2	Internal signal from on-chip timers
dac_inc_ch1_trg1	TIM8_TRGO	Internal signal from on-chip timers
dac_inc_ch1_trg2	TIM7_TRGO	Internal signal from on-chip timers
dac_inc_ch1_trg3	TIM15_TRGO	Internal signal from on-chip timers
dac_inc_ch1_trg4	TIM2_TRGO	Internal signal from on-chip timers
dac_inc_ch1_trg5	TIM4_TRGO	Internal signal from on-chip timers
dac_inc_ch1_trg6	EXTI10	External pin
dac_inc_ch1_trg7	TIM6_TRGO	Internal signal from on-chip timers
dac_inc_ch1_trg8	TIM3_TRGO	Internal signal from on-chip timers
dac_inc_ch1_trg9	hrtim_dac_step_trg1	Internal signal from on-chip timers
dac_inc_ch1_trg10	hrtim_dac_step_trg2	Internal signal from on-chip timers
dac_inc_ch1_trg11	hrtim_dac_step_trg3	Internal signal from on-chip timers
dac_inc_ch1_trg12	hrtim_dac_step_trg4	Internal signal from on-chip timers

Table 184. DAC2 interconnection (continued)

Signal name	Source	Source type
dac_inc_ch1_trg13	hrtim_dac_step_trg5	Internal signal from on-chip timers
dac_inc_ch1_trg14	hrtim_dac_step_trg6	Internal signal from on-chip timers

Table 185. DAC3 interconnection

Signal name	Source	Source type
dac_hold_ck	ck_lsi or ck_lse (selected in the RCC)	LSI or LSE clock selected in the RCC
dac_chx_trg1 (x = 1, 2)	TIM1_TRGO	Internal signal from on-chip timers
dac_chx_trg2 (x = 1, 2)	TIM7_TRGO	Internal signal from on-chip timers
dac_chx_trg3 (x = 1, 2)	TIM15_TRGO	Internal signal from on-chip timers
dac_chx_trg4 (x = 1, 2)	TIM2_TRGO	Internal signal from on-chip timers
dac_chx_trg5 (x = 1, 2)	TIM4_TRGO	Internal signal from on-chip timers
dac_chx_trg6 (x = 1, 2)	EXTI9	External pin
dac_chx_trg7 (x = 1, 2)	TIM6_TRGO	Internal signal from on-chip timers
dac_chx_trg8 (x = 1, 2)	TIM3_TRGO	Internal signal from on-chip timers
dac_chx_trg9 (x = 1, 2)	hrtim_dac_reset_trg1	Internal signal from on-chip timers
dac_chx_trg10 (x = 1, 2)	hrtim_dac_reset_trg2	Internal signal from on-chip timers
dac_chx_trg11 (x = 1, 2)	hrtim_dac_reset_trg3	Internal signal from on-chip timers
dac_chx_trg12 (x = 1, 2)	hrtim_dac_reset_trg4	Internal signal from on-chip timers
dac_chx_trg13 (x = 1, 2)	hrtim_dac_reset_trg5	Internal signal from on-chip timers
dac_chx_trg14 (x = 1, 2)	hrtim_dac_reset_trg6	Internal signal from on-chip timers
dac_chx_trg15 (x = 1, 2)	hrtim_dac_trg3	Internal signal from on-chip timers
dac_inc_chx_trg1 (x = 1, 2)	TIM1_TRGO	Internal signal from on-chip timers
dac_inc_chx_trg2 (x = 1, 2)	TIM7_TRGO	Internal signal from on-chip timers

Table 185. DAC3 interconnection (continued)

Signal name	Source	Source type
dac_inc_chx_trg3 (x = 1, 2)	TIM15_TRGO	Internal signal from on-chip timers
dac_inc_chx_trg4 (x = 1, 2)	TIM2_TRGO	Internal signal from on-chip timers
dac_inc_chx_trg5 (x = 1, 2)	TIM4_TRGO	Internal signal from on-chip timers
dac_inc_chx_trg6 (x = 1, 2)	EXTI10	External pin
dac_inc_chx_trg7 (x = 1, 2)	TIM6_TRGO	Internal signal from on-chip timers
dac_inc_chx_trg8 (x = 1, 2)	TIM3_TRGO	Internal signal from on-chip timers
dac_inc_chx_trg9 (x = 1, 2)	hrtim_dac_step_trg1	Internal signal from on-chip timers
dac_inc_chx_trg10 (x = 1, 2)	hrtim_dac_step_trg2	Internal signal from on-chip timers
dac_inc_chx_trg11 (x = 1, 2)	hrtim_dac_step_trg3	Internal signal from on-chip timers
dac_inc_chx_trg12 (x = 1, 2)	hrtim_dac_step_trg4	Internal signal from on-chip timers
dac_inc_chx_trg13 (x = 1, 2)	hrtim_dac_step_trg5	Internal signal from on-chip timers
dac_inc_chx_trg14 (x = 1, 2)	hrtim_dac_step_trg6	Internal signal from on-chip timers

Table 186. DAC4 interconnection

Signal name	Source	Source type
dac_hold_ck	ck_lsi or ck_lse (selected in RCC)	LSI or LSE clock selected in the RCC
dac_chx_trg1 (x = 1, 2)	TIM8_TRGO	Internal signal from on-chip timers
dac_chx_trg2 (x = 1, 2)	TIM7_TRGO	Internal signal from on-chip timers
dac_chx_trg3 (x = 1, 2)	TIM15_TRGO	Internal signal from on-chip timers
dac_chx_trg4 (x = 1, 2)	TIM2_TRGO	Internal signal from on-chip timers
dac_chx_trg5 (x = 1, 2)	TIM4_TRGO	Internal signal from on-chip timers
dac_chx_trg6 (x = 1, 2)	EXTI9	External pin
dac_chx_trg7 (x = 1, 2)	TIM6_TRGO	Internal signal from on-chip timers

Table 186. DAC4 interconnection (continued)

Signal name	Source	Source type
dac_chx_trg8 (x = 1, 2)	TIM3_TRGO	Internal signal from on-chip timers
dac_chx_trg9 (x = 1, 2)	hrtim_dac_reset_trg1	Internal signal from on-chip timers
dac_chx_trg10 (x = 1, 2)	hrtim_dac_reset_trg2	Internal signal from on-chip timers
dac_chx_trg11 (x = 1, 2)	hrtim_dac_reset_trg3	Internal signal from on-chip timers
dac_chx_trg12 (x = 1, 2)	hrtim_dac_reset_trg4	Internal signal from on-chip timers
dac_chx_trg13 (x = 1, 2)	hrtim_dac_reset_trg5	Internal signal from on-chip timers
dac_chx_trg14 (x = 1, 2)	hrtim_dac_reset_trg6	Internal signal from on-chip timers
dac_chx_trg15 (x = 1, 2)	hrtim_dac_trg1	Internal signal from on-chip timers
dac_inc_chx_trg1 (x = 1, 2)	TIM8_TRGO	Internal signal from on-chip timers
dac_inc_chx_trg2 (x = 1, 2)	TIM7_TRGO	Internal signal from on-chip timers
dac_inc_chx_trg3 (x = 1, 2)	TIM15_TRGO	Internal signal from on-chip timers
dac_inc_chx_trg4 (x = 1, 2)	TIM2_TRGO	Internal signal from on-chip timers
dac_inc_chx_trg5 (x = 1, 2)	TIM4_TRGO	Internal signal from on-chip timers
dac_inc_chx_trg6 (x = 1, 2)	EXTI10	External pin
dac_inc_chx_trg7 (x = 1, 2)	TIM6_TRGO	Internal signal from on-chip timers
dac_inc_chx_trg8 (x = 1, 2)	TIM3_TRGO	Internal signal from on-chip timers
dac_inc_chx_trg9 (x = 1, 2)	hrtim_dac_step_trg1	Internal signal from on-chip timers
dac_inc_chx_trg10 (x = 1, 2)	hrtim_dac_step_trg2	Internal signal from on-chip timers
dac_inc_chx_trg11 (x = 1, 2)	hrtim_dac_step_trg3	Internal signal from on-chip timers
dac_inc_chx_trg12 (x = 1, 2)	hrtim_dac_step_trg4	Internal signal from on-chip timers

Table 186. DAC4 interconnection (continued)

Signal name	Source	Source type
dac_inc_chx_trg13 (x = 1, 2)	hrtim_dac_step_trg5	Internal signal from on-chip timers
dac_inc_chx_trg14 (x = 1, 2)	hrtim_dac_step_trg6	Internal signal from on-chip timers

22.4.3 DAC channel enable

Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR register. The DAC channel is then enabled after a

t_{WAKEUP}

startup time.

DACxRDY bit is set in the DAC_SR register when the DAC interface is ready to accept data. Writing new data or asserting the trigger is not allowed when ENx bit is set while DACxRDY signal is reset.

Note: The ENx bit enables the analog DAC channelx only. The DAC channelx digital interface is enabled even if the ENx bit is reset.

22.4.4 DAC data format

Depending on the selected configuration mode, the data have to be written into the specified register as described below:

Single DAC channel

There are three possibilities:

8-bit right alignment: the software has to load data into the DAC_DHR8Rx[7:0] bits (stored into the DHRx[11:4] bits)

12-bit left alignment: the software has to load data into the DAC_DHR12Lx [15:4] bits (stored into the DHRx[11:0] bits)

12-bit right alignment: the software has to load data into the DAC_DHR12Rx [11:0] bits (stored into the DHRx[11:0] bits)

Depending on the loaded DAC_DHRyyyx register, the data written by the user is shifted and stored into the corresponding DHRx (data holding registerx, which are internal non-memory-mapped registers). The DHRx register is then loaded into the DORx register either automatically, by software trigger or by an external event trigger.

Figure 157. Data registers in single DAC channel mode

Dual DAC channels (when available)

There are three possibilities:

8-bit right alignment: data for DAC channel1 to be loaded into the DAC_DHR8RD [7:0] bits (stored into the DHR1[11:4] bits) and data for DAC channel2 to be loaded into the DAC_DHR8RD [15:8] bits (stored into the DHR2[11:4] bits)

12-bit left alignment: data for DAC channel 1 to be loaded into the DAC_DHR12LD [15:4] bits (stored into the DHR1[11:0] bits) and data for DAC channel2 to be loaded into the DAC_DHR12LD [31:20] bits (stored into the DHR2[11:0] bits)

12-bit right alignment: data for DAC channel1 to be loaded into the DAC_DHR12RD [11:0] bits (stored into the DHR1[11:0] bits) and data for DAC channel2 to be loaded into the DAC_DHR12RD [27:16] bits (stored into the DHR2[11:0] bits)

Depending on the loaded DAC_DHRyyyD register, the data written by the user is shifted and stored into DHR1 and DHR2 (data holding registers, which are internal non-memory-mapped registers). The DHR1 and DHR2 registers are then loaded into the DAC_DOR1 and DOR2 registers, respectively, either automatically, by software trigger or by an external event trigger.

Figure 158. Data registers in dual DAC channel mode

Signed/unsigned data

DAC input data are unsigned: 0x000 corresponds to the minimum value and 0xFFF to the maximum value for 12-bit mode.

The DAC can also handle signed input data in 2's complement format. This is done by setting SINFORMATx bit in the DAC_MCR register.

When SINFORMATx bit is set, the MSB bit of the data written to DHRx registers is inverted when it is copied to the DAC_DORx register, and the DAC interface can accept signed data (Q1.15, Q1.11 or Q1.7 format). DAC_DHR12Lx register can be used to store 16-bit signed data in the data holding registers. The 12 MSBs of 16-bit data are used for the DAC output data and the MSB bit is inverted. The four LSBs are simply ignored.

Table 187. Data format (case of 12-bit data)

SINFORMATx bit	DATA written to DHRx register	DATA transfered to DORx register
0	0x000	0x000
0	0xFFF	0xFFF
1	0x7FF	0xFFF

Table 187. Data format (case of 12-bit data) (continued)

SINFORMATx bit	DATA written to DHRx register	DATA transfered to DORx register
1	0x000	0x800
1	0xFFF	0x7FF
1	0x800	0x000

22.4.5 DAC conversion

The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must be performed by loading the DAC_DHRx register (write operation to DAC_DHR8Rx, DAC_DHR12Lx, DAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12RD or DAC_DHR12LD).

Data stored in the DAC_DHRx register are automatically transferred to the DAC_DORx register after one dac_hclk clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR register is reset). However, when a hardware trigger is selected (TENx bit in DAC_CR register is set) and a trigger occurs, the transfer is performed three dac_hclk clock cycles after the trigger signal.

When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage becomes available after a time

t_{SETTLING}

that depends on the power supply voltage and the analog output load.

HFSEL bits of DAC_MCR must be set when dac_hclk clock speed is faster than 80 MHz. It adds an extra delay to the transfer from DAC_DHRx register to DAC_DORx register.

Refer to Table HFSEL description below for the limitation of the DAC_DORx update rate depending on HFSEL bits and dac_hclk clock frequency.

If the data is updated or a software/hardware trigger event occurs during the non-allowed period, the peripheral behavior is unpredictable.

The above timing is only related to the limitation of the DAC interface. Refer also to the

t_{SETTLING}

parameter value in the product datasheet.

Table 188. HFSEL description

HFSEL[1:0]	AHB frequency	Function
00	< 80 MHz	DAC_DOR update rate up to 3 AHB clock cycles
01	2.80 MHz(1)	DAC_DOR update rate up to 5 AHB clock cycles
10	≥ 160 MHz	DAC_DOR update rate up to 7 AHB clock cycles
11	Reserved	-

Refer to the device datasheet for the value of the maximum AHB frequency.

Figure 159. Timing diagram for conversion with trigger disabled TEN

= 0

22.4.6 DAC output voltage

Digital inputs are converted to output voltages on a linear conversion between 0 and

V_{REF +}

. The analog output voltages on each DAC channel pin are determined by the following equation:

DACoutput

= V_{REF} \times \frac{DOR}{4096}

22.4.7 DAC trigger selection

If the TENx control bit is set, the conversion can then be triggered by an external event (timer counter, external interrupt line). The TSELx[3:0] control bits determine which out of 16 possible events triggers the conversion as shown in TSELx[3:0] bits of the DAC_CR register. These events can be either the software trigger or hardware triggers. Refer to the interconnection table in Section 22.4.2: DAC pins and internal signals.

Each time a DAC interface detects a rising edge on the selected trigger source (refer to the table below), the last data stored into the DAC_DHRx register are transferred into the DAC_DORx register. The DAC_DORx register is updated three dac_hclk cycles after the trigger occurs.

If the software trigger is selected, the conversion starts once the SWTRIG bit is set. SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the DAC_DHRx register contents.

The reset trigger selection and the increment trigger selection of the sawtooth generation are performed through STRSTTRIGSELx and STINCTRIGSELx control bits, respectively. STRSTTRIGSELx mapping is similar to TSELx. Refer to the Section 22.4.2: DAC pins and internal signals for TSELx, STRSTTRIGSELx, and STINCTRIGSELx mappings.

Note: TSELx[3:0] bit cannot be changed when the ENx bit is set.

When software trigger is selected, the transfer from the DAC_DHRx register to the DAC_DORx register takes only one dac_hclk clock cycle.

22.4.8 DMA requests

Each DAC channel has a DMA capability. Two DMA channels are used to service DAC channel DMA requests.

When an external trigger (but not a software trigger) occurs while the DMAENx bit is set, the value of the DAC_DHRx register is transferred into the DAC_DORx register when the transfer is complete, and a DMA request is generated.

In dual mode, if both DMAENx bits are set, two DMA requests are generated. If only one DMA request is needed, only the corresponding DMAENx bit must be set. In this way, the application can manage both DAC channels in dual mode by using one DMA request and a unique DMA channel.

As DAC_DHRx to DAC_DORx data transfer occurred before the DMA request, the very first data has to be written to the DAC_DHRx before the first trigger event occurs.

DMA underrun

The DAC DMA request is not queued so that if a second external trigger arrives before the acknowledgment for the first external trigger is received (first request), then no new request is issued and the DMA channelx underrun flag DMAUDRx in the DAC_SR register is set, reporting the error condition. The DAC channelx continues to convert old data.

The software must clear the DMAUDRx flag by writing 1, clear the DMAEN bit of the used DMA stream and re-initialize both DMA and DAC channelx to restart the transfer correctly. The software must modify the DAC trigger conversion frequency or lighten the DMA workload to avoid a new DMA underrun. Finally, the DAC conversion can be resumed by enabling both DMA data transfer and conversion trigger.

For each DAC channelx, an interrupt is also generated if its corresponding DMAUDRIEx bit in the DAC_CR register is enabled.

DMA Double data mode

When the DMA controller is used in Normal mode, only 12-bit (or 8-bit) data are transferred by a DMA request. As the AHB width is 32 bits, two 12-bit data may be transferred simultaneously. To use this mode, set the DMADOUBLEx bit of DAC_MCR register.

A DAC DMA request is generated every two external triggers (except for software triggers) when the DMAENx bit is set:

When the first trigger is detected, the value of the DAC_DHRx and DAC_DHRBx registers are transferred into the DAC_DORx and DAC_DORBx registers. The actual DAC data is loaded into the DAC_DORx register. A DMA request is then generated. The DMA writes the new data to the DAC_DHRx and DAC_DHRBx data registers.

When the next trigger is detected, the actual DAC data is loaded into the DAC_DHRBx register. This second trigger does not generate any DMA request. The DORSTATx bit indicates which DOR data is actually loaded into the analog DAC input.

DMA underrun function is also supported in DMA Double data mode.

In DMA Double mode, DMA requests can only handle one DAC channel. To use two channel outputs in DMA Double mode, each DMA channel has to be configured separately.

The following conditions must be met to change from Double data to single data mode or vice versa:

The DAC must be disabled.

DMAEN bit must be cleared (ENx $= 0$ and DMAEN $= 0$ ).

22.4.9 Noise generation

In order to generate a variable-amplitude pseudonoise, an LFSR (linear feedback shift register) is available. DAC noise generation is selected by setting WAVEx[1:0] to 01 . The preloaded value in LFSR is 0xAAA. This register is updated three dac_hclk clock cycles after each trigger event, following a specific calculation algorithm.

Figure 160. DAC LFSR register calculation algorithm

The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this value is then transferred into the DAC_DORx register.

If LFSR is

0 \times 0000

,a ’1 is injected into it (antilock-up mechanism).

It is possible to reset LFSR wave generation by resetting the WAVEx[1:0] bits.

Figure 161. DAC conversion (SW trigger enabled) with LFSR wave generation

Note: The DAC trigger must be enabled for noise generation by setting the TENx bit in the

DAC_CR register.

22.4.10 Triangle-wave generation

It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal. DAC triangle-wave generation is selected by setting WAVEx[1:0] to 10". The amplitude is configured through the MAMPx[3:0] bits in the DAC_CR register. An internal triangle counter is incremented three dac_hclk clock cycles after each trigger event. The value of this counter is then added to the DAC_DHRx register without overflow and the sum is transferred into the DAC_DORx register. The triangle counter is incremented as long as it is less than the maximum amplitude defined by the MAMPx[3:0] bits. Once the configured amplitude is reached, the counter is decremented down to 0 , then incremented again and so on.

It is possible to reset triangle wave generation by resetting the WAVEx[1:0] bits.

Figure 162. DAC triangle wave generation

Figure 163. DAC conversion (SW trigger enabled) with triangle wave generation

Note: The DAC trigger must be enabled for triangle wave generation by setting the TENx bit in the DAC_CR register.

The MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot be changed.

22.4.11 DAC sawtooth wave generation

The DAC can generate a sawtooth waveform. Specific register settings for the initial value, increment value and direction control are required:

DAC sawtooth wave generation is selected by setting WAVEx[1:0] to 11 in the DAC_CR register.

The sawtooth counter initial value (reset value) is configured through STRSTDATAx[11:0] bits in the DAC_STRx register.

The increment value is defined by the STINCDATAx[15:0] bits in the DAC_STRx register.

The sawtooth direction is defined by STDIRx bit in the DAC_STRx register.

The sawtooth counter starts from STRSTDATAx[11:0] (bits 12 to 15 are set to 0000), each increment trigger then increments (or decrements) STINCDATAx[15:0] value.

The DAC output is used from 12 MSB of those counter value. When the counter reaches 0x0000 or 0xFFFF, the value is saturated. The sawtooth reset trigger signal initializes the counter value to the STRSTDATAx[11:0] (bits 12 to 15 are set to 0000) value.

The increment trigger and reset trigger must be selected through the STINCTRIGSELx[3:0] and the STRSTTRIGSELx[3:0] bits. The STRSTTRIG signal has higher priority than STINCTRIG. Thetrigger signal cannot be faster than the DAC_DORx update rate defined in Table HFSEL description. If STINCTRIG is asserted faster than the allowed data update rate, the STINCTRIG trigger is ignored. If the STRSTTRIG signal is applied after the STINCTRIG and before DAC_DORx update rate constraints, STRSTTRIG is put on hold. Then, immediately after the data increment, the reset trigger is applied.

Figure 164. DAC sawtooth wave generation (STDIRx = 0)

Figure 165. DAC sawtooth wave generation (STDIRx = 1)

Figure 166. DAC sawtooth STINCTRIG and STRSTTRIG priority (STDIR = 0)

MSv46132V1

22.4.12 DAC channel modes

Each DAC channel can be configured in Normal mode or Sample and hold mode. The output buffer can be enabled to obtain a high drive capability. Before enabling output buffer, the voltage offset needs to be calibrated. This calibration is performed at the factory (loaded after reset) and can be adjusted by software during application operation.

Normal mode

In Normal mode, there are four combinations, by changing the buffer state and by changing the DACx_OUTy pin interconnections.

To enable the output buffer, the MODEx[2:0] bits in DAC_MCR register must be:

000: DAC is connected to the external pin

001: DAC is connected to external pin and to on-chip peripherals

To disable the output buffer, the MODEx[2:0] bits in DAC_MCR register must be:

010: DAC is connected to the external pin

011: DAC is connected to on-chip peripherals

Sample and hold mode

In Sample and hold mode, the DAC core converts data on a triggered conversion, and then holds the converted voltage on a capacitor. When not converting, the DAC cores and buffer are completely turned off between samples and the DAC output is tri-stated, therefore reducing the overall power consumption. A stabilization period, which value depends on the buffer state, is required before each new conversion.

In this mode, the DAC core and all corresponding logic and registers are driven by the LSI/LSE low-speed clock (dac_hold_ck) in addition to the dac_hclk clock, allowing using the DAC channels in deep low power modes such as Stop mode.

The LSI/LSE low-speed clock (dac_hold_ck) must not be stopped when the Sample and hold mode is enabled.

The sample/hold mode operations can be divided into 3 phases:

Sample phase: the sample/hold element is charged to the desired voltage. The charging time depends on capacitor value (internal or external, selected by the user). The sampling time is configured with the TSAMPLEx[9:0] bits in DAC_SHSRx register. During the write of the TSAMPLEx[9:0] bits, the BWSTx bit in DAC_SR register is set to 1 to synchronize between both clocks domains (AHB and low speed clock) and allowing the software to change the value of sample phase during the DAC channel operation

Hold phase: the DAC output channel is tri-stated, the DAC core and the buffer are turned off, to reduce the current consumption. The hold time is configured with the THOLDx[9:0] bits in DAC_SHHR register

Refresh phase: the refresh time is configured with the TREFRESHx[7:0] bits in DAC_SHRR register

The timings for the three phases above are in units of LSI/LSE clock periods. As an example,to configure a sample time of

350 μ s

,a hold time of

2 ms

and a refresh time of

100 μ s

assuming LSI/LSE

\sim 32 KHz

is selected:

12 cycles are required for sample phase: TSAMPLEx[9:0] = 11,

62 cycles are required for hold phase: THOLDx[9:0] = 62,

and 4 cycles are required for refresh period: TREFRESHx[7:0] = 4.

In this example, the power consumption is reduced by almost a factor of 15 versus Normal modes.

The formulas to compute the right sample and refresh timings are described in the table below, the Hold time depends on the leakage current.

Table 189. Sample and refresh timings

Buffer State	${t_{SAMP}}^{(1) (2)}$	$t_{{REFRESH}^{(2) (3)}}$
Enable	$7 μ s + (10^{} R_{BON}^{} C_{SH})$	$7 μ s + {(R_{BON}^{} C_{SH})}^{} \ln (2^{*} N_{LSB})$
Disable	$3 μ s + (10^{} R_{BOFF}^{} C_{SH})$	$3 μ s + {({R_{BOFF}}^{} C_{SH})}^{} \ln (2^{*} N_{LSB})$

In the above formula the settling to the desired code value with $1 / 2 LSB$ or accuracy requires 10 constant time for 12 bits resolution. For $8$ bits resolution,the settling time is 7 constant time.

$C_{SH}$ is the capacitor in Sample and hold mode.

The tolerated voltage drop during the hold phase "Vd" is represented by the number of LSBs after the capacitor discharging with the output leakage current. The settling back to the desired value with $1 / 2$ LSB error accuracy requires $\ln (2^{*} Nlsb)$ constant time of the DAC.

Example of the sample and refresh time calculation with output buffer on

The values used in the example below are provided as indication only. Refer to the product datasheet for product data.

C_{SH} = 100 nF

V_{DDA} = 3.0 V

Sampling phase:

t_{SAMP} = 7 μ s + (10 * 2000 * 100 * 10^{- 9}) = 2.007 ms

(where

R_{BON} = 2 k Ω

)

Refresh phase:

t_{REFRESH} = 7 μ s + (2000 * 100 * 10^{- 9}) * \ln (2^{*} 10) = 606.1 μ s

(where

N_{LSB} = 10

(10 LSB drop during the hold phase)

Hold phase:

D_{v} = i_{leak} * t_{hold} / C_{SH} = 0.0073 V (10 LSB of 12 bit at 3 V)

i_{leak} = 150 nA

(worst case on the IO leakage on all the temperature range)

t_{hold} = 0.0073 * 100 * 10^{- 9} / (150 * 10^{- 9}) = 4.867 ms

Figure 167. DAC Sample and hold mode phase diagram

Like in Normal mode, the Sample and hold mode has different configurations.

To enable the output buffer, MODEx[2:0] bits in DAC_MCR register must be set to:

100: DAC is connected to the external pin

101: DAC is connected to external pin and to on chip peripherals

To disabled the output buffer, MODEx[2:0] bits in DAC_MCR register must be set to:

110: DAC is connected to external pin and to on chip peripherals

111: DAC is connected to on chip peripherals

When

MODEx [2 : 0]

bits are equal to 111,an internal capacitor,

C_{Lint}

holds the voltage output of the DAC core and then drive it to on-chip peripherals.

All Sample and hold phases are interruptible, and any change in DAC_DHRx immediately triggers a new sample phase.

Note: The sawtooth wave generation is not supported in Sample and hold mode operation.

Table 190. Channel output modes summary

MODEX[2:0]			Mode	Buffer	Output connections
0	0	0	Normal mode	Enabled	Connected to external pin
0	0	1		Enabled	Connected to external pin and to on chip-peripherals (such as comparators)
0	1	0		Disabled	Connected to external pin
0	1	1		Disabled	Connected to on chip peripherals (such as comparators
1	0	0	Sample and hold mode	Enabled	Connected to external pin
1	0	1		Enabled	Connected to external pin and to on chip peripherals (such as comparators)
1	1	0		Disabled	Connected to external pin and to on chip peripherals (such as comparators)
1	1	1		Disabled	Connected to on chip peripherals (such as comparators)

22.4.13 DAC channel buffer calibration

The transfer function for an N-bit digital-to-analog converter (DAC) is:

V_{out} = ((D / 2^{N}) \times G \times V_{ref}) + V_{OS}

Where

V_{OUT}

is the analog output,

D

is the digital input,

G

is the gain,

V_{ref}

is the nominal full-scale voltage,and

V_{os}

is the offset voltage. For an ideal DAC channel,

G = 1

and

V_{os} = 0

Due to output buffer characteristics, the voltage offset may differ from part-to-part and introduce an absolute offset error on the analog output. To compensate the Vos, a calibration is required by a trimming technique.

The calibration is only valid when the DAC channelx is operating with buffer enabled (MODEx[2:0] = 0b000 or 0b001 or 0b100 or 0b101). if applied in other modes when the buffer is off, it has no effect. During the calibration:

The buffer output is disconnected from the pin internal/external connections and put in tristate mode (HiZ).

The buffer acts as a comparator to sense the middle-code value 0x800 and compare it to VREF+/2 signal through an internal bridge, then toggle its output signal to 0 or 1 depending on the comparison result (CAL_FLAGx bit).

Two calibration techniques are provided:

Factory trimming (default setting)

The DAC buffer offset is factory trimmed. The default value of OTRIMx[4:0] bits in DAC_CCR register is the factory trimming value and it is loaded once DAC digital interface is reset.

User trimming

The user trimming can be done when the operating conditions differs from nominal factory trimming conditions and in particular when

V_{DDA}

voltage,temperature,VREF+ values change and can be done at any point during application by software.

Note: Refer to the datasheet for more details of the Nominal factory trimming conditions

In addition,when

V_{DD}

is removed (example the device enters in STANDBY or VBAT modes) the calibration is required.

The steps to perform a user trimming calibration are as below:

If the DAC channel is active, write 0 to ENx bit in DAC_CR to disable the channel.

Select a mode where the buffer is enabled, by writing to DAC_MCR register, $MODEx [2 : 0] = 0 b 000$ or 0b001 or 0b100 or 0b101 .

Start the DAC channelx calibration, by setting the CENx bit in DAC_CR register to 1.

Apply a trimming algorithm:

a) Write a code into OTRIMx[4:0] bits, starting by 0b00000.

b) Wait for

t_{TRIM}

delay.

c) Check if CAL_FLAGx bit in DAC_SR is set to 1.

d) If CAL_FLAGx is set to 1, the OTRIMx[4:0] trimming code is found and can be used during device operation to compensate the output value, else increment OTRIMx[4:0] and repeat sub-steps from (a) to (d) again.

The software algorithm may use either a successive approximation or dichotomy techniques to compute and set the content of OTRIMx[4:0] bits in a faster way.

The commutation/toggle of CAL_FLAGx bit indicates that the offset is correctly compensated and the corresponding trim code must be kept in the OTRIMx[4:0] bits in DAC_CCR register.

Note:

t_{T R I M}

delay must be respected between the write to the OTRIMx[4:0] bits and the read of the CAL_FLAGx bit in DAC_SR register in order to get a correct value.This parameter is specified into datasheet electrical characteristics section.

V_{D D A}

,VREF+ and temperature conditions do not change during device operation while it enters more often in standby and VBAT mode, the software may store the OTRIMx[4:0] bits found in the first user calibration in the flash or in back-up registers. then to load/write them directly when the device power is back again thus avoiding to wait for a new calibration time. When CENx bit is set, it is not allowed to set ENx bit.

22.4.14 Dual DAC channel conversion modes (if dual channels are available)

To efficiently use the bus bandwidth in applications that require the two DAC channels at the same time, three dual registers are implemented: DHR8RD, DHR12RD and DHR12LD. A unique register access is then required to drive both DAC channels at the same time. For the wave generation, no accesses to DHRxxxD registers are required. As a result, two output channels can be used either independently or simultaneously.

15 conversion modes are possible using the two DAC channels and these dual registers. All the conversion modes can nevertheless be obtained using separate DHRx registers if needed.

All modes are described in the paragraphs below.

Independent trigger without wave generation

To configure the DAC in this conversion mode, the following sequence is required:

Set the two DAC channel trigger enable bits TEN1 and TEN2.

Configure different trigger sources by setting different values in the TSEL1 and TSEL2 bitfields.

Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD).

When a DAC channel1 trigger arrives, the DHR1 register is transferred into DAC_DOR1 (three dac_hclk clock cycles later).

When a DAC channel2 trigger arrives, the DHR2 register is transferred into DAC_DOR2 (three dac_hclk clock cycles later).

Independent trigger with single LFSR generation

To configure the DAC in this conversion mode, the following sequence is required:

Set the two DAC channel trigger enable bits TEN1 and TEN2.

Configure different trigger sources by setting different values in the TSEL1 and TSEL2 bitfields.

Configure the two DAC channel WAVEx[1:0] bits as 01 and the same LFSR mask value in the MAMPx[3:0] bits.

Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD).

When a DAC channel1 trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three dac_hclk clock cycles later). Then the LFSR1 counter is updated.

When a DAC channel2 trigger arrives, the LFSR2 counter, with the same mask, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three dac_hclk clock cycles later). Then the LFSR2 counter is updated.

Independent trigger with different LFSR generation

To configure the DAC in this conversion mode, the following sequence is required:

Set the two DAC channel trigger enable bits TEN1 and TEN2.

Configure different trigger sources by setting different values in the TSEL1 and TSEL2 bitfields.

Configure the two DAC channel WAVEx[1:0] bits as 01 and set different LFSR masks values in the MAMP1[3:0] and MAMP2[3:0] bits.

Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD).

When a DAC channel1 trigger arrives, the LFSR1 counter, with the mask configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three dac_hclk clock cycles later). Then the LFSR1 counter is updated.

When a DAC channel2 trigger arrives, the LFSR2 counter, with the mask configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three dac_hclk clock cycles later). Then the LFSR2 counter is updated.

Independent trigger with single triangle generation

To configure the DAC in this conversion mode, the following sequence is required:

Set the two DAC channel trigger enable bits TEN1 and TEN2.

Configure different trigger sources by setting different values in the TSEL1 and TSEL2 bitfields.

Configure the two DAC channel WAVEx[1:0] bits as $1 x$ and the same maximum amplitude value in the MAMPx[3:0] bits.

Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD).

When a DAC channel 1 trigger arrives, the DAC channel1 triangle counter, with the same triangle amplitude, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three dac_hclk clock cycles later). The DAC channel1 triangle counter is then updated.

When a DAC channel 2 trigger arrives, the DAC channel 2 triangle counter, with the same triangle amplitude, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three dac_hclk clock cycles later). The DAC channel2 triangle counter is then updated.

Independent trigger with different triangle generation

To configure the DAC in this conversion mode, the following sequence is required:

Set the two DAC channel trigger enable bits TEN1 and TEN2.

Configure different trigger sources by setting different values in the TSEL1 and TSEL2 bits.

Configure the two DAC channel WAVEx[1:0] bits as $1 x$ and set different maximum amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits.

Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD).

When a DAC channel 1 trigger arrives, the DAC channel 1 triangle counter, with a triangle amplitude configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three dac_hclk clock cycles later). The DAC channel1 triangle counter is then updated.

When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with a triangle amplitude configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three dac_hclk clock cycles later). The DAC channel2 triangle counter is then updated.

Independent trigger with single sawtooth generation

To configure the DAC in this conversion mode, the following sequence is required:

Configure different trigger sources by setting different values in STRSTTRIGSEL1[3:0], STRSTTRIGSEL2[3:0], STINCTRIGSEL2[3:0] and STINCTRIGSEL1[3:0] bits.

Configure the two DAC channel WAVEx[1:0] bits to 11 and set the same STRSTDATAx[11:0], STINCDATAx[15:0] and STDIRx values for each register.

When a DAC channel 1 trigger arrives, the DAC channel1 sawtooth counter updates the DHR1 register and transfers it into DAC_DOR1 (three AHB clock cycles later).

When a DAC channel 2 trigger arrives, the DAC channel 2 sawtooth counter updates the DHR1 register and transfers it into DAC_DOR1 (three AHB clock cycles later).

Independent trigger with different sawtooth wave generation

To configure the DAC in this conversion mode, the following sequence is required:

Configure different trigger sources by setting different values in the STRSTTRIGSEL1[23:0], STRSTTRIGSEL2[23:0], STINCTRIGSEL2[3:0] and STINCTRIGSEL1[3:0] bits.

Configure the two DAC channel WAVEx[1:0] bits as 11 and set different STRSTDATAx[11:0], STINCDATAx[15:0] and STDIRx value for each register.

When a DAC channel1 trigger arrives, the DAC channel1 sawtooth counter updates the DHR1 register and loads it into DAC_DOR1 (three AHB clock cycles later).

When a DAC channel2 trigger arrives, the DAC channel2 sawtooth counter updates the DHR2 register and loads it into DAC_DOR1 (three AHB clock cycles later).

Simultaneous software start

To configure the DAC in this conversion mode, the following sequence is required:

Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD).

In this configuration, one dac_hclk clock cycle later, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and DAC_DOR2, respectively.

Simultaneous trigger without wave generation

To configure the DAC in this conversion mode, the following sequence is required:

Set the two DAC channel trigger enable bits TEN1 and TEN2.

Configure the same trigger source for both DAC channels by setting the same value in the TSEL1 and TSEL2 bitfields.

Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD). When a trigger arrives, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and DAC_DOR2, respectively (after three dac_hclk clock cycles).

Simultaneous trigger with single LFSR generation

To configure the DAC in this conversion mode, the following sequence is required:

Set the two DAC channel trigger enable bits TEN1 and TEN2.

Configure the same trigger source for both DAC channels by setting the same value in the TSEL1 and TSEL2 bitfields.

Configure the two DAC channel WAVEx[1:0] bits as 01 and the same LFSR mask value in the MAMPx[3:0] bits.

Load the dual DAC channel data to the desired DHR register (DHR12RD, DHR12LD or DHR8RD).

When a trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three dac_hclk clock cycles later). The LFSR1 counter is then updated. At the same time, the LFSR2 counter, with the same mask, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three dac_hclk clock cycles later). The LFSR2 counter is then updated.

Simultaneous trigger with different LFSR generation

To configure the DAC in this conversion mode, the following sequence is required:

Set the two DAC channel trigger enable bits TEN1 and TEN2

Configure the same trigger source for both DAC channels by setting the same value in the TSEL1 and TSEL2 bitfields.

Configure the two DAC channel WAVEx[1:0] bits as 01 and set different LFSR mask values using the MAMP1[3:0] and MAMP2[3:0] bits.

Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD).

When a trigger arrives, the LFSR1 counter, with the mask configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three dac_hclk clock cycles later). The LFSR1 counter is then updated.

At the same time, the LFSR2 counter, with the mask configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three dac_hclk clock cycles later). The LFSR2 counter is then updated.

Simultaneous trigger with single triangle generation

To configure the DAC in this conversion mode, the following sequence is required:

Set the two DAC channel trigger enable bits TEN1 and TEN2

Configure the same trigger source for both DAC channels by setting the same value in the TSEL1 and TSEL2 bitfields.

Configure the two DAC channel WAVEx[1:0] bits as $1 x$ and the same maximum amplitude value using the MAMPx[3:0] bits.

Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD).

When a trigger arrives, the DAC channel1 triangle counter, with the same triangle amplitude, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three dac_hclk clock cycles later). The DAC channel1 triangle counter is then updated.

At the same time, the DAC channel2 triangle counter, with the same triangle amplitude, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three dac_hclk clock cycles later). The DAC channel2 triangle counter is then updated.

Simultaneous trigger with different triangle generation

To configure the DAC in this conversion mode, the following sequence is required:

Set the two DAC channel trigger enable bits TEN1 and TEN2

Configure the same trigger source for both DAC channels by setting the same value in the TSEL1 and TSEL2 bitfields.

Configure the two DAC channel WAVEx[1:0] bits as $1 x$ and set different maximum amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits.

Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD).

When a trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three AHB clock cycles later). Then the DAC channel1 triangle counter is updated.

At the same time, the DAC channel2 triangle counter, with a triangle amplitude configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three dac_hclk clock cycles later). Then the DAC channel2 triangle counter is updated.

Simultaneous trigger with single sawtooth wave generation

To configure the DAC in this conversion mode, the following sequence is required:

Configure the same trigger source for both DAC channels by setting the same value in STRSTTRIGSEL1[3:0],STRSTTRIGSEL2[3:0], STINCTRIGSEL2[3:0] and STINCTRIGSEL1[3:0] bits.

Configure the two DAC channel WAVEx[1:0] bits to 11 and set the same STRSTDATAx[11:0], STINCDATAx[15:0] and STDIRx value for each register.

When a trigger arrives, the DAC channel1/2 sawtooth counter updates DHR1 and DHR2 registers and loads them into DAC_DOR1/2 (three AHB clock cycles later).

Simultaneous trigger with different sawtooth wave generation

To configure the DAC in this conversion mode, the following sequence is required:

Configure the same trigger source for both DAC channels by setting the same value in STRSTTRIGSEL1[3:0], STRSTTRIGSEL2[3:0], STINCTRIGSEL2[3:0] bits and STINCTRIGSEL1[3:0] bits.

Configure the two DAC channel WAVEx[1:0] bits to 11 and set different STRSTDATAx[11:0], STINCDATAx[15:0], STDIRx values for each register.

When a trigger arrives, DAC channel1/2 sawtooth counter updates the DHR1 and DHR2 registers and loads them independently into DAC_DOR1/2 (three AHB clock cycles later).

22.7 DAC registers

Refer to Section 1 on page 73 for a list of abbreviations used in register descriptions.

The peripheral registers have to be accessed by words (32-bit).

22.7.1 DAC control register (DAC_CR)

Address offset: 0x00

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	CEN2	DMAU DRIE2	DMAE N2	MAMP2[3:0]				WAVE2[1:0]		TSEL2[3]	TSEL2[2]	TSEL2[1]	TSEL2[0]	TEN2	EN2
	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Res.	CEN1	DMAU DRIE1	DMAE N1	MAMP1[3:0]				WAVE1[1:0]		TSEL1[3]	TSEL1[2]	TSEL1[1]	TSEL1[0]	TEN1	EN1
	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bit 31 Reserved, must be kept at reset value.

Bit 30 CEN2: DAC channel2 calibration enable

This bit is set and cleared by software to enable/disable DAC channel2 calibration, it can be written only if EN2 bit is set to 0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored.

0: DAC channel2 in Normal operating mode

1: DAC channel2 in calibration mode

Note: This bit is available only on dual-channel DACs. Refer to Section 22.3: DAC

implementation.

Bit 29 DMAUDRIE2: DAC channel2 DMA underrun interrupt enable

This bit is set and cleared by software.

0: DAC channel2 DMA underrun interrupt disabled

1: DAC channel2 DMA underrun interrupt enabled

Note: This bit is available only on dual-channel DACs. Refer to Section 22.3: DAC

implementation.

Bit 28 DMAEN2: DAC channel2 DMA enable

This bit is set and cleared by software.

0: DAC channel2 DMA mode disabled

1: DAC channel2 DMA mode enabled

Note: This bit is available only on dual-channel DACs. Refer to Section 22.3: DAC implementation.

Bits 27:24 MAMP2[3:0]: DAC channel2 mask/amplitude selector

These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode.

0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1

0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3

0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7

0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15

0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31

0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63

0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127

0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255

1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511

1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023

1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047

\geq

1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

Note: These bits are available only on dual-channel DACs. Refer to Section 22.3: DAC implementation.

Bits 23:22 WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable

These bits are set/reset by software.

00: wave generation disabled

01: Noise wave generation enabled

10: Triangle wave generation enabled

11: Sawtooth wave generation enabled

Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)

These bits are available only on dual-channel DACs. Refer to Section 22.3: DAC

implementation.

Bits 21:18 TSEL2[3:0]: DAC channel2 trigger selection

These bits select the external event used to trigger DAC channel2

0000: SWTRIG2

0001: dac_ch2_trg1

0010: dac_ch2_trg2

1111: dac_ch2_trg15

Refer to the trigger selection tables in Section 22.4.2: DAC pins and internal signals for details on trigger configuration and mapping.

Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled).

These bits are available only on dual-channel DACs. Refer to Section 22.3: DAC implementation.

Bit 17 TEN2: DAC channel2 trigger enable

This bit is set and cleared by software to enable/disable DAC channel2 trigger 0: DAC channel2 trigger disabled and data written into the DAC_DHR2 register are transferred one dac_hclk clock cycle later to the DAC_DOR2 register

1: DAC channel2 trigger enabled and data from the DAC_DHR2 register are transferred three dac_hclk clock cycles later to the DAC_DOR2 register

Note: When software trigger is selected, the transfer from the DAC_DHR2 register to the DAC_DOR2 register takes only one dac_hclk clock cycle.

These bits are available only on dual-channel DACs. Refer to Section 22.3: DAC implementation.

Bit 16 EN2: DAC channel2 enable

This bit is set and cleared by software to enable/disable DAC channel2.

0: DAC channel2 disabled

1: DAC channel2 enabled

Note: These bits are available only on dual-channel DACs. Refer to Section 22.3: DAC implementation.

Bit 15 Reserved, must be kept at reset value.

Bit 14 CEN1: DAC channel1 calibration enable

This bit is set and cleared by software to enable/disable DAC channel1 calibration, it can be written only if bit

EN 1 = 0

into

DAC_CR

(the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored.

0: DAC channel 1 in Normal operating mode

1: DAC channel 1 in calibration mode

Bit 13 DMAUDRIE1: DAC channel1 DMA Underrun Interrupt enable

This bit is set and cleared by software.

0: DAC channel1 DMA Underrun Interrupt disabled

1: DAC channel1 DMA Underrun Interrupt enabled

Bit 12 DMAEN1: DAC channel1 DMA enable

This bit is set and cleared by software.

0: DAC channel1 DMA mode disabled

1: DAC channel1 DMA mode enabled

Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector