29 General-purpose timers (TIM2/TIM3/TIM4/TIM5)

29.1 TIM2/TIM3/TIM4/TIM5 introduction

The general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a programmable prescaler.

They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM).

Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers.

The timers are completely independent, and do not share any resources. They can be synchronized together as described in Section 29.4.23: Timer synchronization.

29.2 TIM2/TIM3/TIM4/TIM5 main features

General-purpose TIMx timer features include:

16-bit or 32-bit up, down, up/down auto-reload counter.

16-bit programmable prescaler used to divide (also "on the fly") the counter clock frequency by any factor between 1 and 65535 .

Up to 4 independent channels for:

Input capture

Output compare

PWM generation (Edge- and Center-aligned modes)

One-pulse mode output

Synchronization circuit to control the timer with external signals and to interconnect several timers.

Interrupt/DMA generation on the following events:

Update: counter overflow/underflow, counter initialization (by software or internal/external trigger)

Trigger event (counter start, stop, initialization or count by internal/external trigger)

Input capture

Output compare

Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning purposes

Trigger input for external clock or cycle-by-cycle current management

Timer instance	TIM2	TIM3	TIM4	TIM5
Resolution	32-bit	16-bit	16-bit	32-bit
OCREF clear selection	Yes	Yes	No	No
Sources	tim_etrf tim_ocref_clr[7:0]	tim_etrf tim_ocref_clr[7:0]	tim_etrf -	tim_etrf -

TIM2/TIM3/TIM4/TIM5 pins and internal signals

Table 270 and Table 271 in this section summarize the TIM inputs and outputs.

Table 270. TIM input/output pins

Pin name	Signal type	Description
TIM_CH1 TIM_CH2 TIM_CH3 TIM_CH4	Input/Output	Timer multi-purpose channels. Each channel be used for capture, compare or PWM. TIM_CH1 and TIM_CH2 can also be used as external clock (below 1/4 of the tim_ker_ck clock) , external trigger and quadrature encoder inputs. TIM_CH1, TIM_CH2 and TIM_CH3 can be used to interface with digital hall effect sensors.
TIM_ETR	Input	External trigger input. This input can be used as external trigger or as external clock source. This input can receive a clock with a frequency higher than the tim_ker_ck if the tim_etr_in prescaler is used.

Table 271. TIM internal input/output signals

Internal signal name	Signal type	Description
tim_ti1_in[15:0] tim_ti2_in[15:0] tim_ti3_in[15:0] tim_ti4_in[15:0]	Input	Internal timer inputs bus. The tim_ti1_in[15:0] and tim_ti2_in[15:0] inputs can be used for capture or as external clock (below 1/4 of the tim_ker_ck clock) and for quadrature encoder signals.
tim_etr[15:0]	Input	External trigger internal input bus. These inputs can be used as trigger, external clock or for hardware cycle-by-cycle pulse width control. These inputs can receive clock with a frequency higher than the tim_ker_ck if the tim_etr_in prescaler is used.
tim_itr[15:0]	Input	Internal trigger input bus. These inputs can be used for the slave mode controller or as a input clock (below 1/4 of the tim_ker_ck clock).
tim_trgo	Output	Internal trigger output. This trigger can trigger other on-chip peripherals.
tim_ocref_clr[7:0]	Input	Timer tim_ocref_clr input bus. These inputs can be used to clear the tim_ocxref signals, typically for hardware cycle-by-cycle pulse width control.
tim_pclk	Input	Timer APB clock.
tim_ker_ck	Input	Timer kernel clock

Table 271. TIM internal input/output signals (continued)

Internal signal name	Signal type	Description
tim_it	Output	Global Timer interrupt, gathering capture/compare, update and break trigger requests.
tim_cc1_dma tim_cc2_dma tim cc3 dma tim_cc4_dma	Output	Timer capture/compare [4:1] dma requests.
tim_upd_dma	Output	Timer update dma request.
tim_trg_dma	Output	Timer trigger dma request.

Table 272, Table 273, Table 274 and Table 275 are listing the sources connected to the tim_ti[4:1] input multiplexers.

Table 272. Interconnect to the tim_ti1 input multiplexer

tim_ti1 inputs	Sources
tim_ti1 inputs	TIM2	TIM3	TIM4	TIM5
tim_ti1_in0	TIM2_CH1	TIM3_CH1	TIM4_CH1	TIM5_CH1
tim_ti1_in1	comp1_out	comp1_out	comp1_out	LSI
tim_ti1_in2	comp2_out	comp2_out	comp2_out	LSE
tim_ti1_in3	comp3_out	comp3_out	comp3_out	RTC wake-up
tim_ti1_in4	comp4_out	comp4_out	comp4_out	comp1_out
tim_ti1_in5	comp5_out	comp5_out	comp5_out	comp2_out
tim_ti1_in6	Reserved	comp6_out	comp6_out	comp3_out
tim_ti1_in7		comp7_out	comp7_out	comp4_out
tim_ti1_in8		Reserved	Reserved	comp5_out
tim_ti1_in9				comp6_out
tim_ti1_in10				comp7_out
tim_ti1_in[15:11]	Reserved

Table 273. Interconnect to the tim_ti2 input multiplexer

tim_ti2 inputs	Sources
tim_ti2 inputs	TIM2	TIM3	TIM4	TIM5
tim_ti2_in0	TIM2_CH2	TIM3_CH2	TIM4_CH2	TIM5_CH2
tim_ti2_in1	comp1_out	comp1_out	comp1_out	comp1_out
tim_ti2_in2	comp2_out	comp2_out	comp2_out	comp2_out
tim_ti2_in3	comp3_out	comp3_out	comp3_out	comp3_out

Table 273. Interconnect to the tim_ti2 input multiplexer (continued)

tim_ti2 inputs	Sources
tim_ti2 inputs	TIM2	TIM3	TIM4	TIM5
tim_ti2_in4	comp4_out	comp4_out	comp4_out	comp4_out
tim_ti2_in5	comp6_out	comp5_out	comp5_out	comp5_out
tim_ti2_in6	Reserved	comp6_out	comp6_out	comp6_out
tim_ti2_in7	Reserved	comp7_out	comp7_out	comp7_out
tim_ti2_in[15:8]	Reserved

Table 274. Interconnect to the tim_ti3 input multiplexer

tim_ti3 inputs	Sources
tim_ti3 inputs	TIM2	TIM3	TIM4	TIM5
tim_ti3_in0	TIM2_CH3	TIM3_CH3	TIM4_CH3	TIM5_CH3
tim_ti3_in1	comp4_out	comp3_out	comp5_out	Reserved
tim_ti2_in[15:2]	Reserved

Table 275. Interconnect to the tim_ti4 input multiplexer

tim_ti4 inputs	Sources
tim_ti4 inputs	TIM2	TIM3	TIM4	TIM5
tim_ti4_in0	TIM2_CH4	TIM3_CH4	TIM4_CH4	TIM5_CH4
tim_ti4_in1	comp1_out	Reserved	comp6_out	Reserved
tim_ti4_in2	comp2_out	Reserved	Reserved	Reserved
tim_ti4_in[15:3]	Reserved

Table 276 lists the internal sources connected to the tim_itr input multiplexer.

Table 276. TIMx internal trigger connection

TIMx	TIM2	TIM3	TIM4	TIM5
tim_itr0	tim1_trgo	tim1_trgo	tim1_trgo	tim1_trgo
tim_itr1	Reserved	tim2_trgo	tim2_trgo	tim2_trgo
tim_itr2	tim3_trgo	Reserved	tim3_trgo	tim3_trgo
tim_itr3	tim4_trgo	tim4_trgo	Reserved	tim4_trgo
tim_itr4	tim5_trgo	tim5_trgo	tim5_trgo	Reserved
tim_itr5	tim8_trgo	tim8_trgo	tim8_trgo	tim8_trgo
tim_itr6	tim15_trgo	tim15_trgo	tim15_trgo	tim15_trgo
tim_itr7	tim16_oc1	tim16_oc1	tim16_oc1	tim16_oc1

Table 276. TIMx internal trigger connection (continued)

TIMx	TIM2	TIM3	TIM4	TIM5
tim_itr8	tim17_oc1	tim17_oc1	tim17_oc1	tim17_oc1
tim_itr9	tim20_trgo	tim20_trgo	tim20_trgo	tim20_trgo
tim_itr10	hrtim_out_sync2	hrtim_out_sync2	hrtim_out_sync2	hrtim_out_sync2
tim_itr11	USB SOF SYNC	Reserved	Reserved	Reserved
tim_itr[15:12]	Reserved

Table 277 lists the internal sources connected to the tim_etr input multiplexer.

Table 277. Interconnect to the tim_etr input multiplexer

Timer external trigger input signal	Timer external trigger signals assignment
Timer external trigger input signal	TIM2	TIM3	TIM4	TIM5
tim_etr0	TIM2_ETR	TIM3_ETR	TIM4_ETR	TIM5_ETR
tim_etr1	comp1_out	comp1_out	comp1_out	comp1_out
tim_etr2	comp2_out	comp2_out	comp2_out	comp2_out
tim_etr3	comp3_out	comp3_out	comp3_out	comp3_out
tim_etr4	comp4_out	comp4_out	comp4_out	comp4_out
tim_etr5	comp5_out	comp5_out	comp5_out	comp5_out
tim_etr6	comp6_out	comp6_out	comp6_out	comp6_out
tim_etr7	comp7_out	comp7_out	comp7_out	comp7_out
tim_etr8	TIM3_ETR	TIM2_ETR	TIM3_ETR	TIM2_ETR
tim_etr9	TIM4_ETR	TIM4_ETR	TIM5_ETR	TIM3_ETR
tim_etr10	TIM5_ETR	Reserved	Reserved	Reserved
tim_etr11	LSE	adc2_awd1
tim_etr12	Reserved	adc2_awd2
tim_etr13	Reserved	adc2_awd3
tim_etr[15:14]	Reserved

Table 278 lists the internal sources connected to the tim_ocref_clr input multiplexer.

Table 278. Interconnect to the tim_ocref_clr input multiplexer

Timer tim_ocref_clr signal	Timer tim_ocref_clr signals assignment
Timer tim_ocref_clr signal	TIM2	TIM3	TIM4	TIM5
tim_ocref_clr0	comp1_out	comp1_out	Reserved	Reserved
tim_ocref_clr1	comp2_out	comp2_out
tim_ocref_clr2	comp3_out	comp3_out
tim_ocref_clr3	comp4_out	comp4_out
tim_ocref_clr4	comp5_out	comp5_out
tim_ocref_clr5	comp6_out	comp6_out
tim_ocref_clr6	comp7_out	comp7_out
tim_ocref_clr7	Reserved

29.4.3 Time-base unit

The main block of the programmable timer is a 16-bit/32-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler.

The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.

The time-base unit includes:

Counter Register (TIMx_CNT)

Prescaler Register (TIMx_PSC):

Auto-Reload Register (TIMx_ARR)

The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration.

The counter is clocked by the prescaler output tim_cnt_ck, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling).

Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.

Prescaler description

The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit/32-bit register (in the TIMx_PSC register). It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event. Figure 359 and Figure 360 give some examples of the counter behavior when the prescaler ratio is changed on the fly:

Figure 360. Counter timing diagram with prescaler division change from 1 to 4

29.4.4 Counter modes

Upcounting mode

In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event.

An Update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).

The UEV event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0 . However, the counter restarts from 0 , as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (UIF bit in

TIMx_SR register) is set (depending on the URS bit):

The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register)

The auto-reload shadow register is updated with the preload value (TIMx_ARR)

The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36.

Figure 366. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded)

Downcounting mode

In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0 , then restarts from the auto-reload value and generates a counter underflow event.

An Update event can be generated at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller)

The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0 . However, the counter restarts from the current auto-reload value, whereas the counter of the prescaler restarts from 0 (but the prescale rate doesn't change).

In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (UIF bit in

TIMx_SR register) is set (depending on the URS bit):

The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register).

The auto-reload active register is updated with the preload value (content of the TIMx_ARR register). Note that the auto-reload is updated before the counter is reloaded, so that the next period is the expected one.

The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. reload value down to 1 and generates a counter underflow event. Then it restarts counting from 0 .

Figure 367. Counter timing diagram, internal clock divided by 1

Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to '00'. The Output compare interrupt flag of channels configured in output is set when: the counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center aligned mode 2, CMS = "10") the counter counts up and down (Center aligned mode 3, CMS = "11").

In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated by hardware and gives the current direction of the counter.

The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. In this case, the counter restarts counting from 0 , as well as the counter of the prescaler.

The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0 . However, the counter continues counting up and down, based on the current auto-reload value.

When an update event occurs, all the registers are updated and the update flag (UIF bit in

TIMx_SR register) is set (depending on the URS bit):

The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register).

The auto-reload active register is updated with the preload value (content of the TIMx_ARR register). Note that if the update source is a counter overflow, the auto-reload is updated before the counter is reloaded, so that the next period is the expected one (the counter is loaded with the new value).

The following figures show some examples of the counter behavior for different clock frequencies.

29.4.5 Clock selection

The counter clock can be provided by the following clock sources:

Internal clock (tim_ker_ck)

External clock mode1: external input pin (tim_ti1 or tim_ti2)

External clock mode2: external trigger input (tim_etr_in)

Internal trigger inputs (tim_itr): using one timer as prescaler for another timer, for example, Timer 1 can be configured to act as a prescaler for Timer 2. Refer to : Using one timer as prescaler for another timer on page 1307 for more details.

Internal clock source (tim_ker_ck)

If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1 , the prescaler is clocked by the internal clock tim_ker_ck.

Figure 378 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. each rising or falling edge on a selected input.

External clock source mode 1

This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at

Figure 379. tim_ti2 external clock connection example

Codes ranging from 01000 to 11111: tim_itr[15:0].

For example, to configure the upcounter to count in response to a rising edge on the tim_ti2 input, use the following procedure:

Select the proper tim_ti2_in[15:0] source (internal or external) with the TI2SEL[3:0] bits in the TIMx_TISEL register.

Configure channel 2 to detect rising edges on the tim_ti2 input by writing CC2S= '01 in the TIMx_CCMR1 register.

Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed,keep IC2F=0000).

Note: The capture prescaler is not used for triggering, so it does not need to be configured.

Select rising edge polarity by writing CC2P=0 and CC2NP=0 in the TIMx_CCER register.

Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register.

Select tim_ti2 as the input source by writing TS=00110 in the TIMx_SMCR register.

Enable the counter by writing CEN=1 in the TIMx_CR1 register.

When a rising edge occurs on tim_ti2, the counter counts once and the TIF flag is set.

The delay between the rising edge on tim_ti2 and the actual clock of the counter is due to the resynchronization circuit on tim_ti2 input.

Figure 380. Control circuit in external clock mode 1

External clock source mode 2

This mode is selected by writing ECE=1 in the TIMx_SMCR register.

The counter can count at each rising or falling edge on the external trigger input tim_etr_in.

Figure 381 gives an overview of the external trigger input block.

Figure 381. External trigger input block

For example, to configure the upcounter to count each 2 rising edges on tim_etr_in, use the following procedure:

Select the proper tim_etr_in source (internal or external) with the ETRSEL[3:0] bits in the TIMx_AF1 register.

As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.

Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register

Select rising edge detection on the tim_etr_in by writing ETP=0 in the TIMx_SMCR register

Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.

Enable the counter by writing CEN=1 in the TIMx_CR1 register.

The counter counts once each 2 tim_etr_in rising edges.

The delay between the rising edge on tim_etr_in and the actual clock of the counter is due to the resynchronization circuit on the tim_etrp signal. As a consequence, the maximum frequency that can be correctly captured by the counter is at most

1 / 4

of TIMxCLK frequency. When the ETRP signal is faster, the user must apply a division of the external signal by a proper ETPS prescaler setting.

29.4.6 Capture/compare channels

Each Capture/Compare channel is built around a capture/compare register (including a shadow register), an input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control).

The following figure gives an overview of one Capture/Compare channel.

The input stage samples the corresponding tim_tix input to generate a filtered signal tim_tixf. Then, an edge detector with polarity selection generates a signal (tim_tixfpy) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS).

Figure 383. Capture/compare channel (example: channel 1 input stage)

The output stage generates an intermediate waveform which is then used for reference:

tim_ocxref (active high). The polarity acts at the end of the chain.

Figure 384. Capture/compare channel 1 main circuit

Figure 385. Output stage of capture/compare channel (channel 1, idem ch.2, 3 and 4)

Available on some instances only. If not available, tim_etrf is directly connected to tim_ocref_clr_int.

The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register.

In capture mode, captures are actually done in the shadow register, which is copied into the preload register. In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter.

29.4.7 Input capture mode

In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to 0 or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when it is written with 0 .

The following example shows how to capture the counter value in TIMx_CCR1 when tim_ti1 input rises. To do this, use the following procedure:

Select the proper tim_tix_in[15:0] source (internal or external) with the TI1SEL[3:0] bits in the TIMx_TISEL register.

Select the active input: TIMx_CCR1 must be linked to the tim_ti1 input, so write the CC1S bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00 , the channel is configured in input and the TIMx_CCR1 register becomes read-only.

Program the needed input filter duration in relation with the signal connected to the timer (when the input is one of the tim_tix (ICxF bits in the TIMx_CCMRx register). Let's imagine that, when toggling, the input signal is not stable during at must 5 internal clock cycles. We must program a filter duration longer than these 5 clock cycles. We can validate a transition on tim_ti1 when 8 consecutive samples with the new level have been detected (sampled at $f_{DTS}$ frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register.

Select the edge of the active transition on the tim_ti1 channel by writing the CC1P and CC1NP and CC1NP bits to 000 in the TIMx_CCER register (rising edge in this case).

Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to 00 in the TIMx_CCMR1 register).

Enable capture from the counter into the capture register by setting the CC1E bit in the TIMx_CCER register.

If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the TIMx_DIER register.

When an input capture occurs:

The TIMx_CCR1 register gets the value of the counter on the active transition.

CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared.

An interrupt is generated depending on the CC1IE bit.

A DMA request is generated depending on the CC1DE bit.

In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which may happen after reading the flag and before reading the data.

Note:

IC interrupt and/or DMA requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register.

29.4.8 PWM input mode

This mode is used to measure both the period and the duty cycle of a PWM signal

connected to single tim_tix input:

The TIMx_CCR1 register holds the period value (interval between two consecutive rising edges)

The TIM_CCR2 register holds the pulse width (interval between two consecutive rising and falling edges)

This mode is a particular case of input capture mode. The set-up procedure is similar with the following differences:

Two ICx signals are mapped on the same tim_tix input.

These 2 ICx signals are active on edges with opposite polarity.

One of the two TlxFP signals is selected as trigger input and the slave mode controller is configured in reset mode.

The period and the pulse width of a PWM signal applied on tim_ti1 can be measured using the following procedure:

Select the proper tim_tix_in[15:0] source (internal or external) with the TI1SEL[3:0] bits in the TIMx_TISEL register.

Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (tim_ti1 selected).

Select the active polarity for tim_ti1fp1 (used both for capture in TIMx_CCR1 and counter clear): write the CC1P to ' 0 ' and the CC1NP bit to ' 0 ' (active on rising edge).

Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 register (tim_ti1 selected).

Select the active polarity for tim_ti1fp2 (used for capture in TIMx_CCR2): write the CC2P bit to '1' and the CC2NP bit to ' 0 ' (active on falling edge).

Select the valid trigger input: write the TS bits to 00101 in the TIMx_SMCR register (tim_ti1fp1 selected).

Configure the slave mode controller in reset mode: write the SMS bits to 100 in the TIMx_SMCR register.

Enable the captures: write the CC1E and CC2E bits to '1 in the TIMx_CCER register.

The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only tim_ti1fp1 and tim_ti2fp2 are connected to the slave mode controller.

29.4.9 Forced output mode

In output mode (CCxS bits

= 00

in the TIMx_CCMRx register),each output compare signal (tim_ocxref and then tim_ocx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter.

To force an output compare signal (tim_ocxref/tim_ocx) to its active level, one just needs to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus tim_ocxref is forced high (tim_ocxref is always active high) and tim_ocx get opposite value to CCxP polarity bit.

For example: CCxP=0 (tim_ocx active high)

=>

tim_ocx is forced to high level.

tim_ocxref signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx register.

Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the Output Compare Mode section.

29.4.10 Output compare mode

This function is used to control an output waveform or indicating when a period of time has elapsed.

When a match is found between the capture/compare register and the counter, the output compare function:

Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.

Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).

Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the TIMx_DIER register).

Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request selection).

The TIMx_CCRx registers can be programmed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register.

In output compare mode, the update event UEV has no effect on tim_ocxref and tim_ocx output. The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One-pulse mode).

Procedure

Select the counter clock (internal, external, prescaler).

Write the desired data in the TIMx_ARR and TIMx_CCRx registers.

Set the CCxIE and/or CCxDE bits if an interrupt and/or a DMA request is to be generated.

Select the output mode. For example:

a) Write OCxM = 0011 to toggle tim_ocx output pin when CNT matches CCRx

b) Write OCxPE

= 0

to disable preload register

c) Write

CCxP = 0

to select active high polarity

d) Write

CCxE = 1

to enable the output

Enable the counter by setting the CEN bit in the TIMx_CR1 register.

The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 387.

29.4.11 PWM mode

Pulse width modulation mode is used to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.

The PWM mode can be selected independently on each channel (one PWM per tim_ocx output) by writing 110 (PWM mode 1) or '111 (PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. The corresponding preload register must be enabled by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.

As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, all registers must be initialized by setting the UG bit in the TIMx_EGR register.

tim_ocx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. tim_ocx output is enabled by the CCxE bit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more details.

In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CCRx

\leq

TIMx_CNT or TIMx_CNT

\leq

TIMx_CCRx (depending on the direction of the counter). The tim_ocref_clr can be cleared by an external event through the tim_etr_in or the tim_oceref_clr signals. In this case the tim_ocref_clr signal is asserted only:

After a compare match event

When the output compare mode (OCxM bits in TIMx_CCMRx register) switches from the "frozen" configuration (no comparison, OCxM='000) to one of the PWM modes (OCxM=‘110 or ’111). This forces the PWM by software while the timer is running.

The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register.

PWM edge-aligned mode

Upcounting configuration

Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Upcounting mode on page 1245.

In the following example, we consider PWM mode 1. The reference PWM signal tim_ocxref is high as long as TIMx_CNT

Figure 388. Edge-aligned PWM waveforms (ARR=8)

Downcounting configuration

Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to Downcounting mode on page 1249.

In PWM mode 1, the reference signal tim_ocxref is low as long as TIMx_CNT>TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in TIMx_ARR, then tim_ocxref is held at 100%. PWM is not possible in this mode.

PWM center-aligned mode

Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from 100 (all the remaining configurations having the same effect on the tim_ocxref/tim_ocx signals). The compare flag is set when the counter counts up, when it counts down or both when it counts up and down depending on the CMS bits configuration. The direction bit

(DIR) in the TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to Center-aligned mode (up/down counting) on page 1252.

Figure 389 shows some center-aligned PWM waveforms in an example where:

TIMx_ARR=8,

PWM mode is the PWM mode 1,

The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register.

Hints on using center-aligned mode:

When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software.

Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results. In particular:

The direction is not updated if a value greater than the auto-reload value is written in the counter (TIMx_CNT>TIMx_ARR). For example, if the counter was counting up, it continues to count up.

The direction is updated if 0 or the TIMx_ARR value is written in the counter but no Update Event UEV is generated.

The safest way to use center-aligned mode is to generate an update by software (setting the UG bit in the TIMx_EGR register) just before starting the counter and not to write the counter while it is running.

Dithering mode

The PWM mode effective resolution can be increased by enabling the dithering mode, using the DITHEN bit in the TIMx_CR1 register. This applies to both the CCR (for duty cycle resolution increase) and ARR (for PWM frequency resolution increase).

The operating principle is to have the actual CCR (or ARR) value slightly changed (adding or not one timer clock period) over 16 consecutive PWM periods, with predefined patterns. This allows a 16-fold resolution increase, considering the average duty cycle or PWM period. The Figure 390 below presents the dithering principle applied to 4 consecutive PWM cycles. Figure 391 for example):

Figure 390. Dithering principle

When the dithering mode is enabled, the register coding is changed as following (see

The 4 LSBs are coding for the enhanced resolution part (fractional part).

The MSBs are left-shifted by 4 places and are coding for the base value. In 16-bit mode, the 16-bit format is maintained.

Table 279. CCR and ARR register change dithering pattern

LSB value	PWM period
LSB value	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16
0000	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
0001	+1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
0010	+1	-	-	-	-	-	-	-	+1	-	-	-	-	-	-	-
0011	+1	-	-	-	+1	-	-	-	+1	-	-	-	-	-	-	-
0100	+1	-	-	-	+1	-	-	$-$	+1	$-$	-	-	+1	-	-	-
0101	+1	-	+1	-	+1	-	-	-	+1	-	-	-	+1	-	-	-
0110	+1	-	+1	-	+1	-	-	-	+1	-	+1	-	+1	-	-	-
0111	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-	-	-
1000	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-
1001	+1	+1	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-
1010	+1	+1	+1	-	+1	-	+1	-	+1	+1	+1	-	+1	-	+1	-
1011	+1	+1	+1	-	+1	+1	+1	-	+1	+1	+1	-	+1	-	+1	-
1100	+1	+1	+1	-	+1	+1	+1	-	+1	+1	+1	-	+1	+1	+1	-
1101	+1	+1	+1	+1	+1	+1	+1	-	+1	+1	+1	-	+1	+1	+1	-
1110	+1	+1	+1	+1	+1	+1	+1	-	+1	+1	+1	+1	+1	+1	+1	-
1111	+1	+1	+1	+1	+1	+1	+1	+1	+1	+1	+1	+1	+1	+1	+1	-

The dithering mode is also available in center-aligned PWM mode (CMS bits in TIMx_CR1 register are not equal to '00'). In this case, the dithering pattern is applied over 8 consecutive PWM periods, considering the up and down counting phases as shown in the Figure 395 below.

Figure 395. Dithering effect on duty cycle in center-aligned PWM mode

No dithering Dithering up Dithering down

Table 280 below shows how the dithering pattern is added in center-aligned PWM mode.

Table 280. CCR register change dithering pattern in center-aligned PWM mode

LSB value	PWM period
	1		2		3		4		5		6		7		8
	Up	Dn	Up	Dn	Up	Dn	Up	Dn	Up	Dn	Up	Dn	Up	Dn	Up	Dn
0000	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
0001	+1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
0010	+1	-	-	-	-	-	-	-	+1	-	-	-	-	-	-	-
0011	+1	-	-	-	+1	-	-	-	+1	-	-	-	-	-	-	-
0100	+1	-	-	-	+1	-	-	-	+1	-	-	-	+1	-	-	-
0101	+1	-	+1	-	+1	-	-	-	+1	-	-	-	+1	-	-	-
0110	+1	-	+1	-	+1	-	-	-	+1	-	+1	-	+1	-	-	-
0111	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-	-	-
1000	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-
1001	+1	+1	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-
1010	+1	+1	+1	-	+1	-	+1	-	+1	+1	+1	-	+1	-	+1	-
1011	+1	+1	+1	-	+1	+1	+1	-	+1	+1	+1	-	+1	-	+1	-
1100	+1	+1	+1	-	+1	+1	+1	-	+1	+1	+1	-	+1	+1	+1	-
1101	+1	+1	+1	+1	+1	+1	+1	-	+1	+1	+1	-	+1	+1	+1	-
1110	+1	+1	+1	+1	+1	+1	+1	-	+1	+1	+1	+1	+1	+1	+1	-
1111	+1	+1	+1	+1	+1	+1	$+ 1$	$+ 1$	+1	+1	+1	+1	+1	+1	+1	-

29.4.12 Asymmetric PWM mode

Asymmetric mode allows two center-aligned PWM signals to be generated with a programmable phase shift. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and the phase-shift are determined by a pair of TIMx_CCRx registers. One register controls the PWM during up-counting, the second during down counting, so that PWM is adjusted every half PWM cycle:

tim_oc1refc (or tim_oc2refc) is controlled by TIMx_CCR1 and TIMx_CCR2

Figure 396 shows an example of signals that can be generated using Asymmetric PWM

mode (channels 1 to 4 are configured in Asymmetric PWM mode 2).

Figure 396. Generation of 2 phase-shifted PWM signals with

50 %

duty cycle

29.4.13 Combined PWM mode

Combined PWM mode allows two edge or center-aligned PWM signals to be generated with programmable delay and phase shift between respective pulses. While the frequency is

determined by the value of the TIMx_ARR register, the duty cycle and delay are determined by the two TIMx_CCRx registers. The resulting signals, tim_ocxrefc, are made of an OR or AND logical combination of two reference PWMs:

tim_oc1refc (or tim_oc2refc) is controlled by TIMx_CCR1 and TIMx_CCR2

tim_oc3refc (or tim_oc4refc) is controlled by TIMx_CCR3 and TIMx_CCR4

Combined PWM mode can be selected independently on two channels (one tim_ocx output per pair of CCR registers) by writing '1100' (Combined PWM mode 1) or '1101' (Combined PWM mode 2) in the OCxM bits in the TIMx_CCMRx register.

When a given channel is used as combined PWM channel, its secondary channel must be configured in the opposite PWM mode (for instance, one in Combined PWM mode 1 and the other in Combined PWM mode 2). Note: bit is not contiguous with the 3 least significant ones.

Figure 397 shows an example of signals that can be generated using combined PWM mode, obtained with the following configuration:

Channel 1 is configured in Combined PWM mode 2,

Channel 2 is configured in PWM mode 1,

Channel 3 is configured in Combined PWM mode 2,

Channel 4 is configured in PWM mode 1

Figure 397. Combined PWM mode on channels 1 and 3

29.4.14 Clearing the tim_ocxref signal on an external event

The tim_ocxref signal of a given channel can be cleared when a high level is applied on the tim_ocref_clr_int input (OCxCE enable bit in the corresponding TIMx_CCMRx register set to 1). tim_ocxref remains low until the next transition to the active state, on the following PWM cycle. This function can only be used in Output compare and PWM modes. It does not work in Forced mode.

The tim_ocref_clr_int source depends on the OCREF clear selection feature implementation, refer to Section 29.3: TIM2/TIM3/TIM4/TIM5 implementation.

If the OCREF clear selection feature is implemented, the tim_ocref_clr_int can be selected between the tim_ocref_clr input and the tim_etrf input (tim_etr_in after the filter) by configuring the OCCS bit in the TIMx_SMCR register. The tim_ocref_clr input can be selected among several tim_ocref_clr[7:0] inputs, using the OCRSEL[2:0] bitfield in the TIMx_AF2 register, as shown in Figure 398 below.

Figure 398. OCREF_CLR input selection multiplexer

If the OCREF clear selection feature is not implemented, the tim_ocref_clr_int input is directly connected to the tim_etrf input.

For example, the tim_ocref_clr_int signal can be connected to the output of a comparator to be used for current handling. In this case, tim_etr_in must be configured as follows:

The external trigger prescaler must be kept off: bits ETPS[1:0] in the TIMx_SMCR register are cleared to 00 .

The external clock mode 2 must be disabled: bit ECE in the TIM1_SMCR register is cleared to 0 .

The external trigger polarity (ETP) and the external trigger filter (ETF) can be configured according to the application's needs.

Figure 399 shows the behavior of the tim_ocxref signal when the tim_etrf input becomes high, for both values of the OCxCE enable bit. In this example, the timer TIMx is programmed in PWM mode.

Figure 399. Clearing TIMx tim_ocxref

Note: In case of a PWM with a 100% duty cycle (if CCRx>ARR), tim_ocxref is enabled again at the next counter overflow.

29.4.15 One-pulse mode

One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay.

Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. One-pulse mode is selected by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV.

A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be:

Figure 400. Example of One-pulse mode

For example one may want to generate a positive pulse on tim_oc1 with a length of

t_{PULSE}

and after a delay of

t_{DELAY}

as soon as a positive edge is detected on the tim_ti2 input pin.

Let's use tim_ti2fp2 as trigger 1:

Select the proper tim_ti2_in[15:0] source (internal or external) with the TI2SEL[3:0] bits in the TIMx_TISEL register.

Map tim_ti2fp2 on tim_ti2 by writing CC2S=01 in the TIMx_CCMR1 register.

tim_ti2fp2 must detect a rising edge, write CC2P=0 and CC2NP='0' in the TIMx_CCER register.

Configure tim_ti2fp2 as trigger for the slave mode controller (tim_trgi) by writing TS=00110 in the TIMx_SMCR register.

tim_ti2fp2 is used to start the counter by writing SMS to '110 in the TIMx_SMCR register (trigger mode).

The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler).

The $t_{DELAY}$ is defined by the value written in the TIMx_CCR1 register.

The $t_{PULSE}$ is defined by the difference between the auto-reload value and the compare value (TIMx_ARR - TIMx_CCR1).

Let's say one want to build a waveform with a transition from ' 0 to ' 1 when a compare match occurs and a transition from '1 to ' 0 when the counter reaches the auto-reload value. To do this PWM mode 2 must be enabled by writing OC1M=111 in the TIMx_CCMR1 register. Optionally the preload registers can be enabled by writing OC1PE=1 in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case one has to write the compare value in the TIMx_CCR1 register, the auto-reload value in the TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger event on tim_ti2. CC1P is written to ' 0 in this example.

In our example, the DIR and CMS bits in the TIMx_CR1 register must be low.

Since only 1 pulse (Single mode) is needed, a 1 must be written in the OPM bit in the TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0 ). When OPM bit in the TIMx_CR1 register is set to ' 0 ', so the Repetitive Mode is selected.

Particular case: tim_ocx fast enable:

In One-pulse mode, the edge detection on tim_tix input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay

t_{DELAY}

min we can get.

If one wants to output a waveform with the minimum delay, the OCxFE bit can be set in the TIMx_CCMRx register. Then tim_ocxref (and tim_ocx) is forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.

29.4.16 Retriggerable one-pulse mode

This mode allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length, but with the following differences with Non-retriggerable one-pulse mode described in Section 29.4.15:

The pulse starts as soon as the trigger occurs (no programmable delay)

The pulse is extended if a new trigger occurs before the previous one is completed

The timer must be in Slave mode,with the bits

SMS [3 : 0] =

’1000’ (Combined Reset + trigger mode) in the TIMx_SMCR register, and the OCxM[3:0] bits set to '1000' or '1001' for Retriggerable OPM mode 1 or 2.

If the timer is configured in Up-counting mode, the corresponding CCRx must be set to 0 (the ARR register sets the pulse length). If the timer is configured in Down-counting mode CCRx must be above or equal to ARR.

Note:

In Retriggerable one-pulse mode,the CCxIF flag is not significant.

The OCxM[3:0] and SMS[3:0] bit fields are split into two parts for compatibility reasons, the most significant bit is not contiguous with the 3 least significant ones.

This mode must not be used with center-aligned PWM modes. It is mandatory to have CMS[1:0] = 00 in TIMx_CR1.

Figure 403. Pulse generation on compare event, for edge-aligned and encoder modes

This output compare mode is selected using the OC3M[3:0] and OC4M[3:0] bit fields in TIMx_CCMR2 register.

The pulse width is programmed using the PW[7:0] bitfield in the register, using a specific clock prescaled according to PWPRSC[2:0] bits, as follows:

t_{PW} = PW [7 : 0] \times t_{PWG}

where

t_{PWG} = (2^{(PWPRSC [2 : 0])}) \times t_{tim_\ker_ck}

gives the resolution and maximum values depending on the prescaler value.

The pulse is retriggerable: a new trigger while the pulse is ongoing, causes the pulse to be extended.

Note: If the two channels are enabled simultaneously, the pulses are issued independently as long as the trigger on one channel is not overlapping the pulse generated on the concurrent output. On the opposite, if the two triggers are overlapping, the pulse width related to the 1st arriving trigger is extended (because of the re-trigger), while the pulse width of the last arriving trigger is correct (as shown on the Figure 404 below).

Figure 404. Extended pulse width in case of concurrent triggers

29.4.18 Encoder interface mode

Quadrature encoder

To select Encoder Interface mode write SMS='0001 in the TIMx_SMCR register if the counter is counting on tim_ti1 edges only, SMS=0010 if it is counting on tim_ti2 edges only and SMS=0011 if it is counting on both tim_ti1 and tim_ti2 edges.

Select the tim_ti1 and tim_ti2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER register. CC1NP and CC2NP must be kept cleared. When needed, the input filter can be programmed as well.

The two inputs tim_ti1 and tim_ti2 are used to interface to an incremental encoder. Refer to Table 281. The counter is clocked by each valid transition on tim_ti1fp1 or tim_ti2fp2 (tim_ti1 and tim_ti2 after input filter and polarity selection, tim_ti1fp1=tim_ti1 if not filtered and not inverted, tim_ti2fp2=tim_ti2 if not filtered and not inverted) assuming that it is enabled (CEN bit in TIMx_CR1 register written to '1'). The sequence of transitions of the two inputs is evaluated and generates count pulses as well as the direction signal. Depending on the sequence the counter counts up or down,the DIR bit in the TIMx_CR1 register is modified by hardware accordingly. The DIR bit is calculated at each transition on any input (tim_ti1 or tim_ti2), whatever the counter is counting on tim_ti1 only, tim_ti2 only or both tim_ti1 and tim_ti2.

Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value in the TIMx_ARR register ( 0 to ARR or ARR down to 0 depending on the direction). So the TIMx_ARR must be configured before starting. In the same way, the capture, compare, prescaler, trigger output features continue to work as normal. Encoder mode and External clock mode 2 are not compatible and must not be selected together.

In this mode, the counter is modified automatically following the speed and the direction of the-quadrature encoder and its content, therefore, always represents the encoder's position. The count direction corresponds to the rotation direction of the connected sensor. The table summarizes the possible combinations, assuming tim_ti1 and tim_ti2 do not switch at the same time.

Table 281. Counting direction versus encoder signals(CC1P = CC2P = 0)

Active edge	SMS[3:0]	Level on opposite signal (tim_ti1fp1 for tim_ti2, tim_ti2fp2 for tim_ti1)	tim_ti1fp1 signal		tim_ti2fp2 signal
Active edge	SMS[3:0]		Rising	Falling	Rising	Falling
Counting on tim_ti1 only x1 mode	1110	High	Down	Up	No count	No count
Counting on tim_ti1 only x1 mode	1110	Low	No count	No count	No count	No count
Counting on tim_ti2 only x1 mode	1111	High	No count	No count	Up	Down
Counting on tim_ti2 only x1 mode	1111	Low	No count	No count	No count	No count
Counting on tim_ti1 only x2 mode	0001	High	Down	Up	No count	No count
Counting on tim_ti1 only x2 mode	0001	Low	Up	Down	No count	Down
Counting on tim ti2 only x2 mode	0010	High	No count	No count	Up	Down
Counting on tim ti2 only x2 mode	0010	Low	No count	No count	Down	Up
Counting on tim ti1 and tim ti2 x4 mode	0011	High	Down	Up	Up	Down
Counting on tim ti1 and tim ti2 x4 mode	0011	Low	Up	Down	Down	Up

A quadrature encoder can be connected directly to the MCU without external interface logic. However, comparators are normally be used to convert the encoder's differential outputs to digital signals. This greatly increases noise immunity. The third encoder output which indicate the mechanical zero position, may be connected to the external trigger input and trigger a counter reset.

Figure 405 gives an example of counter operation, showing count signal generation and direction control. It also shows how input jitter is compensated where both edges are selected. This might occur if the sensor is positioned near to one of the switching points. For this example we assume that the configuration is the following:

CC1S= 01 (TIMx_CCMR1 register, tim_ti1fp1 mapped on tim_ti1)

CC2S= 01 (TIMx_CCMR1 register, tim_ti2fp2 mapped on tim_ti2)

CC1P and CC1NP = '0' (TIMx_CCER register, tim_ti1fp1 noninverted, tim_ti1fp1=tim_ti1)

CC2P and CC2NP = '0' (TIMx_CCER register, tim_ti2fp2 noninverted, tim_ti2fp2=tim_ti2)

SMS= 0011 (TIMx_SMCR register, both inputs are active on both rising and falling edges)

CEN= 1 (TIMx_CR1 register, Counter is enabled)

The Figure 407 below shows the timer counter value during a speed reversal, for various counting modes.

The timer, when configured in Encoder Interface mode provides information on the sensor's current position. Dynamic information can be obtained (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode. The output of the encoder which indicates the mechanical zero can be used for this purpose. Depending on the time between two events, the counter can also be read at regular times. This can be done by latching the counter value into a third input capture register if available (then the capture signal must be periodic and can be generated by another timer). when available, it is also possible to read its value through a DMA request.

The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the update interrupt flag (UIF) into the timer counter register's bit 31 (TIMxCNT[31]). This allows both the counter value and a potential roll-over condition signaled by the UIFCPY flag to be read in an atomic way. It eases the calculation of angular speed by avoiding race conditions caused, for instance, by a processing shared between a background task (counter reading) and an interrupt (update interrupt).

There is no latency between the UIF and UIFCPY flag assertions.

In 32-bit timer implementations, when the IUFREMAP bit is set, bit 31 of the counter is overwritten by the UIFCPY flag upon read access (the counter's most significant bit is only accessible in write mode).

Clock plus direction encoder mode

In addition to the quadrature encoder mode, the timer offers support other types of encoders.

In the "clock plus direction" mode shown on Figure 408, the clock is provided on a single line, on tim_ti2, while the direction is forced using the tim_ti1 input.

This mode is enabled with the SMS[3:0] bitfield in the TIMx_SMCR register, as following:

1010: $\times 2$ mode,the counter is updated on both rising and falling edges of the clock

1011: x1 mode, the counter is updated on a single clock edge, as per CC2P bit value: $CC 2 P = 0$ corresponds to rising edge sensitivity and $CC 2 P = 1$ corresponds to falling edge sensitivity

The polarity of the direction signal on tim_ti1 is set with the CC1P bit: 0 corresponds to positive polarity (up-counting when tim_ti1 is high and down-counting when tim_ti1 is low) and CC1P = 1 corresponds to negative polarity (up-counting when tim_ti1 is low).

Figure 408. Direction plus clock encoder mode

Directional Clock encoder mode

In the "directional clock" mode on Figure 409, the clocks are provided on two lines, with a single one at once, depending on the direction, so as to have one up-counting clock line and one down-counting clock line.

This mode is enabled with the SMS[3:0] bitfield in the TIMx_SMCR register, as following:

1100: $x 2$ mode,the counter is updated on both rising and falling edges of any of the two clock line. The CC1P and CC2P bits are coding for the clock idle state. CCxP $= 0$ corresponds to high-level idle state (refer to Figure 409 below) and CCxP = 1 corresponds to low-level idle state (refer to Figure 410 below).

1101: x1 mode, the counter is updated on a single clock edge, as per CC1P and CC2P bit value. $CCxP = 0$ corresponds to falling edge sensitivity and high-level idle state (refer to Figure 409 below), $CCxP = 1$ corresponds to rising edge sensitivity and low-level idle state (refer to Figure 410 below).

Table 282. Counting direction versus encoder signals and polarity settings

Directional clock mode	SMS[3:0]	Level on opposite signal (tim_ti1fp1 for tim_ti2, tim_ti2fp2 for tim_ti1)	tim_ti1fp1 signal		tim_ti2fp2 signal
Directional clock mode	SMS[3:0]		Rising	Falling	Rising	Falling
x2 mode CCxP=0	1100	High	Down	Down	Up	Up
x2 mode CCxP=0	1100	Low	No count	No count	No count	No count
x2 mode CCxP=1	1100	High	No count	No count	No count	No count
x2 mode CCxP=1	1100	Low	Down	Down	Up	Up
x1 mode $CCxP = 0$	1101	High	No count	Down	No count	Up
x1 mode $CCxP = 0$	1101	Low	No count	No count	No count	No count
x1 mode CCxP=1	1101	High	No count	No count	No count	No count
x1 mode CCxP=1	1101	Low	Down	No count	Up	No count

Index Input

The counter can be reset by an Index signal coming from the encoder, indicating an absolute reference position. The Index signal must be connected to the tim_etr_in input. It can be filtered using the digital input filter.

The index functionality is enabled with the IE bit in the TIMx_ECR register. The IE bit must be set only in encoder mode, when the SMS[3:0] bitfield has the following values: 0001, 0010,011,1010,1011,1100,1101,1110,1111.

Commercially available encoders are proposed with several options for index pulse conditioning, as per the Figure 411 below:

gated with A and B: the pulse width is $1 / 4$ of one channel period,aligned with both A and $B$ edges

gated with $A$ (or gated with $B$ ): the pulse width is $1 / 2$ of one channel period,aligned with the two edges on channel A (resp. channel B)

ungated: the pulse width is up to one channel period, without any alignment to the edges

The circuitry tolerates jitter on index signal, whatever the gating mode, as show on Figure 412 below.

In ungated mode, the signal must be strictly below 2 encoder periods. If the pulse width is greater or equal to 2 encoder period, the counter is reset multiple times.

Figure 412. Jittered Index signals

MSv45766V1

The timer supports the 3 gating options identically, without any specific programming needed. It is only necessary to define on which encoder state (i.e. channel A and channel B state combination) the index must be synchronized, using the IPOS[1:0] bitfield in the TIMx_ECR register.

The Index detection event acts differently depending on counting direction to ensure symmetrical operation during speed reversal:

The counter is reset during up-counting (DIR bit $= 0$ )

The counter is set to TIMx_ARR when down counting

This allows the index to be generated on the very same mechanical angular position whatever the counting direction. The Figure 413 below shows at which position is the index generated, for a simplistic example (an encoder providing 4 edges par mechanical rotation).

Figure 413. Index generation for IPOS[1:0] = 11

The Figure 414 below presents waveforms and corresponding values for IPOS[1:0] = 11. It shows that the instant at which the counter value is forced is automatically adjusted depending on the counting direction:

Counter set to 0 when encoder state is '11' (ChA=1, ChB=1), when up-counting (DIR bit $= 0$ ).

Counter set to TIMx_ARR when exiting the '11' state, when down-counting (DIR bit $= 1$ ).

An interrupt can be issued upon index detection event.

The arrows are indicating on which transition is the index event interrupt generated.

Figure 414. Counter reading with index gated on channel A (IPOS[1:0] = 11)

The Figure 415 below presents waveforms and corresponding values for the ungated mode. The arrows are indicating on which transition is the index event generated.

Figure 420. Directional index sensitivity

Special first index event management

The FIDX bit in the TIMx_ECR register allows the Index to be taken only once, as shown on the Figure 421 below. Once the first index has arrived, any subsequent index is ignored. If needed, the circuitry can be re-armed by writing the FIDX bit to 0 and setting it again to 1 .

Note: When FIDX = 1, the index can be issued twice (IDXF flag set) if the direction changes at position 0 (index active).

Figure 421. Counter reset as function of FIDX bit setting

Index management in non-quadrature mode

The Figure 422 and Figure 423 below detail how the index is managed in directional clock mode and clock plus direction mode, when the SMS[3:0] bitfield is equal to 1010, 1011, 1100,1101.

For both of these modes, the index sensitivity is set with the IPOS[0] bit as following:

$IPOS [0] = 0$ : Index is detected on clock low level

IPOS[0] = 1: Index is detected on clock high level

The IPOS[1] bit is not-significant.

Figure 422. Index behavior in clock + direction mode, IPOS[0] = 1

Figure 423. Index behavior in directional clock mode, IPOS[0] = 1

Encoder error management

For encoder configurations where 2 quadrature signals are available, it is possible to detect transition errors. The reading on the 2 inputs corresponds to a 2-bit gray code which can be represented as a state diagram, on the Figure 424. below. A single bit is expected to change at once. An erroneous transition sets the TERRF interrupt flag in the TIMx_SR status register. A transition error interrupt is generated if the TERRIE bit is set in the TIMx_DIER register.

Figure 424. State diagram for quadrature encoded signals

For encoder having an Index signal, it is possible to detect abnormal operation resulting in an excess of pulses per revolution. An encoder with

N

pulses per revolution provides

4 xN

counts per revolution. The Index signal resets the counter every

4 xN

clock periods.

If the counter value is incremented from TIMx_ARR to 0 or decremented from 0 to TIMxARR value without any index event, this is reported as an Index position error.

The overflow threshold is programmed using the TIMx_ARR register. A 1000 lines encoder results in a counter value being between 0 and 3999 (in 4x reading mode). The overflow detection threshold must be programmed by setting TIMx_ARR = 3999 + 1 = 4000 .

Figure 426. Down-counting encode error detection

An index error sets the IERRF interrupt flag in the TIMx_SR status register. An index error interrupt is generated if the IERRIE bit is set in the TIMx_DIER register.

Functional encoder Interrupts

The following interrupts are also available in encoder mode

Direction change: any change of the counting direction in encoder mode causes the DIR bit in the TIMx_CR1 register to toggle. The direction change sets the DIRF interrupt flag in the TIMx_SR status register. A direction change interrupt is generated if the DIRIE bit is set in the TIMx_DIER register.

Index event: the Index event sets the IDXF interrupt flag in the TIMx_SR status register. An Index interrupt is generated if the IDXIE bit is set in the TIMx_DIER register.

Slave mode selection preload for run-time encoder mode update

It may be necessary to switch from one encoder mode to another during run-time. This is typically done at high-speed to decrease the Update interrupt rate, by switching from x4 to

x 2

x 1

mode,as show on the Figure 427 below.

For this purpose, the SMS[3:0] bit can be preloaded. This is enabled by setting the SMSPE enable bit in the TIMx_SMCR register. The trigger for the transfer from SMS[3:0] preload to active value can be selected with the SMSPS bit in the TIMx_SMCR register.

SMSPS = 0: the transfer is triggered by the update event (UEV) occurring when the counter overflows when upcounting, and underflows when downcounting. This mode must be used only when index is disabled (bit IE $= 0$ ).

SMSPS = 1: the transfer is triggered by the Index event.

Figure 427. Encoder mode change with preload transferred on update (SMSPS = 0)

Encoder clock output

The encoder mode operating principle is not perfectly suited for high-resolution velocity measurements, at low speed, as it requires a relatively long integration time to have a sufficient number of clock edges and a precise measurement.

At low speed, a better solution is to do an edge-to-edge clock period measurement. This can be achieved using a slave timer. The timer can output the encoder clock information on the tim_trgo output. The slave timer can then perform a period measurement and provide velocity information for each and every encoder clock edge.

This mode is enabled by setting the MMS[3:0] bitfield to 1000, in the TIMx_CR2 register. It is valid for the following SMS[3:0] values: 0001, 0010, 0011, 1010, 1011, 1100, 1101, 1110, 1111. Any other SMS[3:0] code is not allowed and may lead to unexpected behavior.

29.4.19 Direction bit output

It is possible to output a direction signal out of the timer, on the tim_oc3 and tim_oc4 output signals (copy of the DIR bit in the TIMx_CR1 register). This is achieved by setting the OC3M[3:0] or the OC4M[3:0] bit field to 1011 in the TIMx_CCMR2 register.

This feature can be used for monitoring the counting direction (or rotation direction) in encoder mode, or to have a signal indicating the up/down phases in center-aligned PWM mode.

29.4.20 UIF bit remapping

The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the update interrupt flag (UIF) into bit 31 of the timer counter register's bit 31 (TIMxCNT[31]). This is used to atomically read both the counter value and a potential roll-over condition signaled by the UIFCPY flag. It eases the calculation of angular speed by avoiding race conditions caused, for instance, by a processing shared between a background task (counter reading) and an interrupt (update interrupt).

There is no latency between the UIF and UIFCPY flag assertions.

29.4.21 Timer input XOR function

The TI1S bit in the TIM1xx_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins tim_ti1, tim_ti2 and tim_ti3.

The XOR output can be used with all the timer input functions such as trigger or input capture.

An example of this feature used to interface Hall sensors is given in Section 28.3.29: Interfacing with Hall sensors on page 1174.

29.4.22 Timers and external trigger synchronization

The TIMx Timers can be synchronized with an external trigger in several modes: Reset mode, Gated mode, Trigger mode, Reset + trigger and gated + reset modes.

Slave mode: Reset mode

The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.

In the following example, the upcounter is cleared in response to a rising edge on tim_ti1 input:

Configure the channel 1 to detect rising edges on tim_ti1. Configure the input filter duration (in this example, we do not need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so it does not need to be configured. The CC1S bits select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect rising edges only).

Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select tim_ti1 as the input source by writing TS=00101 in TIMx_SMCR register.

Start the counter by writing CEN=1 in the TIMx_CR1 register.

The counter starts counting on the internal clock, then behaves normally until tim_ti1 rising edge. When tim_ti1 rises, the counter is cleared and restarts from 0 . In the meantime, the

trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).

The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36. The delay between the rising edge on tim_ti1 and the actual reset of the counter is due to the resynchronization circuit on tim_ti1 input.

Figure 428. Control circuit in reset mode

Slave mode: Gated mode

The counter can be enabled depending on the level of a selected input.

In the following example, the upcounter counts only when tim_ti1 input is low:

Configure the channel 1 to detect low levels on tim_ti1. Configure the input filter duration (in this example, we do not need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so it does not need to be configured. The CC1S bits select the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write CC1P=1 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect low level only).

Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select tim_ti1 as the input source by writing TS=00101 in TIMx_SMCR register.

Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the counter doesn't start if $CEN = 0$ ,whatever is the trigger input level).

The counter starts counting on the internal clock as long as tim_ti1 is low and stops as soon as tim_ti1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops.

The delay between the rising edge on tim_ti1 and the actual stop of the counter is due to the resynchronization circuit on tim_ti1 input. Note: have any effect in gated mode because gated mode acts on a level and not on an edge.

Figure 429. Control circuit in gated mode

The configuration "CCxP=CCxNP=1" (detection of both rising and falling edges) does not

Slave mode: Trigger mode

The counter can start in response to an event on a selected input.

In the following example, the upcounter starts in response to a rising edge on tim_ti2 input:

Configure the channel 2 to detect rising edges on tim_ti2. Configure the input filter duration (in this example, we do not need any filter, so we keep IC2F=0000). The capture prescaler is not used for triggering, so it does not need to be configured. CC2S bits are selecting the input capture source only, CC2S=01 in TIMx_CCMR1 register. Write CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and detect low level only).

Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select tim_ti2 as the input source by writing TS=00110 in TIMx_SMCR register.

When a rising edge occurs on tim_ti2, the counter starts counting on the internal clock and the TIF flag is set.

The delay between the rising edge on tim_ti2 and the actual start of the counter is due to the resynchronization circuit on tim_ti2 input.

Figure 430. Control circuit in trigger mode

Slave mode selection preload for run-time encoder mode update

The SMS[3:0] bit can be preloaded. This is enabled by setting the SMSPE enable bit in the TIMx_SMCR register. The trigger for the transfer from SMS[3:0] preload to active value is the update event (UEV) occurring when the counter overflows.

Slave mode combined reset + trigger mode

In this case, a rising edge of the selected trigger input (tim_trgi) reinitializes the counter, generates an update of the registers, and starts the counter.

This mode is used for one-pulse mode.

Slave mode combined gated + reset mode

The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops and is reset as soon as the trigger becomes low. Both start and stop of the counter are controlled.

This mode is used to detect out-of-range PWM signal (duty cycle exceeding a maximum expected value).

Slave mode external clock mode 2 + trigger mode

The external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and encoder mode). In this case, the tim_etr_in signal is used as external clock input, and another input can be selected as trigger input when operating in reset mode, gated mode or trigger mode. It is recommended not to select tim_etr_in as tim_trgi through the TS bits of TIMx_SMCR register.

In the following example, the upcounter is incremented at each rising edge of the tim_etr_in signal as soon as a rising edge of tim_ti1 occurs:

Configure the external trigger input circuit by programming the TIMx_SMCR register as follows:

ETF = 0000: no filter

ETPS=00: prescaler disabled

ETP=0: detection of rising edges on tim_etr_in and ECE=1 to enable the external clock mode 2.

Configure the channel 1 as follows, to detect rising edges on TI:

– IC1F=0000: no filter.

The capture prescaler is not used for triggering and does not need to be configured.

CC1S=01in TIMx_CCMR1 register to select only the input capture source

CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect rising edge only).

Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select tim_ti1 as the input source by writing TS=00101 in TIMx_SMCR register.

A rising edge on tim_ti1 enables the counter and sets the TIF flag. The counter then counts on tim_etr_in rising edges.

The delay between the rising edge of the tim_etr_in signal and the actual reset of the counter is due to the resynchronization circuit on tim_etrp input.

Figure 433. Master/slave connection example with 1 channel only timers

Note: The timers with one channel only (see Figure 433) do not feature a master mode. However, the tim_oc1 output signal can serve as trigger for slave timer (see TIMx internal trigger connection table in Section 29.4.2: TIM2/TIM3/TIM4/TIM5 pins and internal signals).

The tim_oc1 signal pulse width must be programmed to be at least 2 clock cycles of the destination timer, to make sure the slave timer detects the trigger.

For instance, if the destination timer tim_ker_ck clock is 4 times slower than the source timer, the OC1 pulse width must be 8 clock cycles.

Using one timer as prescaler for another timer

For example, TIM_mstr can be configured to act as a prescaler for TIM_slv. Refer to Figure 432. To do this:

Configure TIM_mstr in master mode so that it outputs a periodic trigger signal on each update event UEV. If MMS=010 is written in the TIM_mstr_CR2 register, a rising edge is output on tim_trgo each time an update event is generated.

To connect the tim_trgo output of TIM_mstr to TIM_slv, TIM_slv must be configured in slave mode using ITR2 as internal trigger. This is selected through the TS bits in the TIM_slv_SMCR register (writing TS=00010).

Then the slave mode controller must be put in external clock mode 1 (write SMS=111 in the TIM_slv_SMCR register). This causes TIM_slv to be clocked by the rising edge of the periodic TIM_mstr trigger signal (which correspond to the TIM_mstr counter overflow).

Finally both timers must be enabled by setting their respective CEN bits (TIMx_CR1 register).

Note: If tim_ocx is selected on TIM_mstr as the trigger output (MMS=1xx), its rising edge is used to clock the counter of TIM_slv.

Using one timer to enable another timer

In this example, we control the enable of TIM_slv with the output compare 1 of TIM_mstr. Refer to Figure 432 for connections. TIM_slv counts on the divided internal clock only when tim_oc1ref of TIM_mstr is high. Both counter clock frequencies are divided by 3 by the prescaler compared to tim_ker_ck (

f_{tim_cnt_ck} = f_{tim_ker_ck} / 3

Configure TIM_mstr master mode to send its Output Compare 1 Reference (tim_oc1ref) signal as trigger output (MMS=100 in the TIM_mstr_CR2 register).

Configure the TIM_mstr tim_oc1ref waveform (TIM_mstr_CCMR1 register).

Configure TIM_slv to get the input trigger from TIM_mstr (TS=00010 in the TIM_slv_SMCR register).

Configure TIM_slv in gated mode (SMS=101 in TIM_slv_SMCR register).

Enable TIM_slv by writing '1 in the CEN bit (TIM_slv_CR1 register).

Start TIM_mstr by writing '1 in the CEN bit (TIM_mstr_CR1 register).

Note: The slave timer counter clock is not synchronized with the master timer counter clock, this mode only affects the TIM_slv counter enable signal.

Figure 434. Gating TIM_slv with tim_oc1ref of TIM_mstr

In the example in Figure 434, the TIM_slv counter and prescaler are not initialized before being started. So they start counting from their current value. It is possible to start from a given value by resetting both timers before starting TIM_mstr. Then any value can be written in the timer counters. The timers can easily be reset by software using the UG bit in the TIMx_EGR registers.

In the next example (refer to Figure 435), we synchronize TIM_mstr and TIM_sIv. TIM_mstr is the master and starts from

0

. TIM_slv is the slave and starts from

0 xE 7

. The prescaler ratio is the same for both timers. TIM_slv stops when TIM_mstr is disabled by writing ’ 0 to the CEN bit in the TIM_mstr_CR1 register:

Configure TIM_mstr master mode to send its Output Compare 1 Reference (tim_oc1ref) signal as trigger output (MMS=100 in the TIM_mstr_CR2 register).

Configure the TIM_mstr tim_oc1ref waveform (TIM_mstr_CCMR1 register).

Configure TIM_slv to get the input trigger from TIM_mstr (TS=00010 in the TIM_slv_SMCR register).

Configure TIM_slv in gated mode (SMS=101 in TIM_slv_SMCR register).

Reset TIM_mstr by writing '1 in UG bit (TIM_mstr_EGR register).

Reset TIM_slv by writing '1 in UG bit (TIM_slv_EGR register).

Initialize TIM_slv to 0xE7 by writing '0xE7' in the TIM_slv counter (TIM_slv_CNT).

Enable TIM_slv by writing '1 in the CEN bit (TIM_slv_CR1 register).

Start TIM_mstr by writing '1 in the CEN bit (TIM_mstr_CR1 register).

Stop TIM_mstr by writing ' 0 in the CEN bit (TIM_mstr_CR1 register).

Figure 435. Gating TIM_slv with Enable of TIM_mstr

Using one timer to start another timer

In this example, we set the enable of TIM_slv with the update event of TIM_mstr. Refer to Figure 432 for connections. TIM_slv starts counting from its current value (which can be non-zero) on the divided internal clock as soon as the update event is generated by

TIM_mstr. When TIM_slv receives the trigger signal its CEN bit is automatically set and the counter counts until we write ' 0 to the CEN bit in the TIM_slv_CR1 register. Both counter clock frequencies are divided by 3 by the prescaler compared to

tim

ker_ck

(f_{tim_cnt_ck} =

f_{tim_ker_ck} / 3

Configure TIM_mstr master mode to send its Update Event (UEV) as trigger output (MMS=010 in the TIM_mstr_CR2 register).

Configure the TIM_mstr period (TIM_mstr_ARR registers).

Configure TIM_slv to get the input trigger from TIM_mstr (TS=00010 in the TIM_slv_SMCR register).

Configure TIM_slv in trigger mode (SMS=110 in TIM_slv_SMCR register).

Start TIM_mstr by writing '1 in the CEN bit (TIM_mstr_CR1 register).

Figure 436. Triggering TIM_slv with update of TIM_mstr

As in the previous example, both counters can be initialized before starting counting. Figure 437 shows the behavior with the same configuration as in Figure 436 but in trigger mode (SMS=110 in the TIM_slv_SMCR register) instead of gated mode.

Figure 437. Triggering TIM_slv with Enable of TIM_mstr

Starting 2 timers synchronously in response to an external trigger

In this example, we set the enable of TIM_mstr when its tim_ti1 input rises, and the enable of TIM_slv with the enable of TIM_mstr. Refer to Figure 432 for connections. To ensure the counters are aligned, TIM_mstr must be configured in Master/Slave mode (slave with respect to tim_ti1, master with respect to TIM_slv):

Configure TIM_mstr master mode to send its Enable as trigger output (MMS=001 in the TIM_mstr_CR2 register).

Configure TIM_mstr slave mode to get the input trigger from tim_ti1 (TS=00100 in the TIM_mstr_SMCR register).

Configure TIM_mstr in trigger mode (SMS=110 in the TIM_mstr_SMCR register).

Configure the TIM_mstr in Master/Slave mode by writing MSM=1 (TIM_mstr_SMCR register).

Configure TIM_slv to get the input trigger from TIM_mstr (TS=00000 in the TIM_slv_SMCR register).

Configure TIM_slv in trigger mode (SMS=110 in the TIM_slv_SMCR register).

When a rising edge occurs on tim_ti1 (TIM_mstr), both counters starts counting synchronously on the internal clock and both TIF flags are set.

Note:

In this example both timers are initialized before starting (by setting their respective UG bits). Both counters starts from 0 , but an offset can easily be inserted between them by writing any of the counter registers (TIMx_CNT). One can see that the master/slave mode insert a delay between CNT_EN and CK_PSC on TIM_mstr.

Note: enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.

Figure 438. Triggering TIM_mstr and TIM_slv with TIM_mstr tim_ti1 input

tim_ker_ck tim_mstr_ti1 TIM_mst counter enable (CEN bit)) tim_mstr_psc_ck tim_mstr_CNT tim_mstr TIF bit TIM_slv counter enable (CEN bit) tim_slv_psc_ck tim_slv_CNT tim_slv TIF bit		Innonannah Inhannannan


		UNTITIALITY
	00


		UNTITITITITITITY
	00	01/02/03/04/05/06/07/08/09/
		MSv62380V1

The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be

29.4.24 ADC triggers

The timer can generate an ADC triggering event with various internal signals, such as reset, enable or compare events.

Note: The clock of the slave peripherals (such as timer, ADC) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.

29.4.25 DMA burst mode

The TIMx timers have the capability to generate multiple DMA requests upon a single event. The main purpose is to be able to re-program part of the timer multiple times without software overhead, but it can also be used to read several registers in a row, at regular intervals.

The DMA controller destination is unique and must point to the virtual register TIMx_DMAR. On a given timer event, the timer launches a sequence of DMA requests (burst). Each write into the TIMx_DMAR register is actually redirected to one of the timer registers.

The DBL[4:0] bits in the TIMx_DCR register set the DMA burst length. The timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers (either in half-words or in bytes).

The DBA[4:0] bits in the TIMx_DCR registers define the DMA base address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register:

Example:

0000: TIMx_CR1

00001: TIMx_CR2

00010: TIMx_SMCR

As an example, the timer DMA burst feature is used to update the contents of the CCRx registers

(x = 2, 3, 4)

upon an update event,with the DMA transferring half words into the CCRx registers.

This is done in the following steps:

Configure the corresponding DMA channel as follows:

DMA channel peripheral address is the DMAR register address

DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers.

Number of data to transfer = 3 (See note below).

Circular mode disabled.

Configure the DCR register by configuring the DBA and DBL bit fields as follows: $DBL = 3$ transfers, $DBA = 0 xE$ .

Enable the TIMx update DMA request (set the UDE bit in the DIER register).

Enable TIMx

Enable the DMA channel

This example is for the case where every CCRx register has to be updated once. If every CCRx register is to be updated twice for example, the number of data to transfer must be 6 . Let's take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and data6. The data is transferred to the CCRx registers as follows: on the first update DMA request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is transferred to CCR3 and data6 is transferred to CCR4.

Note: A null value can be written to the reserved registers.

29.4.26 TIM2/TIM3/TIM4/TIM5 DMA requests

The TIM2/TIM3/TIM4/TIM5 can generate a DMA requests, as shown in Table 283.

Table 283. DMA request

DMA request signal	DMA acronym	DMA request	Enable control bit
tim_upd_dma	TIM_UP	Update	UDE
tim_cc1_dma	TIM_CH1	Capture/compare 1	CC1DE
tim_cc2_dma	TIM_CH2	Capture/compare 2	CC2DE
tim_cc3_dma	TIM_CH3	Capture/compare 3	CC3DE
tim_cc4_dma	TIM_CH4	Capture/compare 4	CC4DE
tim_trg_dma	TIM_TRIG	Trigger	TDE

Note: Some timer’s DMA requests may not be connected to the DMA controller. Refer to the DMA section(s) for more details.

29.4.27 Debug mode

When the microcontroller enters debug mode (Cortex

^{®}

-M4 with FPU core halted),the TIMx counter can either continues to work normally or stops.

The behavior in debug mode can be programmed with a dedicated configuration bit per timer in the Debug support (DBG) module.

For more details, refer to section Debug support (DBG).

29.4.28 TIM2/TIM3/TIM4/TIM5 low-power modes

Table 284. Effect of low-power modes on TIM2/TIM3/TIM4/TIM5

Mode	Description
Sleep	No effect, peripheral is active. The interrupts can cause the device to exit from Sleep mode.
Stop	The timer operation is stopped and the register content is kept. No interrupt can be generated.
Standby	The timer is powered-down and must be reinitialized after exiting the Standby mode

29.4.29 TIM2/TIM3/TIM4/TIM5 interrupts

The TIM2/TIM3/TIM4/TIM5 can generate multiple interrupts, as shown in Table 285.

Table 285. Interrupt requests

Interrupt acronym	Interrupt event	Event flag	Enable control bit	Interrupt clear method	Exit from Sleep mode	Exit from Stop and Standby mode
TIM_UP	Update	UIF	UIE	write 0 in UIF	Yes	No
TIM_CC	Capture/compare 1	CC1IF	CC1IE	write 0 in CC1IF	Yes	No
	Capture/compare 2	CC2IF	CC21E	write 0 in CC2IF	Yes	No
	Capture/compare 3	CC31F	CC31E	write 0 in CC3IF	Yes	No
	Capture/compare 4	CC4IF	CC4IE	write 0 in CC4IF	Yes	No
TIM_TRG	Trigger	TIF	TIE	write 0 in TIF	Yes	No
TIM_DIR _IDX	Index	IDXF	IDXIE	write 0 in IDXF	Yes	No
TIM_DIR _IDX	Direction	DIRF	DIRIE	write 0 in DIRF	Yes	No
TIM_IERR	Index Error	IERRF	IERRIE	write 0 in IERRF	Yes	No
TIM_TER	Transition Error	TERRF	TERRIE	write 0 in TERRF	Yes	No

29.5 TIM2/TIM3/TIM4/TIM5 registers

Refer to Section 1.2 for a list of abbreviations used in register descriptions.

The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

29.5.1 TIMx control register 1 (TIMx_CR1)(x = 2 to 5)

Address offset: 0x000

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	DITH EN	UIFRE MAP	Res.	CKD[1:0]		ARPE	CMS[1:0]		DIR	OPM	URS	UDIS	CEN
			rw	rw		rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:13 Reserved, must be kept at reset value.

Bit 12 DITHEN: Dithering Enable

0: Dithering disabled

1: Dithering enabled

Note: The DITHEN bit can only be modified when CEN bit is reset.

Bit 11 UIFREMAP: UIF status bit remapping

0 : No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.

1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.

Bit 10 Reserved, must be kept at reset value.

Bits 9:8 CKD[1:0]: Clock division

This bit-field indicates the division ratio between the timer clock (tim_ker_ck) frequency and sampling clock used by the digital filters (tim_etr_in, tim_tix),

00:

t_{DTS} = t_{tim_\ker_ck}

01 : t_{DTS} = 2 \times t_{tim_\ker_ck}

10:

t_{DTS} = 4 \times t_{tim_\ker_ck}

11: Reserved

Bit 7 ARPE: Auto-reload preload enable

0: TIMx_ARR register is not buffered

1: TIMx_ARR register is buffered

Bits 6:5 CMS[1:0]: Center-aligned mode selection

00: Edge-aligned mode. The counter counts up or down depending on the direction bit

(DIR).

01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down.

10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up.

11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down.

Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled

(CEN = 1)

Bit 4 DIR: Direction

0 : Counter used as upcounter

1: Counter used as downcounter

Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder

mode.

Bit 3 OPM: One-pulse mode

0 : Counter is not stopped at update event

1: Counter stops counting at the next update event (clearing the bit CEN)

Bit 2 URS: Update request source

This bit is set and cleared by software to select the UEV event sources.

0: Any of the following events generate an update interrupt or DMA request if enabled.

These events can be:

Counter overflow/underflow

Setting the UG bit

Update generation through the slave mode controller

1: Only counter overflow/underflow generates an update interrupt or DMA request if

enabled.

Bit 1 UDIS: Update disable

This bit is set and cleared by software to enable/disable UEV event generation.

0: UEV enabled. The Update (UEV) event is generated by one of the following events:

Counter overflow/underflow

Setting the UG bit

Update generation through the slave mode controller

Buffered registers are then loaded with their preload values.

1: UEV disabled. The Update event is not generated, shadow registers keep their value

(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is

set or if a hardware reset is received from the slave mode controller.

Bit 0 CEN: Counter enable

0: Counter disabled

1: Counter enabled

Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.

CEN is cleared automatically in one-pulse mode, when an update event occurs.

29.5.2 TIMx control register 2 (TIMx_CR2)(x = 2 to 5)

Address offset: 0x004

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	MMS[3]	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
						rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	TI1S	MMS[2:0]			CCDS	Res.	Res.	Res.
								rw	rw	rw	rw	rw

Bits 31:26 Reserved, must be kept at reset value.

Bits 24:8 Reserved, must be kept at reset value.

Bit 7 TI1S: tim_ti1 selection

0: The tim_ti1_in[15:0] multiplexer output is to tim_ti1 input

1: The tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input. See also Section 28.3.29: Interfacing with Hall sensors on page 1174.

Bits 25, 6, 5, 4 MMS[3:0]: Master mode selection

These bits are used to select the information to be sent in master mode to slave timers for synchronization (tim_trgo). The combination is as follows:

0000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on tim_trgo is delayed compared to the actual reset.

0001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode.

When the Counter Enable signal is controlled by the trigger input, there is a delay on tim_trgo, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).

0010: Update - The update event is selected as trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer.

0011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo).

0100: Compare - tim_oc1refc signal is used as trigger output (tim_trgo)

0101: Compare - tim_oc2refc signal is used as trigger output (tim_trgo)

0110: Compare - tim_oc3refc signal is used as trigger output (tim_trgo)

0111: Compare - tim_oc4refc signal is used as trigger output (tim_trgo)

1000: Encoder Clock output - The encoder clock signal is used as trigger output (tim_trgo). This code is valid for the following SMS[3:0] values: 0001, 0010, 0011, 1010, 1011,

1100, 1101, 1110, 1111

. Any other SMS[3:0] code is not allowed and may lead to unexpected behavior.

Others: Reserved

Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

Bit 3 CCDS: Capture/compare DMA selection

0: CCx DMA request sent when CCx event occurs

1: CCx DMA requests sent when update event occurs

Bits 2:0 Reserved, must be kept at reset value.

29.5.3 TIMx slave mode control register (TIMx_SMCR)(x = 2 to 5)

Address offset: 0x008

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	SMSPS	SMSPE	Res.	Res.	TS[4:3]		Res.	Res.	Res.	SMS[3]
						rw	rw			rw	rw				rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP	ECE	ETPS[1:0]		ETF[3:0]				MSM	TS[2:0]			occs	SMS[2:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 SMSPS: SMS preload source

This bit selects whether the events that triggers the SMS[3:0] bitfield transfer from preload to active

0 : The transfer is triggered by the Timer's Update event

1: The transfer is triggered by the Index event

Bit 24 SMSPE: SMS preload enable

This bit selects whether the SMS[3:0] bitfield is preloaded

0: SMS[3:0] bitfield is not preloaded

1: SMS[3:0] preload is enabled

Bits 23:22 Reserved, must be kept at reset value.

Bits 19:17 Reserved, must be kept at reset value.

Bit 15 ETP: External trigger polarity

This bit selects whether tim_etr_in or tim_etr_in is used for trigger operations

0: tim_etr_in is non-inverted, active at high level or rising edge

1: tim_etr_in is inverted, active at low level or falling edge

Bit 14 ECE: External clock enable

This bit enables External clock mode 2.

0 : External clock mode 2 disabled

1: External clock mode 2 enabled. The counter is clocked by any active edge on the tim_etrf signal.

Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with tim_trgi connected to tim_etrf (SMS=111 and TS=00111).

It is possible to simultaneously use external clock mode 2 with the following slave

modes: reset mode, gated mode and trigger mode. Nevertheless, tim_trgi must not be

connected to tim_etrf in this case (TS bits must not be 00111).

If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is tim_etrf.

Bits 13:12 ETPS[1:0]: External trigger prescaler

External trigger signal tim_etrp frequency must be at most

1 / 4

of tim_ker_ck frequency. A prescaler can be enabled to reduce tim_etrp frequency. It is useful when inputting fast external clocks on tim_etr_in.

00: Prescaler OFF

01: tim_etrp frequency divided by 2

10: tim_etrp frequency divided by 4

11: tim_etrp frequency divided by 8

Bits 11:8 ETF[3:0]: External trigger filter

This bit-field then defines the frequency used to sample tim_etrp signal and the length of the digital filter applied to tim_etrp. The digital filter is made of an event counter in which

N

consecutive events are needed to validate a transition on the output:

0000: No filter,sampling is done at

f_{DTS}

0001:

f_{SAMPLING} = f_{tim_ker_ck}, N = 2

0010:

f_{SAMPLING} = f_{tim_ker_ck}, N = 4

0011:

f_{SAMPLING} = f_{tim_ker_ck}, N = 8

0100:

f_{SAMPLING} = f_{DTS} / 2, N = 6

0101:

f_{SAMPLING} = f_{DTS} / 2, N = 8

0110:

f_{SAMPLING} = f_{DTS} / 4, N = 6

0111:

f_{SAMPLING} = f_{DTS} / 4, N = 8

1000:

f_{SAMPLING} = f_{DTS} / 8, N = 6

1001:

f_{SAMPLING} = f_{DTS} / 8, N = 8

1010:

f_{SAMPLING} = f_{DTS} / 16, N = 5

1011:

f_{SAMPLING} = f_{DTS} / 16, N = 6

1100:

f_{SAMPLING} = f_{DTS} / 16, N = 8

1101:

f_{SAMPLING} = f_{DTS} / 32, N = 5

1110:

f_{SAMPLING} = f_{DTS} / 32, N = 6

1111:

f_{SAMPLING} = f_{DTS} / 32, N = 8

Bit 7 MSM: Master/Slave mode

0 : No action

1: The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). It is useful if we want to synchronize several timers on a single external event.

Bits 21, 20, 6, 5, 4 TS[4:0]: Trigger selection

This bit-field selects the trigger input to be used to synchronize the counter.

00000: Internal trigger 0 (tim_itr0)

00001: Internal trigger 1 (tim_itr1)

00010: Internal trigger 2 (tim_itr2)

00011: Internal trigger 3 (tim_itr3)

00100: tim_ti1 edge detector (tim_ti1f_ed)

00101: Filtered timer input 1 (tim_ti1fp1)

00110: Filtered timer input 2 (tim_ti2fp2)

00111: External trigger input (tim_etrf)

01000: Internal trigger 4 (tim_itr4)

01001: Internal trigger 5 (tim_itr5)

01010: Internal trigger 6 (tim_itr6)

01011: Internal trigger 7 (tim_itr7)

01100: Internal trigger 8 (tim_itr8)

01101: Internal trigger 9 (tim_itr9)

01110: Internal trigger 10 (tim_itr10)

01111: Internal trigger 11 (tim_itr11)

10000: Internal trigger 12 (tim_itr12)

10001: Internal trigger 13 (tim_itr13)

10010: Internal trigger 14 (tim_itr14)

10011: Internal trigger 15 (tim_itr15)

Others: Reserved

See Section 29.4.2: TIM2/TIM3/TIM4/TIM5 pins and internal signals for product specific

implementation details.

Note: These bits must be changed only when they are not used (for example when SMS = 000) to avoid wrong edge detections at the transition.

Bit 3 OCCS: OCREF clear selection

This bit is used to select the OCREF clear source

0: tim_ocref_clr_int is connected to the tim_ocref_clr input

1: tim_ocref_clr_int is connected to tim_etrf

Note: If the OCREF clear selection feature is not supported, this bit is reserved and forced by hardware to '0'. Section 29.3: TIM2/TIM3/TIM4/TIM5 implementation.

Bits $16, 2, 1, 0$ SMS[3:0]: Slave mode selection

When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (refer to ETP bit in TIMx_SMCR for tim_etr_in and

CCxP/CCxNP bits in TIMx_CCER register for tim_ti1fp1 and tim_ti2fp2).

0000: Slave mode disabled - if CEN = '1 then the prescaler is clocked directly by the internal clock.

0001: Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level.

0010: Encoder mode 2 - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level.

0011: Encoder mode 3 - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input.

0100: Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers.

0101: Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.

0110: Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). Only the start of the counter is controlled.

0111: External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter.

1000: Combined reset + trigger mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter, generates an update of the registers and starts the counter.

1001: Combined gated + reset mode - The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops and is reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.

1010: Encoder mode: Clock plus direction, x2 mode.

1011: Encoder mode: Clock plus direction, x1 mode, tim_ti2fp2 edge sensitivity is set by CC2P.

1100: Encoder mode: Directional Clock, x2 mode.

1101: Encoder mode: Directional Clock, x1 mode, tim_ti1fp1 and tim_ti2fp2 edge sensitivity is set by CC1P and CC2P.

1110: Quadrature encoder mode: x1 mode, counting on tim_ti1fp1 edges only, edge sensitivity is set by CC1P.

1111: Quadrature encoder mode: x1 mode, counting on tim_ti2fp2 edges only, edge sensitivity is set by CC2P.

Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal.

Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.

29.5.4 TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 5)

Address offset: 0x00C

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	TERR IE	IERR IE	DIRIE	IDXIE	Res.	Res.	Res.	Res.
								rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	TDE	Res.	CC4DE	CC3DE	CC2DE	CC1DE	UDE	Res.	TIE	Res.	CC41E	CC31E	CC2IE	CC1IE	UIE
	rw		rw	rw	rw	rw	rw		rw		rw	rw	rw	rw	rw

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 TERRIE: Transition error interrupt enable

0: Transition error interrupt disabled

1: Transition error interrupt enabled

Bit 22 IERRIE: Index error interrupt enable 0 : Index error interrupt disabled 1: Index error interrupt enabled Bit 21 DIRIE: Direction change interrupt enable 0: Direction change interrupt disabled 1: Direction change interrupt enabled

Bit 20 IDXIE: Index interrupt enable 0 : Index interrupt disabled 1: Index interrupt enabled

Bits 19:15 Reserved, must be kept at reset value.

Bit 14 TDE: Trigger DMA request enable

0: Trigger DMA request disabled. 1: Trigger DMA request enabled.

Bit 13 Reserved, must be kept at reset value.

Bit 12 CC4DE: Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled. 1: CC4 DMA request enabled.

Bit 11 CC3DE: Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled. 1: CC3 DMA request enabled.

Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled.

1: CC2 DMA request enabled.

Bit 9 CC1DE: Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled. 1: CC1 DMA request enabled.

Bit 8 UDE: Update DMA request enable

0: Update DMA request disabled.

1: Update DMA request enabled.

Bit 7 Reserved, must be kept at reset value.

Bit 6 TIE: Trigger interrupt enable

0: Trigger interrupt disabled.

1: Trigger interrupt enabled.

Bit 5 Reserved, must be kept at reset value.

Bit 4 CC4IE: Capture/Compare 4 interrupt enable

0: CC4 interrupt disabled.

1: CC4 interrupt enabled.

Bit 3 CC3IE: Capture/Compare 3 interrupt enable

0: CC3 interrupt disabled.

1: CC3 interrupt enabled.

Bit 2 CC2IE: Capture/Compare 2 interrupt enable

0: CC2 interrupt disabled.

1: CC2 interrupt enabled.

Bit 1 CC1IE: Capture/Compare 1 interrupt enable

0: CC1 interrupt disabled.

1: CC1 interrupt enabled.

Bit 0 UIE: Update interrupt enable

0: Update interrupt disabled.

1: Update interrupt enabled.

29.5.5 TIMx status register (TIMx_SR)(x = 2 to 5)

Address offset: 0x010 Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res	Res.	Res.	Res.	Res.	TERRF	IERRF	DIRF	IDXF	Res.	Res.	Res.	Res.
								rc_w0	rc_w0	rc_w0	rc_w0
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	CC40F	CC3OF	CC20F	CC10F	Res.	Res.	TIF	Res.	CC4IF	CC31F	CC21F	CC1IF	UIF
			rc_w0	rc_w0	rc_w0	rc_w0			rc_w0		rc_w0	rc_w0	rc_w0	rc_w0	rc_w0

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 TERRF: Transition error interrupt flag

This flag is set by hardware when a transition error is detected in encoder mode. It is cleared by software by writing it to ’ 0 ’.

0 : No encoder transition error has been detected.

1: An encoder transition error has been detected

Bit 22 IERRF: Index error interrupt flag

This flag is set by hardware when an index error is detected. It is cleared by software by writing it to ' 0 '.

0 : No index error has been detected.

1: An index error has been detected

Bit 21 DIRF: Direction change interrupt flag

This flag is set by hardware when the direction changes in encoder mode (DIR bit value in

TIMx_CR is changing). It is cleared by software by writing it to ' 0 '.

0 : No direction change

1: Direction change

Bit 20 IDXF: Index interrupt flag

This flag is set by hardware when an index event is detected. It is cleared by software by writing it to ' 0 '.

0 : No index event occurred.

1: An index event has occurred

Bits 19:13 Reserved, must be kept at reset value.

Bit 12 CC4OF: Capture/Compare 4 overcapture flag

refer to CC10F description

Bit 11 CC3OF: Capture/Compare 3 overcapture flag

refer to CC10F description

Bit 10 CC2OF: Capture/compare 2 overcapture flag

refer to CC1OF description

Bit

9

CC10F: Capture/Compare 1 overcapture flag

This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ’ 0 ’.

0 : No overcapture has been detected.

1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set

Bits 8:7 Reserved, must be kept at reset value.

Bit 6 TIF: Trigger interrupt flag

This flag is set by hardware on the TRG trigger event (active edge detected on tim_trgi input) when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 0 : No trigger event occurred. 1: Trigger interrupt pending.

Bit 5 Reserved, must be kept at reset value.

Bit 4 CC4IF: Capture/Compare 4 interrupt flag Refer to CC1IF description

Bit

3

CC3IF: Capture/Compare 3 interrupt flag Refer to CC1IF description

Bit 2 CC2IF: Capture/Compare 2 interrupt flag Refer to CC1IF description

Bit 1 CC1IF: Capture/compare 1 interrupt flag

This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only).

0 : No compare match / No input capture occurred

1: A compare match or an input capture occurred

If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in downcounting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description.

If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER).

Bit 0 UIF: Update interrupt flag

This bit is set by hardware on an update event. It is cleared by software.

0 : No update occurred

1: Update interrupt pending. This bit is set by hardware when the registers are updated:

At overflow or underflow and if UDIS=0 in the TIMx_CR1 register.

When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register.

When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS

= 0

and UDIS

= 0

in the TIMx_CR1 register.

29.5.6 TIMx event generation register (TIMx_EGR)(x = 2 to 5)

Address offset: 0x014

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	TG	Res.	CC4G	CC3G	CC2G	CC1G	UG
									w		w	w	w	w	w

Bits 15:7 Reserved, must be kept at reset value.

Bit 6 TG: Trigger generation

This bit is set by software in order to generate an event, it is automatically cleared by hardware.

0 : No action

1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

Bit 5 Reserved, must be kept at reset value.

Bit 4 CC4G: Capture/compare 4 generation Refer to CC1G description

Bit 3 CC3G: Capture/compare 3 generation

Refer to CC1G description

Bit 2 CC2G: Capture/compare 2 generation

Refer to CC1G description

Bit 1 CC1G: Capture/compare 1 generation

This bit is set by software in order to generate an event, it is automatically cleared by

hardware.

0 : No action

1: A capture/compare event is generated on channel 1:

If channel CC1 is configured as output:

CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.

If channel CC1 is configured as input:

The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC10F flag is set if the CC1IF flag was already high.

Bit 0 UG: Update generation

This bit can be set by software, it is automatically cleared by hardware.

0 : No action

1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if

DIR = 0

(upcounting),else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting).

29.5.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 5)

Address offset: 0x018

Reset value: 0x00000000

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (for example channel 1 in input capture mode and channel 2 in output compare mode).

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC2F[3:0]				IC2PSC[1:0]		CC2S[1:0]		IC1F[3:0]				IC1PSC[1:0]		CC1S[1:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Input capture mode

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:12 IC2F[3:0]: Input capture 2 filter

Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler

Bits 9:8 CC2S[1:0]: Capture/compare 2 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC2 channel is configured as output.

01: CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2.

10: CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1.

11: CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working

only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).

Bits 7:4 IC1F[3:0]: Input capture 1 filter

This bit-field defines the frequency used to sample tim_ti1 input and the length of the digital filter applied to tim_ti1. The digital filter is made of an event counter in which

N

consecutive events are needed to validate a transition on the output:

0000: No filter,sampling is done at

f_{DTS}

0001:

f_{SAMPLING} = f_{tim_ker_ck}, N = 2

0010:

f_{SAMPLING} = f_{tim_ker_ck}, N = 4

0011:

f_{SAMPLING} = f_{tim_ker_ck}, N = 8

0100 : f_{SAMPLING} = f_{DTS} / 2, N = 6

0101:

f_{SAMPLING} = f_{DTS} / 2, N = 8

0110 : f_{SAMPLING} = f_{DTS} / 4, N = 6

0111:

f_{SAMPLING} = f_{DTS} / 4, N = 8

1000:

f_{SAMPLING} = f_{DTS} / 8, N = 6

1001 : f_{SAMPLING} = f_{DTS} / 8, N = 8

1010:

f_{SAMPLING} = f_{DTS} / 16, N = 5

1011:

f_{SAMPLING} = f_{DTS} / 16, N = 6

1100:

f_{SAMPLING} = f_{DTS} / 16, N = 8

1101:

f_{SAMPLING} = f_{DTS} / 32, N = 5

1110:

f_{SAMPLING} = f_{DTS} / 32, N = 6

1111:

f_{SAMPLING} = f_{DTS} / 32, N = 8

Bits 3:2 IC1PSC[1:0]: Input capture 1 prescaler

This bit-field defines the ratio of the prescaler acting on CC1 input (tim_ic1). The prescaler is reset as soon as CC1E=0 (TIMx_CCER register).

00 : no prescaler, capture is done each time an edge is detected on the capture input

01: capture is done once every 2 events

10: capture is done once every 4 events

11: capture is done once every 8 events

Bits 1:0 CC1S[1:0]: Capture/Compare 1 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC1 channel is configured as output

01: CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1

10: CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2

11: CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working

only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

29.5.8 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 2 to 5)

Address offset: 0x018

Reset value: 0x00000000

The same register can be used for output compare mode (this section) or for input capture mode (previous section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (for example channel 1 in input capture mode and channel 2 in output compare mode).

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	OC2M [3]	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OC1M [3]
							rw								rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC2CE	OC2M[2:0]			OC2PE	OC2FE	CC2S[1:0]		OC1CE	OC1M[2:0]			OC1PE	OC1FE	CC1S[1:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Output compare mode

Bits 31:25 Reserved, must be kept at reset value.

Bits 23:17 Reserved, must be kept at reset value.

Bit 15 OC2CE: Output compare 2 clear enable

Bits 24, 14:12 OC2M[3:0]: Output compare 2 mode

refer to OC1M description on bits 6:4

Bit 11 OC2PE: Output compare 2 preload enable

Bit 10 OC2FE: Output compare 2 fast enable

Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC2 channel is configured as output

01: CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2

10: CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1

11: CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working

only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)

Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).

Bit 7 OC1CE: Output compare 1 clear enable

0: tim_oc1ref is not affected by the tim_ocref_clr_int input

1: tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int input

Bits 16, 6:4 OC1M[3:0]: Output compare 1 mode

These bits define the behavior of the output reference signal tim_oc1ref from which tim_oc1 is derived. tim_oc1ref is active high whereas tim_oc1 active level depends on CC1P bit.

0000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. This mode can be used when the timer serves as a software timebase. When the frozen mode is enabled during timer operation, the ouput keeps the state (active or inactive) it had before entering the frozen state.

0001: Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).

0010: Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).

0011: Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1.

0100: Force inactive level - tim_oc1ref is forced low.

0101: Force active level - tim_oc1ref is forced high.

0110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTTIMx_CCR1 else active (tim_oc1ref=1).

0111: PWM mode 2 - In upcounting, channel 1 is inactive as long as

TIMx_CNTTIMx_CCR1 else inactive.

1000: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update.

1001: Retriggerable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update.

1010: Reserved.

1011: Reserved.

1100: Combined PWM mode 1 - tim_oc1ref has the same behavior as in PWM mode 1. tim_oc1refc is the logical OR between tim_oc1ref and tim_oc2ref.

1101: Combined PWM mode 2 - tim_oc1ref has the same behavior as in PWM mode 2. tim_oc1refc is the logical AND between tim_oc1ref and tim_oc2ref.

1110: Asymmetric PWM mode 1 - tim_oc1ref has the same behavior as in PWM mode 1. tim_oc1refc outputs tim_oc1ref when the counter is counting up, tim_oc2ref when it is counting down.

1111: Asymmetric PWM mode 2 - tim_oc1ref has the same behavior as in PWM mode 2. tim_oc1refc outputs tim_oc1ref when the counter is counting up, tim_oc2ref when it is counting down.

Note: In PWM mode, the OCREF level changes when the result of the comparison changes, when the output compare mode switches from "frozen" mode to "PWM" mode and when the output compare mode switches from "force active/inactive" mode to "PWM" mode. Bit 3 OC1PE: Output compare 1 preload enable

0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.

1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.

Bit 2 OC1FE: Output compare 1 fast enable

This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger.

0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles.

1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode.

Bits 1:0 CC1S[1:0]: Capture/Compare 1 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC1 channel is configured as output.

01: CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1.

10: CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2.

11: CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

29.5.9 TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 5)

Address offset: 0x01C

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC4F[3:0]				IC4PSC[1:0]		CC4S[1:0]		IC3F[3:0]				IC3PSC[1:0]		CC3S[1:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Input capture mode

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:12 IC4F[3:0]: Input capture 4 filter

Bits 11:10 IC4PSC[1:0]: Input capture 4 prescaler

Bits 9:8 CC4S[1:0]: Capture/Compare 4 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC4 channel is configured as output

01: CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4

10: CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3

11: CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working

only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).

Bits 7:4 IC3F[3:0]: Input capture 3 filter

Bits 3:2 IC3PSC[1:0]: Input capture 3 prescaler

Bits 1:0 CC3S[1:0]: Capture/Compare 3 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC3 channel is configured as output

01: CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3

10: CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4

11: CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working

only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).

29.5.10 TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)(x = 2 to 5)

Address offset: 0x01C

Reset value: 0x00000000

The same register can be used for output compare mode (this section) or for input capture mode (previous section). The direction of a channel is defined by configuring the

corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (for example channel 1 in input capture mode and channel 2 in output compare mode).

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res	Res.	Res.	Res.	Res.	Res.	Res.	OC4M [3]	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OC3M [3]
							rw								rw

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC4CE	OC4M[2:0]			OC4PE	OC4FE	CC4S[1:0]		OC3CE	OC3M[2:0]			OC3PE	OC3FE	CC3S[1:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Output compare mode

Bits 31:25 Reserved, must be kept at reset value.

Bits 23:17 Reserved, must be kept at reset value.

Bit 15 OC4CE: Output compare 4 clear enable Bits 24, 14:12 OC4M[3:0]: Output compare 4 mode Refer to OC3M[3:0]

Bit 11 OC4PE: Output compare 4 preload enable

Bit 10 OC4FE: Output compare 4 fast enable

Bits 16, 6:4 OC3M[3:0]: Output compare 3 mode

These bits define the behavior of the output reference signal tim_oc3ref from which tim_oc3 and tim_oc3n are derived. tim_oc3ref is active high whereas tim_oc3 and tim_oc3n active level depends on CC3P and CC3NP bits.

0000: Frozen - The comparison between the output compare register TIMx_CCR3 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base).

0001: Set channel 3 to active level on match. tim_oc3ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 3 (TIMx_CCR3).

0010: Set channel 3 to inactive level on match. tim_oc3ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 3 (TIMx_CCR3).

0011: Toggle - tim_oc3ref toggles when TIMx_CNT=TIMx_CCR3.

0100: Force inactive level - tim_oc3ref is forced low.

0101: Force active level - tim_oc3ref is forced high.

0110: PWM mode 1 - In upcounting, channel 3 is active as long as TIMx_CNTTIMx_CCR3 else active (tim_oc3ref='1').

0111: PWM mode 2 - In upcounting, channel 3 is inactive as long as

TIMx_CNTTIMx_CCR3 else inactive.

1000: Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update.

1001: Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update.

1010: Pulse on compare: a pulse is generated on tim_oc3ref upon CCR3 match event, as per PWPRSC[2:0] and PW[7:0] bitfields programming in TIMxECR.

1011: Direction output. The tim_oc3ref signal is overridden by a copy of the DIR bit.

1100: Combined PWM mode 1 - tim_oc3ref has the same behavior as in PWM mode 1. tim_oc3refc is the logical OR between tim_oc3ref and tim_oc4ref.

1101: Combined PWM mode 2 - tim_oc3ref has the same behavior as in PWM mode 2. tim_oc3refc is the logical AND between tim_oc3ref and tim_oc4ref.

1110: Asymmetric PWM mode 1 - tim_oc3ref has the same behavior as in PWM mode 1. tim_oc3refc outputs tim_oc3ref when the counter is counting up, tim_oc4ref when it is counting down.

1111: Asymmetric PWM mode 2 - tim_oc3ref has the same behavior as in PWM mode 2. tim_oc3refc outputs tim_oc3ref when the counter is counting up, tim_oc4ref when it is counting down.

Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).

Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from "frozen" mode to "PWM" mode.

On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC3M active bits take the new value from the preloaded bits only when a COM event is generated.

Bit 3 OC3PE: Output compare 3 preload enable

Bit 2 OC3FE: Output compare 3 fast enable

Bits 1:0 CC3S[1:0]: Capture/Compare 3 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC3 channel is configured as output

01: CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3

10: CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4

11: CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working

only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).

29.5.11 TIMx capture/compare enable register (TIMx_CCER)(x = 2 to 5)

Address offset: 0x020

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC4NP	Res	CC4P	CC4E	CC3NP	Res	CC3P	CC3E	CC2NP	Res.	CC2P	CC2E	CC1NP	Res.	CC1P	CC1E
rw		rw	rw	rw		rw	rw	rw		rw	rw	rw		rw	rw

Bit 15 CC4NP: Capture/Compare 4 output Polarity. Refer to CC1NP description

Bit 14 Reserved, must be kept at reset value.

Bit 13 CC4P: Capture/Compare 4 output Polarity. Refer to CC1P description

Bit 12 CC4E: Capture/Compare 4 output enable. refer to CC1E description

Bit 11 CC3NP: Capture/Compare 3 output Polarity. Refer to CC1NP description

Bit 10 Reserved, must be kept at reset value.

Bit

9

CC3P: Capture/Compare 3 output Polarity. Refer to CC1P description

Bit 8 CC3E: Capture/Compare 3 output enable. Refer to CC1E description

Bit 7 CC2NP: Capture/Compare 2 output Polarity. Refer to CC1NP description

Bit 6 Reserved, must be kept at reset value.

Bit

5

CC2P: Capture/Compare 2 output Polarity. refer to CC1P description

Bit 4 CC2E: Capture/Compare 2 output enable. Refer to CC1E description

Bit 3 CC1NP: Capture/Compare 1 output Polarity.

CC1 channel configured as output: CC1NP must be kept cleared in this case.

CC1 channel configured as input: This bit is used in conjunction with CC1P to define tim_ti1fp1/tim_ti2fp1 polarity. refer to CC1P description.

Bit 2 Reserved, must be kept at reset value.

Bit 1 CC1P: Capture/Compare 1 output Polarity.

0: OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) 1: OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations.

CC 1 NP = 0, CC 1 P = 0

: non-inverted/rising edge. The circuit is sensitive to TlxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode).

CC 1 NP = 0, CC 1 P = 1

: inverted/falling edge. The circuit is sensitive to TlxFP1 falling edge

(capture or trigger operations in reset, external clock or trigger mode),

TlxFP1 is inverted (trigger operation in gated mode or encoder mode).

CC 1 NP = 1, CC 1 P = 1

: non-inverted/both edges. The circuit is sensitive to both TlxFP1 rising

and falling edges (capture or trigger operations in reset, external clock

or trigger mode), TIxFP1is not inverted (trigger operation in gated

mode). This configuration must not be used in encoder mode.

CC 1 NP = 1, CC 1 P = 0

: this configuration is reserved,it must not be used.

Bit 0 CC1E: Capture/Compare 1 output enable.

0: Capture mode disabled / OC1 is not active

1: Capture mode enabled / OC1 signal is output on the corresponding output pin

Table 286. Output control bit for standard tim_ocx channels

CCxE bit	tim_ocx output state
0	Output disabled (not driven by the timer: Hi-Z)
1	Output enabled (tim_ocx = tim_ocxref + Polarity)

Note:

The state of the external IO pins connected to the standard tim_ocx channels depends only on the GPIO registers when

C C x E = 0

29.5.12 TIMx counter (TIMx_CNT)(x = 3, 4)

Address offset: 0x024

Reset value: 0x00000000

Bit 31 UIFCPY: Value depends on IUFREMAP in TIMx_CR1.

If UIFREMAP

= 0

Reserved

If UIFREMAP = 1

UIFCPY: UIF Copy

This bit is a read-only copy of the UIF bit of the TIMx_ISR register

Bits 30:16 Reserved, must be kept at reset value.

Bits 15:0 CNT[15:0]: Counter value'

Non-dithering mode (DITHEN = 0)

The register holds the counter value.

Dithering mode (DITHEN = 1)

The register holds the non-dithered part in CNT[15:0]. The fractional part is not available.

29.5.13 TIMx counter (TIMx_CNT)(x = 2, 5)

Address offset: 0x024

Reset value: 0x00000000

rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

CNT[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bit 31 UIFCPY_CNT[31]: Value depends on IUFREMAP in TIMx_CR1.

If UIFREMAP

= 0

CNT[31]: Most significant bit of counter value

If UIFREMAP

= 1

UIFCPY: UIF Copy

This bit is a read-only copy of the UIF bit of the TIMx_ISR register

Bits 30:0 CNT[30:0]: Least significant part of counter value

Non-dithering mode (DITHEN = 0)

The register holds the counter value.

Dithering mode (DITHEN = 1)

The register holds the non-dithered part in CNT[30:0]. The fractional part is not available.

29.5.14 TIMx prescaler (TIMx_PSC)(x = 2 to 5)

Address offset: 0x028

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0 PSC[15:0]: Prescaler value

The counter clock frequency tim_cnt_ck is equal to

f_{tim_psc_ck} / (P S C [15 : 0] + 1)

. PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in "reset mode").

29.5.15 TIMx auto-reload register (TIMx_ARR)(x = 3, 4)

Address offset:

0 \times 02 C

Reset value: 0x0000 FFFF

ANN[10.0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:0 ARR[19:0]: Low Auto-reload value

ARR is the value to be loaded in the actual auto-reload register.

Refer to the Section 29.4.3: Time-base unit on page 1243 for more details about ARR

update and behavior.

The counter is blocked while the auto-reload value is null.

Non-dithering mode (DITHEN = 0)

The register holds the auto-reload value.

Dithering mode (DITHEN = 1)

The register holds the integer part in ARR[19:4]. The ARR[3:0] bitfield contains the dithered part.

29.5.16 TIMx auto-reload register (TIMx_ARR)(x = 2, 5)

Address offset: 0x02C

Reset value: 0xFFFF FFFF 29.5.17 TIMx capture/compare register 1 (TIMx_CCR1)(x = 3, 4)

							Analysis
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:0 ARR[31:0]: Auto-reload value

ARR is the value to be loaded in the actual auto-reload register.

Refer to the Section 29.4.3: Time-base unit on page 1243 for more details about ARR

update and behavior.

The counter is blocked while the auto-reload value is null.

Non-dithering mode (DITHEN = 0)

The register holds the auto-reload value.

Dithering mode (DITHEN = 1)

The register holds the integer part in ARR[31:4]. The ARR[3:0] bitfield contains the dithered part.

Address offset: 0x034

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	CCR1[19:16]
												rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:0 CCR1[19:0]: Capture/compare 1 value

If channel CC1 is configured as output:

CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit

OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on tim_oc1 output.

Non-dithering mode (DITHEN = 0)

The register holds the compare value in CCR1[15:0]. The CCR1[19:16] bits are reset. Dithering mode (DITHEN = 1)

The register holds the integer part in CCR1[19:4]. The CCR1[3:0] bitfield contains the dithered part.

If channel CC1 is configured as input:

CCR1 is the counter value transferred by the last input capture 1 event (tim_ic1). The

TIMx_CCR1 register is read-only and cannot be programmed.

Non-dithering mode (DITHEN = 0)

The CCR1[15:0] bits hold the capture value. The CCR1[19:16] bits are reserved.

Dithering mode (DITHEN = 1)

The register holds the capture in CCR1[19:0]. The CCR1[3:0] bits are reset.

29.5.18 TIMx capture/compare register 1 (TIMx_CCR1)(x = 2, 5)

Address offset: 0x034

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR1[31:16]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:0 CCR1[31:0]: Capture/compare 1 value If channel CC1 is configured as output:

CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on tim_oc1 output.

Non-dithering mode (DITHEN = 0)

The register holds the compare value.

Dithering mode (DITHEN = 1)

The register holds the integer part in CCR1[31:4]. The CCR1[3:0] bitfield contains the dithered part.

If channel CC1 is configured as input:

CCR1 is the counter value transferred by the last input capture 1 event (tim_ic1). The

TIMx_CCR1 register is read-only and cannot be programmed.

Non-dithering mode (DITHEN = 0)

The register holds the capture value.

Dithering mode (DITHEN = 1)

The register holds the capture in CCR1[31:0]. The CCR1[3:0] bits are reset.

29.5.19 TIMx capture/compare register 2 (TIMx_CCR2)(x = 3, 4)

Address offset: 0x038

Reset value: 0x00000000

CON2[10.0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:0 CCR2[19:0]: Capture/compare 1 value

If channel CC2 is configured as output:

CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on tim_oc2 output.

Non-dithering mode (DITHEN = 0)

The register holds the compare value in CCR2[15:0]. The CCR2[19:16] bits are reset.

Dithering mode (DITHEN = 1)

The register holds the integer part in CCR2[19:4]. The CCR2[3:0] bitfield contains the dithered part.

If channel CC2 is configured as input:

CCR2 is the counter value transferred by the last input capture 2 event (tim_ic2). The TIMx_CCR2 register is read-only and cannot be programmed.

Non-dithering mode (DITHEN = 0)

The CCR2[15:0] bits hold the capture value. The CCR2[19:16] bits are reserved.

Dithering mode (DITHEN = 1)

The register holds the capture in CCR2[19:0]. The CCR2[3:0] bits are reset.

29.5.20 TIMx capture/compare register 2 (TIMx_CCR2)(x = 2, 5)

Address offset: 0x038

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR2[31:16]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR2[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:0 CCR2[31:0]: Capture/compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on tim_oc2 output.

Non-dithering mode (DITHEN = 0)

The register holds the compare value.

Dithering mode (DITHEN = 1)

The register holds the integer part in CCR2[31:4]. The CCR2[3:0] bitfield contains the

dithered part.

If channel CC2 is configured as input:

CCR2 is the counter value transferred by the last input capture 2 event (tim_ic2). The

TIMx_CCR2 register is read-only and cannot be programmed.

Non-dithering mode (DITHEN = 0)

The register holds the capture value.

Dithering mode (DITHEN = 1)

The register holds the capture in CCR2[31:0]. The CCR2[3:0] bits are reset.

29.5.21 TIMx capture/compare register 3 (TIMx_CCR3)(x = 3, 4)

Address offset: 0x03C

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	CCR3[19:16]
												rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR3[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:0 CCR3[19:0]: Capture/compare 3 value

If channel CC3 is configured as output:

CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on tim_oc3 output.

Non-dithering mode (DITHEN = 0)

The register holds the compare value in CCR3[15:0]. The CCR3[19:16] bits are reset.

Dithering mode (DITHEN = 1)

The register holds the integer part in CCR3[19:4]. The CCR3[3:0] bitfield contains the dithered part.

If channel CC3 is configured as input:

CCR3 is the counter value transferred by the last input capture 3 event (tim_ic3). The TIMx_CCR3 register is read-only and cannot be programmed.

Non-dithering mode (DITHEN = 0)

The CCR3[15:0] bits hold the capture value. The CCR3[19:16] bits are reserved.

Dithering mode (DITHEN = 1)

The register holds the capture in CCR3[19:0]. The CCR3[3:0] bits are reset.

29.5.22 TIMx capture/compare register 3 (TIMx_CCR3)(x = 2, 5)

Address offset: 0x03C

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR3[31:16]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR3[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:0 CCR3[31:0]: Capture/compare 3 value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on tim_oc3 output.

Non-dithering mode (DITHEN = 0)

The register holds the compare value.

Dithering mode (DITHEN = 1)

The register holds the integer part in CCR3[31:4]. The CCR3[3:0] bitfield contains the

dithered part.

If channel CC3 is configured as input:

CCR3 is the counter value transferred by the last input capture 3 event (tim_ic3). The

TIMx_CCR3 register is read-only and cannot be programmed.

Non-dithering mode (DITHEN = 0)

The register holds the capture value.

Dithering mode (DITHEN = 1)

The register holds the capture in CCR3[31:0]. The CCR3[3:0] bits are reset.

29.5.23 TIMx capture/compare register 4 (TIMx_CCR4)(x = 3, 4)

Address offset: 0x040

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	CCR4[19:16]
												rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR4[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:0 CCR4[19:0]: Capture/compare 4 value

If channel CC4 is configured as output:

CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on tim_oc4 output.

Non-dithering mode (DITHEN = 0)

The register holds the compare value in CCR4[15:0]. The CCR4[19:16] bits are reset.

Dithering mode (DITHEN = 1)

The register holds the integer part in CCR4[19:4]. The CCR4[3:0] bitfield contains the dithered part.

If channel CC4 is configured as input:

CCR4 is the counter value transferred by the last input capture 4 event (tim_ic4). The TIMx_CCR4 register is read-only and cannot be programmed.

Non-dithering mode (DITHEN = 0)

The CCR4[15:0] bits hold the capture value. The CCR4[19:16] bits are reserved.

Dithering mode (DITHEN = 1)

The register holds the capture in CCR4[19:0]. The CCR4[3:0] bits are reset.

29.5.24 TIMx capture/compare register 4 (TIMx_CCR4)(x = 2, 5)

Address offset: 0x040

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR4[31:16]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR4[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:0 CCR4[31:0]: Capture/compare 4 value If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on tim_oc4 output.

Non-dithering mode (DITHEN = 0)

The register holds the compare value.

Dithering mode (DITHEN = 1)

The register holds the integer part in CCR4[31:4]. The CCR4[3:0] bitfield contains the dithered part.

If channel CC4 is configured as input:

CCR4 is the counter value transferred by the last input capture 4 event (tim_ic4). The

TIMx_CCR4 register is read-only and cannot be programmed.

Non-dithering mode (DITHEN = 0)

The register holds the capture value.

Dithering mode (DITHEN = 1)

The register holds the capture in CCR4[31:0]. The CCR4[3:0] bits are reset.

29.5.25 TIMx timer encoder control register (TIMx_ECR)(x = 2 to 5)

Address offset: 0x058

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	PWPRSC[2:0]			PW[7:0]
					rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	IPOS[1:0]		FIDX	Res.	Res.	IDIR[1:0]		IE
								rw	rw	rw			rw	rw	rw

Bits 31:27 Reserved, must be kept at reset value.

Bits 26:24 PWPRSC[2:0]: Pulse width prescaler

This bitfield sets the clock prescaler for the pulse generator, as following:

t_{PWG} = (2^{(PWPRSC [2 : 0])}) \times t_{tim_\ker_ck}

Bits 23:16 PW[7:0]: Pulse width

This bitfield defines the pulse duration, as following:

t_{PW} = PW [7 : 0] \times t_{PWG}

Bits 15:8 Reserved, must be kept at reset value.

29.5.26 TIMx timer input selection register (TIMx_TISEL)(x = 2 to 5)

Address offset: 0x05C

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	TI4SEL[3:0]				Res.	Res.	Res.	Res.	TI3SEL[3:0]
				rw	rw	rw	rw					rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	TI2SEL[3:0]				Res.	Res.	Res.	Res.	TI1SEL[3:0]
				rw	rw	rw	rw					rw	rw	rw	rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 7:6 IPOS[1:0]: Index positioning

In quadrature encoder mode (SMS[3:0] = 0001, 0010, 0011, 1110, 1111), this bit indicates in

which AB input configuration the Index event resets the counter.

00: Index resets the counter when

A B = 00

01: Index resets the counter when

A B = 01

10: Index resets the counter when

AB = 10

11: Index resets the counter when

A B = 11

In directional clock mode or clock plus direction mode (SMS[3:0] = 1010, 1011, 1100, 1101), these bits indicates on which level the Index event resets the counter. In bidirectional clock mode, this applies for both clock inputs.

x 0

: Index resets the counter when clock is 0

x1: Index resets the counter when clock is 1

Note: IPOS[1] bit is not significant

Bit 5 FIDX: First index

This bit indicates if the first index only is taken into account

0 : Index is always active

1: the first Index only resets the counter

Bits 4:3 Reserved, must be kept at reset value.

Bits 2:1 IDIR[1:0]: Index direction

This bit indicates in which direction the Index event resets the counter.

00: Index resets the counter whatever the direction

01: Index resets the counter when up-counting only

10: Index resets the counter when down-counting only

11: Reserved

Note: The IDR[1:0] bitfield must be written when IE bit is reset (index disabled).

Bit 0 IE: Index enable

This bit indicates if the Index event resets the counter.

0 : Index disabled

1: Index enabled

Bits 27:24 TI4SEL[3:0]: Selects tim_ti4[15:0] input

0000: tim_ti4_in0: TIMx_CH4

0001: tim_ti4_in1

\dots

1111: tim_ti4_in15

Refer to Section 29.4.2: TIM2/TIM3/TIM4/TIM5 pins and internal signals for product specific

implementation.

Bits 23:20 Reserved, must be kept at reset value.

Bits 19:16 TI3SEL[3:0]: Selects tim_ti3[15:0] input

0000: tim_ti3_in0: TIMx_CH3

0001: tim_ti3_in1

\dots

1111: tim_ti3_in15

Refer to Section 29.4.2: TIM2/TIM3/TIM4/TIM5 pins and internal signals for product specific

implementation.

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:8 TI2SEL[3:0]: Selects tim_ti2[15:0] input

0000: tim_ti2_in0: TIMx_CH2

0001: tim_ti2_in1

\dots

1111: tim_ti2_in15

Refer to Section 29.4.2: TIM2/TIM3/TIM4/TIM5 pins and internal signals for product specific

implementation.

Bits 7:4 Reserved, must be kept at reset value.

Bits 3:0 TI1SEL[3:0]: Selects tim_ti1[15:0] input

0000: tim_ti1_in0: TIMx_CH1

0001: tim_ti1_in1

\dots

1111: tim_ti1_in15

Refer to Section 29.4.2: TIM2/TIM3/TIM4/TIM5 pins and internal signals for product specific

implementation.

29.5.27 TIMx alternate function register 1 (TIMx_AF1)(x = 2 to 5)

Address offset: 0x060

Reset value: 0x00000000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL[1:0]		Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
rw	rw

Bits 31:18 Reserved, must be kept at reset value.

Bits 17:14 ETRSEL[3:0]: etr_in source selection

These bits select the etr_in input source.

0000: tim_etr0: TIMx_ETR input

0001: tim_etr1

\dots

1111: tim_etr15

Refer to Section 29.4.2: TIM2/TIM3/TIM4/TIM5 pins and internal signals for product specific implementation.

Bits 13:0 Reserved, must be kept at reset value.

29.5.28 TIMx alternate function register 2 (TIMx_AF2)(x = 2 to 5)

Address offset: 0x064

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OCRSEL[2:0]
													rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:16 OCRSEL[2:0]: ocref_clr source selection

These bits select the ocref_clr input source.

000: tim_ocref_clr0

001: tim_ocref_clr1

\dots

111: tim_ocref_clr7

Refer to Section 29.4.2: TIM2/TIM3/TIM4/TIM5 pins and internal signals for product specific implementation.

Bits 15:0 Reserved, must be kept at reset value.

29.5.29 TIMx DMA control register (TIMx_DCR)(x = 2 to 5)

Address offset: 0x3DC

Reset value: 0x00000000

	14	7	12	11	10	0	0	7	0		4	0	4	1	0
Res.	Res.	Res.	DBL[4:0]					Res.	Res.	Res.	DBA[4:0]
			rw	rw	rw	rw	rw				rw	rw	rw	rw	rw

Bits 31:13 Reserved, must be kept at reset value.

Bits 12:8 DBL[4:0]: DMA burst length

This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below).

00000: 1 transfer

00001: 2 transfers

00010: 3 transfers

11010: 26 transfers

Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIM2_CR1.

-If

DBL = 7

bytes and

DBA = TIM 2_CR 1

represents the address of the byte to be

transferred, the address of the transfer is given by the following equation:

(TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL

In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the

address from/to which the data are copied. In this case, the transfer is done to 7 registers

starting from the following address: (TIMx_CR1 address) + DBA

According to the configuration of the DMA Data Size, several cases may occur:

-If the DMA Data Size is configured in half-words, 16-bit data are transferred to each of the 7

registers.

-If the DMA Data Size is configured in bytes, the data are also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA.

Bits 7:5 Reserved, must be kept at reset value.

Bits 4:0 DBA[4:0]: DMA base address

This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register.

Example:

00000: TIMx_CR1,

00001: TIMx_CR2,

00010: TIMx_SMCR, 29.5.30 TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 5)

29.5.31 TIMx register map

TIMx registers are mapped as described in the table below.

Table 287. TIM2/TIM3/TIM4/TIM5 register map and reset values

Offset	Register name	31	30	23	23	27	26	2624	23	22	21	20	1.	1.	17	1.5	伯	14	13	12	11	10	9	8	7	6	5	4	3	2	1	O
0x000	TIMx_CR1	B	3	郎	y	串	:	33	3	3	鲜	33	3	8	3	(3)	3	8	3	NEHILIO	VW3231n		CKD [1:0]		ARPH	CMS [1:0]		D股	Operation	Univ.	Space	CHF
0x000	Reset value																			0	0		0	0	0	0	0	0	0	0	0	0
0x004	TIMx_CR2	Proof.	PROS	3	:	8	d	[8]SWW	超市	Proof.	Proof.	1,000	超市	BUR	REPAR	PAR	B		郎	股本	出	B	Proof.	郎	THE	MMS[2:0]			Open	Proof.	中國	1,573
0x004	Reset value							0																	0	0	0	0	0
0x008	TIMx_SMCR	.3	“	E	PROM	CHE	Proof.	SdSWS3dSWS	Let	股本	TS [4:3]		PAR	PROS	3	SIS	Engineer	ECC	ETPS [1:0]		ETF[3:0]				MS5	TS[2:0]			3	SMS[2:0]
0x008	Reset value							00			0	0				0	0	0	0	0	0	0	0	0	0	0	0	0		0	0	0
0x00C	TIMx_DIER	串	3	PRON	招聘	路	y	3318831	318831	Direct	IDE		：	招聘	8	S	8	TE	S	30500	30800	30200	30100	VISE		正	：	Cutton	COND	CON	GUI	当
0x00C	Reset value							0	0	0	0							0		0	0	0	0	0		0		0	0	0	0	0
0x010	TIMx_SR	Proof.	5,459	RAND	5	海	BUG	3LECK	Effect	Diff	ID.S	Proof.	Proof.	E	PROS	13	：	股本	3	40t00	40800	40200	40100	Refs.	For	千港元	Proof.	COUTE	CS3	COND	GUI	当
0x010	Reset value							0	0	0	0									0	0	0	0			0		0	0	0	0	0
0x014	TIMx_EGR	R	For	PA	CHF	For	BUG	PU好	PO	PARTHE	S	For	REPA	PROM	REPT	出生	鲜		好			Proof.	PAR			IS		Oct-C	CS3	CO2	SU	19
0x014	Reset value																									0		0	0	0	0	0
0x018	TIMx CCMR1 Input Capture mode	2021	Proof.	3	:	8	1.4	3,4731	粉色	粉	S	1,000	B	3	鲜	Proof.	IC2F[3:0]				1C2 PSC [1:0]		CC2S [1:0]		IC1F[3:0]				IC1 PSC [1:0]		CC1S [1:0]
	Reset value																0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
	TIMx CCMR1 Output Compare mode	a	BATT	3	Proof.	PROS	13	[8]wzoo	中國	招	Proof.	PART	BAR	3	路	[8]W100	30200	OC2M [2:0]			3d200	34200	CC2S [1:0]		30100	OC1M $[2 : 0]$			3d100	3.1100	CC1S [1:0]
	Reset value							0								0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x01C	TIMx CCMR2 Input Capture mode	:	：	：	PHY	：	8	(a)3	BUE	3	CATE	8	SH	PROS	33	8	IC4F[3:0]				IC4 PSC [1:0]		CC48 [1:0]		IC3F[3:0]				IC3 PSC [1:0]		CC3S [1:0]
	Reset value																0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
	TIMx CCMR2 Output Compare mode		(a)	PROS	超市	3	CON	[8] WtOO	1,000	Proof.	3,399	E	3	8	E	[8] W800	30	OC4M [2:0]			3d500	3.	CC48 [1:0]		30800	OC3M [2:0]			300	3.1800	CC3S [1:0]
	Reset value							0								0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x020	TIMx_CCER	3	Rep	出口	PHY	COMP	Proof.	COMP3	鸭	3	S	Proof.	0	E	BUR	千港元	dNtOO		COND	COUTE	COND		OS	CO2	COND		Oct-22	CO2	SU		COND	GUI
0x020	Reset value																0		0	0	0		0	0	0		0	0	0		0	0

Table 207. TIMZ/TINIO/TINI4/TINIO TEQISTET THEandeselvalues(continued)
Offset	Register name	31	30	23	23	2726	26	2423	22	21	2023	1.	1.	17	伯	16	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x024	TIMx_CNT	[18]. Ling adding	CNT[30:16] (CNT[31:16] on 32-bit timers only)													CNT[15:0]
0x024	Reset value	0	0	0	0	00	0	00	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x028	TIMx_PSC	8,000	好			3500		3	E	g	5	3	8		8								PSC[15:0]
0x028	Reset value															0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x02C	TIMx_ARR (x = 3, 4)					好6,000			(a)	3,000	3										ARR[19:0]
0x02C	Reset value											0	0	0	0	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
0x02C	TIMx_ARR (x = 2, 5)	ARR[31:0]
0x02C	Reset value	1	1	1	1	11	1	11	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
0x030													Reserved
0x034	TIMx_CCR1			CCR1[31:20] (32-bit timers only)																	CCR1[19:0]
0x034	Reset value	0	0	0	0	00	0	00	0	0	0	0	0	0	0	0		0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x038	TIMx_CCR2		(32-bit timers only)CCR2[31:20]CCR2[19:0]
0x038	Reset value	0	0	0	0	00	0	00	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x03C	TIMx_CCR3	(32-bit timers only)CCR3[31:20]CCR3[19:0]
0x03C	Reset value	0	0	0	0	00	0	00	0	0	0	0	0	0	0	0		0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x040	TIMx_CCR4	(32-bit timers only)CCR4[31:20]CCR4[19:0]
0x040	Reset value	0	0	0	0	00	0	00	0	0	0	0	0	0	0	0		0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x044.. 0x054	ReservedRes.
0x058	TIMx_ECR					f	PWPRSC [2:0]	PW[7:0]								6,699	8		:	a	a	83	郎	IPOS [1:0]		FIDE	3	h	IDIR [1:0]		IE
0x058	Reset value					0	0	00	0	0	0	0	0	0	0									0	0	0			0	0	0
0x05C	TIMx_TISEL					TI4SEL[3:0]				y		TI3SEL[3:0]				將			. .	TI2SEL[3:0]					“	將		TI1SEL[3:0]
0x05C	Reset value					00	0	0				0	0	0	0					0	0	0	0					0	0	0	0
0x060	TIMx_AF1	La	S	將	3	38		138	a	tr	8	a	Proof.	ETRSEL [3:0]					3	E	a	粉	： 3	33	(3)	13	3	S	郎	3,959	3
0x060	Reset value													0	0	0	0
0x064	TIMx_AF2		3			a福				a			OCRSELI 2:0]			R					38	时	3		福	3	3,959	电话		好	a
0x064	Reset value												0	0	0
0x068. Reserved 0x3D8		Res.
0x3DC	TIMx_DCR							都		Proof.		3	(3)			面			DBL[4:0]							8	DBA[4:0]
0x3DC	Reset value																		0	0	0	0	0				0	0	0	0	0

30 General purpose timers (TIM15/TIM16/TIM17)

30.1 TIM15/TIM16/TIM17 introduction

The TIM15/TIM16/TIM17 timers consist of a 16-bit auto-reload counter driven by a programmable prescaler.

They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion).

Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers.

The TIM15/TIM16/TIM17 timers are completely independent, and do not share any resources. TIM15 can be synchronized as described in Section 30.4.26: Timer synchronization (TIM15 only).

30.2 TIM15 main features

TIM15 includes the following features:

16-bit auto-reload upcounter

16-bit programmable prescaler used to divide (also "on the fly") the counter clock frequency by any factor between 1 and 65535

Up to 2 independent channels for:

Input capture

Output compare

PWM generation (edge mode)

One-pulse mode output

Complementary outputs with programmable dead-time (for channel 1 only)

Synchronization circuit to control the timer with external signals and to interconnect several timers together

Repetition counter to update the timer registers only after a given number of cycles of the counter

Break input to put the timer's output signals in the reset state or a known state

Interrupt/DMA generation on the following events:

Update: counter overflow, counter initialization (by software or internal/external trigger)

Trigger event (counter start, stop, initialization or count by internal/external trigger)

Input capture

Output compare

Break input (interrupt request)

Refer to Section 30.4.15: Using the break function for details.

This signal can be used as trigger for some slave timer (see internal trigger connection table in next section). See Section 30.4.27: Using timer output as trigger for other timers (TIM16/TIM17 only) for details.

30.4.2 TIM15/TIM16/TIM17 pins and internal signals

Table 288 and Table 289 in this section summarize the TIM inputs and outputs.

Table 288. TIM input/output pins

Pin name	Signal type	Description
TIM_CH1 TIM_CH2(1)	Input/Output	Timer multi-purpose channels. Each channel be used for capture, compare, or PWM. TIM_CH1 and TIM_CH2 can also be used as external clock (below 1/4 of the tim_ker_ck clock) and external trigger inputs
TIM_CH1N	Output	Timer complementary outputs, derived from TIM_CH1 output with the possibility to have deadtime insertion.
TIM_BKIN	Input / Output	Break input. This input can also be configured in bidirectional mode.

Available for TIM15 only.

Table 289. TIM internal input/output signals

Internal signal name	Signal type	Description
tim_ti1_in[15:0] tim_ti2_in[15:0](1)	Input	Internal timer inputs bus. These inputs can be used for capture or as external clock (below 1/4 of the tim_ker_ck clock).
tim_itr[15:0](1)	Input	Internal trigger input bus. These inputs can be used for the slave mode controller or as a input clock (below 1/4 of the tim_ker_ck clock).
tim_trgo(1)	Output	Internal trigger output. This trigger can trigger other on-chip peripherals.
tim_ocref_clr[7:0]	Input	Timer tim_ocref_clr input bus. These inputs can be used to clea the tim_ocxref signals, typically for hardware cycle-by-cycle pulsewidth control.
tim_brk_cmp[8:1]	Input	Break input for internal signals
tim_sys_brk[n:0]	Input	System break input. This input gathers the MCU's system level errors.
tim_pclk	Input	Timer APB clock
tim_ker_ck	Input	Timer kernel clock. This clock must be synchronous with tim pclk (derived from the same source). The clock ratio tim_ker_ck/tim_pclk must be an integer:1, 2, 3,..., 16 (maximum value)
tim_it	Output	Global Timer interrupt, gathering capture/compare, update, break trigger and commutation requests
tim_cc1_dma	Output	Timer capture / compare 1 dma request
tim_upd_dma	Output	Timer update dma request
tim_trg_dma	Output	Timer trigger dma request
tim_com_dma	Output	Timer commutation dma request

Available for TIM15 only.

Table 290 and Table 291 list the sources connected to the tim_ti[2:1] input multiplexers.

Table 290. Interconnect to the tim_ti1 input multiplexer

tim_ti1 inputs	Sources
tim_ti1 inputs	TIM15	TIM16	TIM17
tim_ti1_in0	TIM15_CH1	TIM16_CH1	TIM17_CH1
tim_ti1_in1	LSE	comp6_out	comp5_out
tim_ti1_in2	comp1_out	MCO	MCO
tim_ti1_in3	comp2_out	HSE / 32(1)	HSE / 32(1)

Table 290. Interconnect to the tim_ti1 input multiplexer (continued)

tim_ti1 inputs	Sources
tim_ti1 inputs	TIM15	TIM16	TIM17
tim_ti1_in4	comp5_out	RTC Clock	RTC Clock
tim_ti1_in5	comp7_out	LSE	LSE
tim_ti1_in6	Reserved	LSI	LSI
tim_ti1_in[15:7]	Reserved

This signal is available only if the HSE32EN bit is set in the TIMx OR1 register. See Section 30.8.19: TIMx option register 1 (TIMx_OR1)(x = 16 to 17) for details.

Table 291. Interconnect to the tim_ti2 input multiplexer

tim_ti2 inputs	Sources
tim_ti2 inputs	TIM 15
tim_ti2_in0	TIM15_CH2
tim_ti2_in1	comp2_out
tim_ti2_in2	comp3_out
tim_ti2_in3	comp6_out
tim_ti2_in4	comp7_out
tim_ti2_in[15:5]	Reserved

Table 292 lists the internal sources connected to the tim_itr input multiplexer.

Table 292. TIMx internal trigger connection

tim_itrx inputs	TIM15
tim_itr0	tim1_trgo
tim_itr1	tim2_trgo
tim_itr2	tim3_trgo
tim_itr3	tim4_trgo
tim_itr4	tim5_trgo
tim_itr5	tim8_trgo
tim_itr6	Reserved
tim_itr7	tim16_oc1
tim_itr8	tim17_oc1
tim_itr9	tim20_trgo
tim_itr10	hrtim_out_sync2
tim_itr[15:11]	Reserved

Table 293 and Table 294 list the sources connected to the tim_brk input.

Table 293. Timer break interconnect

tim_brk inputs	TIM15	TIM16	TIM17
TIM_BKIN	TIM15_BKIN pin	TIM16_BKIN pin	TIM17_BKIN pin
tim_brk_cmp1	comp1_out	comp1_out	comp1_out
tim_brk_cmp2	comp2_out	comp2_out	comp2_out
tim_brk_cmp3	comp3_out	comp3_out	comp3_out
tim_brk_cmp4	comp4_out	comp4_out	comp4_out
tim_brk_cmp5	comp5_out	comp5_out	comp5_out
tim_brk_cmp6	comp6_out	comp6_out	comp6_out
tim_brk_cmp7	comp7_out	comp7_out	comp7_out
tim_brk_cmp8	Reserved

Table 294. System break interconnect

tim_sys_brk inputs	TIM15 / TIM16 / TIM17	Enable bit in SYSCFG_CFGR2 register
tim_sys_brk0	Cortex®-M4 with FPU LOCKUP	CLL
tim_sys_brk1	Programmable Voltage Detector (PVD)	PVDL
tim_sys_brk2	SRAM parity error	SPL
tim_sys_brk3	Flash double ECC error	ECCL
tim_sys_brk4	Clock Security System (CSS)	None (always enabled)

Table 295 lists the internal sources connected to the tim_ocref_clr input multiplexer.

Table 295. Interconnect to the ocref_clr input multiplexer

Timer OCREF clear signal	Timer OCREF clear signals assignment
Timer OCREF clear signal	TIM15	TIM16	TIM17
tim_ocref_clr0	comp1_out	comp1_out	comp1_out
tim_ocref_clr1	comp2_out	comp2_out	comp2_out
tim_ocref_clr2	comp3_out	comp3_out	comp3_out
tim_ocref_clr3	comp4_out	comp4_out	comp4_out
tim_ocref_clr4	comp5_out	comp5_out	comp5_out
tim_ocref_clr5	comp6_out	comp6_out	comp6_out
tim_ocref_clr6	comp7_out	comp7_out	comp7_out
tim_ocref_clr7	Reserved

30.4.3 Time-base unit

The main block of the programmable advanced-control timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler.

The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.

The time-base unit includes:

Counter register (TIMx_CNT)

Prescaler register (TIMx_PSC)

Auto-reload register (TIMx_ARR)

Repetition counter register (TIMx_RCR)

The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detailed for each configuration.

Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1 register.

Prescaler description

The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event.

Figure 441 and Figure 442 give some examples of the counter behavior when the prescaler ratio is changed on the fly:

30.4.4 Counter modes

Upcounting mode

In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event.

If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR). Else the update event is generated at each counter overflow.

Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event.

The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0 . However, the counter restarts from 0 , as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit):

The repetition counter is reloaded with the content of TIMx_RCR register,

The auto-reload shadow register is updated with the preload value (TIMx_ARR),

The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register).

The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36.

30.4.5 Repetition counter

Section 30.4.3: Time-base unit describes how the update event (UEV) is generated with respect to the counter overflows. It is actually generated only when the repetition counter has reached zero. This can be useful when generating PWM signals.

This means that data are transferred from the preload registers to the shadow registers (TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx capture/compare registers in compare mode) every

N

counter overflows,where

N

is the value in the TIMx_RCR repetition counter register.

The repetition counter is decremented at each counter overflow.

The repetition counter is an auto-reload type; the repetition rate is maintained as defined by the TIMx_RCR register value (refer to Figure 449). When the update event is generated by software (by setting the UG bit in TIMx_EGR register) or by hardware through the slave mode controller, it occurs immediately whatever the value of the repetition counter is and the repetition counter is reloaded with the content of the TIMx_RCR register.

Figure 449. Update rate examples depending on mode and TIMx_RCR register settings

30.4.6 Clock selection

The counter clock can be provided by the following clock sources:

Internal clock (tim_ker_ck)

External clock mode1: external input pin (tim_ti1 or tim_ti2, if available)

Internal trigger inputs (tim_itrx) (only for TIM15): using one timer as the prescaler for another timer, for example, TIM1 can be configured to act as a prescaler for TIM15. Refer to Using one timer to enable another timer for more details.

Internal clock source (tim_ker_ck)

If the slave mode controller is disabled (SMS=000), then the CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1 , the prescaler is clocked by the internal clock tim_ker_ck.

Select the proper tim_ti2_in[15:0] source (internal or external) with the TI2SEL[3:0] bits in the TIMx_TISEL register.

Configure channel 2 to detect rising edges on the tim_ti2 input by writing CC2S = '01' in the TIMx_CCMR1 register.

Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed,keep IC2F=0000).

Select rising edge polarity by writing CC2P=0 in the TIMx_CCER register.

Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register.

Select tim_ti2 as the trigger input source by writing TS=00110 in the TIMx_SMCR register.

Enable the counter by writing CEN=1 in the TIMx_CR1 register.

Note: The capture prescaler is not used for triggering, it is not necessary to configure it.

When a rising edge occurs on tim_ti2, the counter counts once and the TIF flag is set.

The delay between the rising edge on tim_ti2 and the actual clock of the counter is due to the resynchronization circuit on tim_ti2 input.

Figure 452. Control circuit in external clock mode 1

30.4.7 Capture/compare channels

Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control).

Figure 453 to Figure 456 give an overview of one Capture/Compare channel.

Figure 456. Output stage of capture/compare channel (channel 2 for TIM15)

The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register.

In capture mode, captures are actually done in the shadow register, which is copied into the preload register.

In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter.

30.4.8 Input capture mode

In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding tim_icx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to ’ 0 ’ or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when it is written with 0 .

The following example shows how to capture the counter value in TIMx_CCR1 when tim_ti1 input rises. To do this, use the following procedure:

Select the proper tim_ti1_in[15:1] source (internal or external) with the TI1SEL[3:0] bits in the TIMx_TISEL register.

Select the active input: TIMx_CCR1 must be linked to the tim_ti1 input, so write the CC1S bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00 , the channel is configured in input and the TIMx_CCR1 register becomes read-only.

Program the appropriate input filter duration in relation with the signal connected to the timer (when the input is one of the tim_tix (ICxF bits in the TIMx_CCMRx register). Let's imagine that, when toggling, the input signal is not stable during at least 5 internal clock cycles. We must program a filter duration longer than these 5 clock cycles. We can validate a transition on tim_ti1 when 8 consecutive samples with the new level have been detected (sampled at $f_{DTS}$ frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register.

Select the edge of the active transition on the tim_ti1 channel by writing CC1P bit to 0 in the TIMx_CCER register (rising edge in this case).

Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to '00' in the TIMx_CCMR1 register).

Enable capture from the counter into the capture register by setting the CC1E bit in the TIMx_CCER register.

If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the TIMx_DIER register.

When an input capture occurs:

The TIMx_CCR1 register gets the value of the counter on the active transition.

CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared.

An interrupt is generated depending on the CC1IE bit.

A DMA request is generated depending on the CC1DE bit.

Note:

IC interrupt and/or DMA requests can be generated by software by setting the

corresponding CCxG bit in the TIMx_EGR register.

30.4.9 PWM input mode (only for TIM15)

This mode is used to measure both the period and the duty cycle of a PWM signal

connected to single tim_tix input:

The TIMx_CCR1 register holds the period value (interval between two consecutive rising edges)

The TIMx_CCR2 register holds the pulse width (interval between two consecutive rising and falling edges)

This mode is a particular case of input capture mode. The set-up procedure is similar with the following differences:

Two tim_icx signals are mapped on the same tim_tix input.

These 2 tim_icx signals are active on edges with opposite polarity.

One of the two tim_tixfpy signals is selected as trigger input and the slave mode controller is configured in reset mode.

For example, one can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on tim_ti1 using the following procedure

(depending on tim_ker_ck frequency and prescaler value):

Select the proper tim_ti1_in[15:0] source (internal or external) with the TI1SEL[3:0] bits in the TIMx_TISEL register.

Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (tim_ti1 selected).

Select the active polarity for tim_ti1fp1 (used both for capture in TIMx_CCR1 and counter clear): write the CC1P and CC1NP bits to ' 0 ' (active on rising edge).

Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 register (tim_ti1 selected).

Select the active polarity for tim_ti1fp2 (used for capture in TIMx_CCR2): write the CC2P and CC2NP bits to '10' (active on falling edge).

Select the valid trigger input: write the TS bits to 00101 in the TIMx_SMCR register (tim_ti1fp1 selected).

Configure the slave mode controller in reset mode: write the SMS bits to 100 in the TIMx_SMCR register.

Enable the captures: write the CC1E and CC2E bits to '1' in the TIMx_CCER register.

The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only tim_ti1fp1 and tim_ti2fp2 are connected to the slave mode controller.

30.4.10 Forced output mode

In output mode (CCxS bits

= 00

in the TIMx_CCMRx register),each output compare signal (tim_ocxref and then tim_ocx/tim_ocxn) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter.

For example:

CCxP = 0

(tim_ocx active high)

\Rightarrow

tim_ocx is forced to high level.

The tim_ocxref signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx register.

30.4.11 Output compare mode

This function is used to control an output waveform or indicating when a period of time has elapsed.

When a match is found between the capture/compare register and the counter, the output compare function:

Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.

Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).

Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the TIMx_DIER register).

Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request selection).

The TIMx_CCRx registers can be programmed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register.

Procedure

Select the counter clock (internal, external, prescaler).

Write the desired data in the TIMx_ARR and TIMx_CCRx registers.

Set the CCxIE bit if an interrupt request is to be generated.

Select the output mode. For example:

Write OCxM = 011 to toggle tim_ocx output pin when CNT matches CCRx

Write OCxPE $= 0$ to disable preload register

Write $CCxP = 0$ to select active high polarity

Write CCxE = 1 to enable the output

Enable the counter by setting the CEN bit in the TIMx_CR1 register.

The TIMx_CCRx register can be updated at any time by software to control the output waveform,provided that the preload register is not enabled (OCxPE='0', else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 458.

30.4.12 PWM mode

Pulse width modulation mode is used to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.

The PWM mode can be selected independently on each channel (one PWM per tim_ocx output) by writing '110' (PWM mode 1) or '111' (PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. The corresponding preload register must be enabled by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.

tim_ocx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. tim_ocx output is enabled by a combination of the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers). Refer to the TIMx_CCER register description for more details.

In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CCRx

\leq

TIMx_CNT or TIMx_CNT

\leq

TIMx_CCRx (depending on the direction of the counter).

The TIM15/TIM16/TIM17 are capable of upcounting only. Refer to Upcounting mode on page 1363. In the following example, we consider PWM mode 1. The reference PWM signal tim_ocxref is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then tim_ocxref is held at ’1’. If the compare value is 0 then tim_ocxref is held at ’0’. Figure 459 shows some edge-aligned PWM waveforms in an example where TIMx_ARR=8.

Figure 460. Dithering principle

When the dithering mode is enabled, the register coding is changed as following (see

the 4 LSBs are coding for the enhanced resolution part (fractional part)

the MSBs are left-shifted to the bits 19:4 and are coding for the base value.

The ARR and CCR values will be updated automatically if the DITHEN bit is set / reset (for instance, if ARR= 0x05 with DITHEN=0, it will be updated to ARR = 0x50 with DITHEN = 1). The following sequence must be followed when resetting the DITHEN bit:

CEN and ARPE bits must be reset

The ARR[3:0] bits must be reset

The DITHEN bit must be reset

The CCIF flags must be cleared

The CEN bit can be set (eventually with ARPE = 1).

Resolution = \frac{F_{Tim}}{F_{pwm}} \Rightarrow F_{pwmMin} = \frac{F_{Tim}}{{Max}_{Resolution}}

Dithering mode disabled: F_{pwmMin} = \frac{F_{Tim}}{65536}

Dithering mode enabled: F_{pwmMin} = \frac{F_{Tim}}{65535 + \frac{15}{16}}

Figure 461. Data format and register coding in dithering mode

The minimum frequency is given by the following formula:

The auto-reload and compare values increments are spread following specific patterns described in the Table 296 below. The dithering sequence is done to have increments distributed as evenly as possible and minimize the overall ripple.

Table 296. CCR and ARR register change dithering pattern

-	PWM period
LSB value	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16
0000	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
0001	+1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
0010	+1	-	-	-	-	-	-	-	+1	-	-	-	-	-	-	-
0011	+1	-	-	-	+1	-	-	-	+1	-	-	-	-	-	-	-
0100	+1	-	-	-	+1	-	-	-	+1	-	-	-	+1	-	-	-
0101	+1	-	+1	-	+1	-	-	-	+1	-	-	-	+1	-	-	-
0110	+1	-	+1	-	+1	-	-	-	+1	-	+1	-	+1	-	-	-
0111	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-	-	-
1000	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-
1001	+1	+1	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-
1010	+1	+1	+1	-	+1	-	+1	-	+1	+1	+1	-	+1	-	+1	-
1011	+1	+1	+1	-	+1	+1	+1	-	+1	+1	+1	-	+1	-	+1	-
1100	+1	+1	+1	-	+1	+1	+1	-	+1	+1	+1	-	+1	+1	+1	-
1101	+1	+1	+1	+1	+1	+1	+1	-	+1	+1	+1	-	+1	+1	+1	-

Table 296. CCR and ARR register change dithering pattern (continued)

-	PWM period
LSB value	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16
1110	+1	+1	+1	+1	+1	+1	+1	-	+1	+1	+1	+1	+1	+1	+1	-
1111	+1	+1	+1	+1	+1	+1	+1	+1	+1	+1	+1	+1	+1	+1	+1	-

30.4.13 Combined PWM mode (TIM15 only)

Combined PWM mode allows two edge or center-aligned PWM signals to be generated with programmable delay and phase shift between respective pulses. While the frequency is

tim_oc1refc (or tim_oc2refc) is controlled by the TIMx_CCR1 and TIMx_CCR2 registers PWM mode 2) in the OCxM bits in the TIMx_CCMRx register.

When a given channel is used as a combined PWM channel, its complementary channel must be configured in the opposite PWM mode (for instance, one in Combined PWM mode

Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant

Figure 464 represents an example of signals that can be generated using combined PWM mode, obtained with the following configuration:

Channel 1 is configured in Combined PWM mode 2,

Channel 2 is configured in PWM mode 1,

Figure 464. Combined PWM mode on channel 1 and 2

30.4.14 Complementary outputs and dead-time insertion

The TIM15/TIM16/TIM17 general-purpose timers can output one complementary signal and manage the switching-off and switching-on of the outputs.

This time is generally known as dead-time and it has to be adjusted depending on the devices that are connected to the outputs and their characteristics (intrinsic delays of level-shifters, delays due to power switches...)

The polarity of the outputs (main output tim_ocx or complementary tim_ocxn) can be selected independently for each output. This is done by writing to the CCxP and CCxNP bits in the TIMx_CCER register.

The complementary signals tim_ocx and tim_ocxn are activated by a combination of several control bits: the CCxE and CCxNE bits in the TIMx_CCER register and the MOE, OISx, OISxN, OSSI and OSSR bits in the TIMx_BDTR and TIMx_CR2 registers. Refer to Table 303: Output control bits for complementary tim_oc1 and tim_oc1n channels with break feature (TIM16/TIM17) on page 1444 for more details. In particular, the dead-time is activated when switching to the idle state (MOE falling down to 0 ).

Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the break circuit is present. There is one 10-bit dead-time generator for each channel. From a reference waveform tim_ocxref, it generates 2 outputs tim_ocx and tim_ocxn. If tim_ocx and tim_ocxn are active high:

The tim_ocx output signal is the same as the reference signal except for the rising edge, which is delayed relative to the reference rising edge.

The tim_ocxn output signal is the opposite of the reference signal except for the rising edge, which is delayed relative to the reference falling edge.

If the delay is greater than the width of the active output (tim_ocx or tim_ocxn) then the corresponding pulse is not generated.

The following figures show the relationships between the output signals of the dead-time generator and the reference signal tim_ocxref. (we suppose CCxP=0, CCxNP=0, MOE=1,

CCxE = 1

and

CCxNE = 1

in these examples)

Figure 465. Complementary output with symmetrical dead-time insertion.

The DTAE bit in the TIMx_DTR2 is used to differentiate the deadtime values for rising and falling edges of the reference signal, as shown on Figure 466.

In asymmetrical mode (DTAE = 1), the rising edge-referred deadtime is defined by the DTG[7:0] bitfield in the TIMx_BDTR register, while the falling edge-referred is defined by the DTGF[7:0] bitfield in the TIMx_DTR2 register. The DTAE bit must be written before enabling the counter and must be not modified while CEN = 1 .

It is possible to have the deadtime value updated on-the-fly during pwm operation, using a preload mechanism. The deadtime bitfield DTG[7:0] and DTGF[7:0] are preloaded when the DTPE bit is set, in the TIMX_DTR2 register. The preload value is loaded in the active register on the next update event.

Note: If the DTPE bit is enabled while the counter is enabled, any new value written since last update is discarded and previous value is used.

Re-directing tim_ocxref to tim_ocx or tim_ocxn

In output mode (forced, output compare or PWM), tim_ocxref can be re-directed to the tim_ocx output or to tim_ocxn output by configuring the CCxE and CCxNE bits in the TIMx_CCER register.

This is used to send a specific waveform (such as PWM or static active level) on one output while the complementary remains at its inactive level. Other alternative possibilities are to have both outputs at inactive level or both outputs active and complementary with dead-time.

Note:

When only tim_ocxn is enabled (CCxE=0,CCxNE=1),it is not complemented and becomes active as soon as tim_ocxref is high. For example, if CCxNP=0 then tim_ocxn=tim_ocxref. On the other hand,when both tim_ocx and tim_ocxn are enabled (CCxE=CCxNE=1) tim_ocx becomes active when tim_ocxref is high whereas tim_ocxn is complemented and becomes active when tim_ocxref is low.

30.4.15 Using the break function

The purpose of the break function is to protect power switches driven by PWM signals generated with the timers. The break input is usually connected to fault outputs of power stages and 3-phase inverters. When activated, the break circuitry shuts down the PWM outputs and forces them to a predefined safe state.

The break channel gathers both system-level fault (clock failure, ECC / parity errors,...) and application fault (from input pins and built-in comparator), and can force the outputs to a predefined level (either active or inactive) after a deadtime duration.

The output enable signal and output levels during break are depending on several control bits:

the MOE bit in TIMx_BDTR register is used to enable /disable the outputs by software and is reset in case of break or break2 event.

the OSSI bit in the TIMx_BDTR register defines whether the timer controls the output in inactive state or releases the control to the GPIO controller (typically to have it in Hi-Z mode)

the OISx and OISxN bits in the TIMx_CR2 register which are setting the output shutdown level, either active or inactive. The tim_ocx and tim_ocxn outputs cannot be set both to active level at a given time, whatever the OISx and OISxN values. Refer to Table 303: Output control bits for complementary tim_oc1 and tim_oc1n channels with break feature (TIM16/TIM17) on page 1444 for more details.

When exiting from reset, the break circuit is disabled and the MOE bit is low. The break function is enabled by setting the BKE bit in the TIMx_BDTR register. The break input polarity can be selected by configuring the BKP bit in the same register. BKE and BKP can be modified at the same time. When the BKE and BKP bits are written, a delay of 1 APB clock cycle is applied before the writing is effective. Consequently, it is necessary to wait 1 APB clock period to correctly read back the bit after the write operation.

Because MOE falling edge can be asynchronous, a resynchronization circuit has been inserted between the actual signal (acting on the outputs) and the synchronous control bit (accessed in the TIMx_BDTR register). It results in some delays between the asynchronous and the synchronous signals. In particular, if MOE is set to 1 whereas it was low, a delay must be inserted (dummy instruction) before reading it correctly. This is because the write acts on the asynchronous signal whereas the read reflects the synchronous signal.

The break is generated by the tim_brk inputs which has:

Programmable polarity (BKP bit in the TIMx_BDTR register)

Programmable enable bit (BKE bit in the TIMx_BDTR register)

Programmable filter (BKF[3:0] bits in the TIMx_BDTR register) to avoid spurious events.

The break can be generated from multiple sources which can be individually enabled and with programmable edge sensitivity, using the TIMx_AF1 register.

The sources for break (tim_brk) channel are:

External sources connected to one of the TIM_BKIN pin (as per selection done in the GPIO alternate function selection registers), with polarity selection and optional digital filtering

Internal sources:

coming from a tim_brk_cmpx input (refer to Section 30.4.2: TIM15/TIM16/TIM17 pins and internal signals for product specific implementation)

coming from a system break request on the tim_sys_brk inputs (refer to Section 30.4.2: TIM15/TIM16/TIM17 pins and internal signals for product specific implementation)

Break events can also be generated by software using BG bit in the TIMx_EGR register. All sources are ORed before entering the timer tim_brk inputs, as per Figure 469 below.

Figure 469. Break circuitry overview

Caution: An asynchronous (clockless) operation is only guaranteed when the programmable filter is disabled. If it is enabled, a fail safe clock mode (for example, using the internal PLL and/or the CSS) must be used to guarantee that break events are handled.

When a break occurs (selected level on the break input):

The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or even releasing the control to the GPIO (selected by the OSSI bit). This feature functions even if the MCU oscillator is off.

Each output channel is driven with the level programmed in the OISx bit in the TIMx_CR2 register as soon as MOE=0. If OSSI=0, the timer releases the output control (taken over by the GPIO) else the enable output remains high.

When complementary outputs are used:

The outputs are first put in reset state inactive state (depending on the polarity). This is done asynchronously so that it works even if no clock is provided to the timer.

If the timer clock is still present, then the dead-time generator is reactivated in order to drive the outputs with the level programmed in the OISx and OISxN bits after a dead-time. Even in this case, tim_ocx and tim_ocxn cannot be driven to their active level together. Note that because of the resynchronization on MOE, the dead-time duration is a bit longer than usual (around 2 tim_ker_ck clock cycles).

If OSSI=0 then the timer releases the enable outputs (taken over by the GPIO which forces a Hi-Z state) else the enable outputs remain or become high as soon as one of the CCxE or CCxNE bits is high.

The break status flag (BIF bit in the TIMx_SR register) is set. An interrupt can be generated if the BIE bit in the TIMx_DIER register is set. A DMA request can be sent if the BDE bit in the TIMx_DIER register is set.

If the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again at the next update event UEV. This can be used to perform a regulation, for instance. Else, MOE remains low until it is written with 1 again. In this case, it can be used for security and the break input can be connected to an alarm from power drivers, thermal sensors or any security components.

Note: If the MOE is reset by the CPU while the AOE bit is set, the outputs are in idle state and forced to inactive level or Hi-Z depending on OSSI value. If both the MOE and AOE bits are reset by the CPU, the outputs are in disabled state and driven with the level programmed in the OISx bit in the TIMx_CR2 register.

Note: The break inputs is acting on level. Thus, the MOE cannot be set while the break input is active (neither automatically nor by software). In the meantime, the status flag BIF cannot be cleared.

The break can be generated by the tim_brk input which has a programmable polarity and an enable bit BKE in the TIMx_BDTR Register.

In addition to the break input and the output management, a write protection has been implemented inside the break circuit to safeguard the application. It is used to freeze the configuration of several parameters (dead-time duration, tim_ocx/tim_ocxn polarities and state when disabled, OCxM configurations, break enable and polarity). The protection can be selected among 3 levels with the LOCK bits in the TIMx_BDTR register. Refer to Section 30.8.14: TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17). The LOCK bits can be written only once after an MCU reset.

The Figure 470 shows an example of behavior of the outputs in response to a break.

Figure 470. Output behavior in response to a break event on tim_brk

			(1) =0) (1) =0) 又 $CxNP = ($ CxNP=1 $CxNP = 0$ CxNP=0 OISx=0	delay OIS delay OIS OIS OIS )ISxN	BREAK (MOET )	$\leftrightarrow$ delay delay delay $\leftrightarrow$ delay x=OIS │		MSv62337V1

tim_ocxref

tim_ocx (tim_ocxn not implemented, CCxP=0
tim_ocx (tim_ocxn not implemented, CCxP=0		OIS:
tim_ocx (tim_ocxn not implemented, CCxP=1		OIS
tim_ocx
(tim_ocxn not implemented, CCxP='		OIS:

tim_ocx		$\leftrightarrow$
tim_ocxn		delay
$(CCxE = 1, CCxP = 0,$	OISx=0, CCxNE	=1, C			kN=1

tim_ocx
		$\leftrightarrow$
tim_ocxn		delay
$(CCxE = 1, CCxP = 0,$	OISx=1, CCxNE	=1, C			(N=1)

tim_ocx
tim_ocxn $(CCxE = 1, CCxP = 0,$	OISx=0, CCxNE	$= 0, C$			(N=1)

tim_ocx
tim_ocxn
$(CCxE = 1, CCxP = 0,$	OISx=1, CCxNE	$= 0, C$			(N=0)

tim_ocx
tim_ocxn $(CCxE = 1, CCxP = 0,$	CCxNE=0, CCxN	IP=0,			=0 or		(xN=1)

30.4.16 Bidirectional break input

The TIM15/TIM16/TIM17 are featuring bidirectional break I/Os, as represented on Figure 471.

They are used to have:

A board-level global break signal available for signaling faults to external MCUs or gate drivers, with a unique pin being both an input and an output status pin

Internal break sources and multiple external open drain sources ORed together to trigger a unique break event, when multiple internal and external break sources must be merged

The tim_brk input is configured in bidirectional mode using the BKBID bit in the TIMxBDTR register. The BKBID programming bit can be locked in read-only mode using the LOCK bits in the TIMxBDTR register (in LOCK level 1 or above).

The bidirectional mode requires the I/O to be configured in open-drain mode with active low polarity (using BKINP and BKP bits). Any break request coming either from system (for example CSS), from on-chip peripherals or from break inputs forces a low level on the break input to signal the fault event. The bidirectional mode is inhibited if the polarity bits are not correctly set (active high polarity), for safety purposes.

The break software event (triggered by setting the BG bit) also causes the break I/O to be forced to ' 0 ' to indicate to the external components that the timer has entered in break state. However,this is valid only if the break is enabled

(BKE = 1)

. When a software break event is generated with

BKE = 0

,the outputs are put in safe state and the break flag is set,but there is no effect on the TIM_BKIN I/O.

A safe disarming mechanism prevents the system to be definitively locked-up (a low level on the break input triggers a break which enforces a low level on the same input).

When the BKDSRM bit is set to 1 , this releases the break output to clear a fault signal and to give the possibility to re-arm the system.

At no point the break protection circuitry can be disabled:

The break input path is always active: a break event is active even if the BKDSRM bit is set and the open drain control is released. This prevents the PWM output to be restarted as long as the break condition is present.

The BKDSRM bit cannot disarm the break protection as long as the outputs are enabled (MOE bit is set) (see Table 297)

Table 297. Break protection disarming conditions

MOE	BKBID	BKDSRM	Break protection state
0	0	X	Armed
0	1	0	Armed
0	1	1	Disarmed
1	$x$	$x$	Armed

Arming and re-arming break circuitry

The break circuitry (in input or bidirectional mode) is armed by default (peripheral reset configuration).

The following procedure must be followed to re-arm the protection after a break event:

The BKDSRM bit must be set to release the output control

The software must wait until the system break condition disappears (if any) and clear the SBIF status flag (or clear it systematically before re-arming)

The software must poll the BKDSRM bit until it is cleared by hardware (when the application break condition disappears)

From this point, the break circuitry is armed and active, and the MOE bit can be set to reenable the PWM outputs.

Figure 471. Output redirection

30.4.17 Clearing the tim_ocxref signal on an external event

The tim_ocref_clr_int input can be selected among several inputs, as shown on Figure 472 below.

Figure 472. tim_ocref_clr input selection multiplexer

30.4.18 6-step PWM generation

When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. Thus one can program in advance the configuration for the next step and change the configuration of all the channels at the same time. COM can be generated by software by setting the COM bit in the TIMx_EGR register or by hardware (on tim_trgi rising edge).

A flag is set when the COM event occurs (COMIF bit in the TIMx_SR register), which can generate an interrupt (if the COMIE bit is set in the TIMx_DIER register) or a DMA request (if the COMDE bit is set in the TIMx_DIER register).

The Figure 473 describes the behavior of the tim_ocx and tim_ocxn outputs when a COM

event occurs, in 3 different examples of programmed configurations.

30.4.19 One-pulse mode

A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be:

$CNT < CCRx \leq ARR$ (in particular, $0 < CCRx$ )

Figure 474. Example of one pulse mode.

For example one may want to generate a positive pulse on tim_oc1 with a length of

t_{PULSE}

and after a delay of

t_{DELAY}

as soon as a positive edge is detected on the tim_ti2 input pin.

Let's use tim_ti2fp2 as trigger 1:

Select the proper tim_ti2_in[15:1] source (internal or external) with the TI2SEL[3:0] bits in the TIMx_TISEL register.

Map tim_ti2fp2 to tim_ti2 by writing CC2S='01' in the TIMx_CCMR1 register.

tim_ti2fp2 must detect a rising edge,write $CC 2 P =^{'} 0^{'}$ and $CC 2 NP =^{'} 0^{'}$ in the TIMx_CCER register.

Configure tim_ti2fp2 as trigger for the slave mode controller (tim_trgi) by writing TS='00110' in the TIMx_SMCR register.

tim_ti2fp2 is used to start the counter by writing SMS to '110' in the TIMx_SMCR register (trigger mode).

The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler).

The $t_{DELAY}$ is defined by the value written in the TIMx_CCR1 register.

The $t_{PULSE}$ is defined by the difference between the auto-reload value and the compare value (TIMx_ARR - TIMx_CCR1).

Let's say one want to build a waveform with a transition from ' 0 ' to ' 1 ' when a compare match occurs and a transition from '1' to ' 0 ' when the counter reaches the auto-reload value. To do this PWM mode 2 must be enabled by writing OC1M=111 in the TIMx_CCMR1 register. Optionally the preload registers can be enabled by writing OC1PE='1' in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case one has to write the compare value in the TIMx_CCR1 register, the auto-reload value in the TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger event on tim_ti2. CC1P is written to ' 0 ' in this example.

Since only 1 pulse is needed, a 1 must be written in the OPM bit in the TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0 ).

Particular case: tim_ocx fast enable

t_{DELAY}

min we can get.

If one wants to output a waveform with the minimum delay, the OCxFE bit can be set in the TIMx_CCMRx register. Then tim_ocxref (and tim_ocx) are forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.

30.4.20 Retriggerable one pulse mode (TIM15 only)

The pulse starts as soon as the trigger occurs (no programmable delay)

The pulse is extended if a new trigger occurs before the previous one is completed

The timer must be in Slave mode,with the bits SMS[3:0]

=

’1000’ (Combined Reset + trigger mode) in the TIMx_SMCR register, and the OCxM[3:0] bits set to '1000' or '1001' for

If the timer is configured in Up-counting mode, the corresponding CCRx must be set to 0 (the ARR register sets the pulse length). If the timer is configured in Down-counting mode,

Note: The OCxM[3:0] and SMS[3:0] bit fields are split into two parts for compatibility reasons, the CMS[1:0] = 00 in TIMx_CR1.

Figure 475. Retriggerable one pulse mode

30.4.21 UIF bit remapping

The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the Update Interrupt Flag UIF into bit 31 of the timer counter register (TIMxCNT[31]). This is used to atomically read both the counter value and a potential roll-over condition signaled by the UIFCPY flag. In particular cases, it can ease the calculations by avoiding race conditions caused for instance by a processing shared between a background task (counter reading) and an interrupt (Update Interrupt).

There is no latency between the assertions of the UIF and UIFCPY flags.

30.4.22 Timer input XOR function (TIM15 only)

The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the two input pins tim_ti1 and tim_ti2.

The XOR output can be used with all the timer input functions such as trigger or input capture. It is useful for measuring the interval between the edges on two input signals, as shown in Figure 476.

Figure 476. Measuring time interval between edges on 2 signals

30.4.23 External trigger synchronization (TIM15 only)

The TIM timers are linked together internally for timer synchronization or chaining.

The TIM15 timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode, Trigger mode, Reset + trigger and gated + reset modes.

Slave mode: Reset mode

In the following example, the upcounter is cleared in response to a rising edge on tim_ti1 input:

Configure the channel 1 to detect rising edges on tim_ti1. Configure the input filter duration (in this example, we do not need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so it does not need to be configured. The CC1S bits select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write CC1P='0' and CC1NP='0' in the TIMx_CCER register to validate the polarity (and detect rising edges only).

Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select tim_ti1 as the input source by writing TS=00101 in TIMx_SMCR register.

Start the counter by writing CEN=1 in the TIMx_CR1 register.

The counter starts counting on the internal clock, then behaves normally until tim_ti1 rising edge. When tim_ti1 rises, the counter is cleared and restarts from 0 . In the meantime, the trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).

Figure 477. Control circuit in reset mode

Slave mode: Gated mode

The counter can be enabled depending on the level of a selected input.

In the following example, the upcounter counts only when tim_ti1 input is low:

Configure the channel 1 to detect low levels on tim_ti1. Configure the input filter duration (in this example, we do not need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so it does not need to be configured. The CC1S bits select the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write CC1P=1 and CC1NP = '0' in the TIMx_CCER register to validate the polarity (and detect low level only).

Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select tim_ti1 as the input source by writing TS=00101 in TIMx_SMCR register.

Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the counter doesn't start if $CEN = 0$ ,whatever is the trigger input level).

The delay between the rising edge on tim_ti1 and the actual stop of the counter is due to the resynchronization circuit on tim_ti1 input.

Figure 478. Control circuit in gated mode

Slave mode: Trigger mode

The counter can start in response to an event on a selected input.

In the following example, the upcounter starts in response to a rising edge on tim_ti2 input:

Configure the channel 2 to detect rising edges on tim_ti2. Configure the input filter duration (in this example, we do not need any filter, so we keep IC2F=0000). The capture prescaler is not used for triggering, so it does not need to be configured. The CC2S bits are configured to select the input capture source only, CC2S=01 in TIMx_CCMR1 register. Write CC2P='1' and CC2NP='0' in the TIMx_CCER register to validate the polarity (and detect low level only).

Configure the timer in trigger mode by writing SMS=110 in the TIMx_SMCR register. Select tim_ti2 as the input source by writing TS=00110 in the TIMx_SMCR register.

When a rising edge occurs on tim_ti2, the counter starts counting on the internal clock and the TIF flag is set.

The delay between the rising edge on tim_ti2 and the actual start of the counter is due to the resynchronization circuit on tim_ti2 input.

Figure 479. Control circuit in trigger mode

Slave mode selection preload for run-time update

30.4.24 Slave mode – combined reset + trigger mode (TIM15 only)

In this case, a rising edge of the selected trigger input (tim_trgi) reinitializes the counter, generates an update of the registers, and starts the counter.

This mode is used for one-pulse mode.

30.4.25 Slave mode combined reset + gated mode (TIM15 only)

The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops and is reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.

This mode is used to detect out-of-range PWM signal (duty cycle exceeding a maximum expected value).

30.4.26 Timer synchronization (TIM15 only)

The TIMx timers are linked together internally for timer synchronization or chaining. Refer to Section 29.4.23: Timer synchronization for details.

30.4.27 Using timer output as trigger for other timers (TIM16/TIM17 only)

The timers with one channel only do not feature a master mode. However, the OC1 output signal can be used to trigger some other timers (including timers described in other sections of this document). Check the "TIMx internal trigger connection" table of any timer on the device to identify which timers can be targeted as slave.

The OC1 signal pulse width must be programmed to be at least 2 clock cycles of the destination timer, to make sure the slave timer detects the trigger.

For instance, if the destination's timer CK_INT clock is 4 times slower than the source timer, the OC1 pulse width must be 8 clock cycles.

30.4.28 ADC triggers (TIM15 only)

The timer can generate an ADC triggering event with various internal signals, such as reset, enable or compare events.

30.4.29 DMA burst mode

The TIMx timers have the capability to generate multiple DMA requests on a single event. The main purpose is to be able to re-program several timer registers multiple times without software overhead, but it can also be used to read several registers in a row, at regular intervals.

Example:

00000: TIMx_CR1,

00001: TIMx_CR2,

00010: TIMx_SMCR,

For example, the timer DMA burst feature can be used to update the contents of the CCRx registers

(x = 2, 3, 4)

on an update event,with the DMA transferring half words into the CCRx registers.

This is done in the following steps:

Configure the corresponding DMA channel as follows:

DMA channel peripheral address is the DMAR register address

DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into the CCRx registers.

Number of data to transfer $= 3$ (See note below).

Circular mode disabled.

Configure the DCR register by configuring the DBA and DBL bit fields as follows: $DBL = 3$ transfers, $DBA = 0 xE$ .

Enable the TIMx update DMA request (set the UDE bit in the DIER register).

Enable TIMx

Enable the DMA channel

This example is for the case where every CCRx register is to be updated once. If every CCRx register is to be updated twice for example, the number of data to transfer must be 6 . Let's take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and data6. The data is transferred to the CCRx registers as follows: on the first update DMA request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is transferred to CCR3 and data6 is transferred to CCR4.

Note:

A null value can be written to the reserved registers.

30.4.30 TIM15/TIM16/TIM17 DMA requests

The TIM15/TIM16/TIM17 can generate a DMA requests, as shown in Table 298.

Table 298. DMA request

DMA request signal	DMA acronym	DMA request	Enable control bit
tim_upd_dma	TIM_UP	Update	UDE
tim_cc1_dma	TIM_CH1	Capture/compare 1	CC1DE
tim_com_dma(1)	TIM_COM	Commutation (COM)	COMDE
tim_trg_dma(1)	TIM_TRIG	Trigger	TDE

Available for TIM15 only.

30.4.31 Debug mode

When the microcontroller enters debug mode (Cortex

^{®}

-M4 with FPU core halted),the TIMx counter can either continue to work normally or stop.

The behavior in debug mode can be programmed with a dedicated configuration bit per timer in the Debug support (DBG) module.

For safety purposes, when the counter is stopped, the outputs are disabled (as if the MOE bit was reset). The outputs can either be forced to an inactive state (OSSI bit

= 1

),or have their control taken over by the GPIO controller (OSSI bit

= 0

) to force them to Hi-Z.

For more details, refer to the debug section.

30.5 TIM15/TIM16/TIM17 low-power modes

Table 299. Effect of low-power modes on TIM15/TIM16/TIM17

Mode	Description
Sleep	No effect, peripheral is active. The interrupts can cause the device to exit from Sleep mode.
Stop	The timer operation is stopped and the register content is kept. No interrupt can be generated.
Standby	The timer is powered-down and must be reinitialized after exiting the Standby mode

30.6 TIM15/TIM16/TIM17 interrupts

The TIM15/TIM16/TIM17 can generate multiple interrupts, as shown in Table 300.

Table 300. Interrupt requests

Interrupt acronym	Interrupt event	Event flag	Enable control bit	Interrupt clear method	Exit from Sleep mode	Exit from Stop and Standby mode
TIM	Update	UIF	UIE	write 0 in UIF	Yes	No
	Capture/compare 1	CC1IF	CC1IE	write 0 in CC1IF	Yes	No
	Capture/compare 2(1)	CC21F	CC2IE	write 0 in CC2IF	Yes	No
	Commutation (COM)	COMIF	COMIE	write 0 in COMIF	Yes	No
	Trigger(1)	TIF	TIE	write 0 in TIF	Yes	No
	Break	BIF	BIE	write 0 in BIF	Yes	No

Available for TIM15 only.

30.7 TIM15 registers

Refer to Section 1.2 for a list of abbreviations used in register descriptions.

30.7.1 TIM15 control register 1 (TIM15_CR1)

Address offset: 0x00

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	DITH EN	UIFRE MAP	Res.	CKD[1:0]		ARPE	Res.	Res.	Res:	OPM	URS	UDIS	CEN
			rw	rw		rw	rw	rw				rw	rw	rw	rw

Bits 15:13 Reserved, must be kept at reset value.

Bit 12 DITHEN: Dithering enable

0 : Dithering disabled

1: Dithering enabled

Note: The DITHEN bit can only be modified when CEN bit is reset.

Bit 11 UIFREMAP: UIF status bit remapping

0: No remapping. UIF status bit is not copied to TIM15_CNT register bit 31.

1: Remapping enabled. UIF status bit is copied to TIM15_CNT register bit 31.

Bit 10 Reserved, must be kept at reset value.

Bits 9:8 CKD[1:0]: Clock division

This bitfield indicates the division ratio between the timer clock (tim_ker_ck) frequency and the dead-time and sampling clock

(t_{DTS})

used by the dead-time generators and the digital filters (tim_tix)

00:

t_{DTS} = t_{tim_\ker_ck}

01 : t_{DTS} = 2^{*} t_{tim_\ker_ck}^{-}

10:

t_{DTS} = 4^{*} t_{tim_\ker_ck}

11: Reserved

Bit 7 ARPE: Auto-reload preload enable

0: TIM15_ARR register is not buffered

1: TIM15_ARR register is buffered

Bits 6:4 Reserved, must be kept at reset value.

Bit 3 OPM: One-pulse mode

0 : Counter is not stopped at update event

1: Counter stops counting at the next update event (clearing the bit CEN)

Bit 2 URS: Update request source

This bit is set and cleared by software to select the UEV event sources.

0 : Any of the following events generate an update interrupt if enabled. These events can be:

Counter overflow/underflow

Setting the UG bit

Update generation through the slave mode controller

1: Only counter overflow/underflow generates an update interrupt if enabled

Bit 1 UDIS: Update disable

This bit is set and cleared by software to enable/disable UEV event generation.

0:UEV enabled. The Update (UEV) event is generated by one of the following events:

Counter overflow/underflow

Setting the UG bit

Update generation through the slave mode controller

Buffered registers are then loaded with their preload values.

1:UEV disabled. The Update event is not generated, shadow registers keep their value

(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is

set or if a hardware reset is received from the slave mode controller.

Bit 0 CEN: Counter enable

0 : Counter disabled

1: Counter enabled

Note: External clock and gated mode can work only if the CEN bit has been previously set by

software. However trigger mode can set the CEN bit automatically by hardware.

30.7.2 TIM15 control register 2 (TIM15_CR2)

Address offset: 0x04

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	OIS2	OIS1N	OIS1	TI1S	MMS[2:0]			CCDS	CCUS	Res.	CCPC
					rw	rw	rw	rw	rw	rw	rw	rw	rw		rw

Bits 15:11 Reserved, must be kept at reset value.

Bit 10 OIS2: Output idle state 2 (tim_oc2 output)

0: tim_oc2=0 when MOE=0

1: tim_oc2=1 when

MOE = 0

Note: This bit cannot be modified as long as LOCK level 1,2 or 3 has been programmed

(LOCK bits in the TIM15_BKR register).

Bit 9 OIS1N: Output Idle state 1 (tim_oc1n output)

0: tim_oc1n=0 after a dead-time when MOE=0

tim_oc 1 n = 1

after a dead-time when

MOE = 0

Note: This bit can not be modified as long as LOCK level 1,2 or 3 has been programmed

(LOCK bits in TIM15_BKR register).

Bit 8 OIS1: Output Idle state 1 (tim_oc1 output)

0: tim_oc1=0 after a dead-time when MOE=0

1: tim_oc1=1 after a dead-time when

MOE = 0

Note: This bit can not be modified as long as LOCK level 1,2 or 3 has been programmed

(LOCK bits in TIM15_BKR register).

Bit 7 TI1S: tim_ti1 selection

0: The tim_ti1_in[15:0] multiplexer output is connected to tim_ti1 input

1: The tim_ti1_in[15:0] and tim_ti2_in[15:0] multiplexers output are connected to the tim_ti1

input (XOR combination)

Bits 6:4 MMS[2:0]: Master mode selection

These bits are used to select the information to be sent in master mode to slave timers for synchronization (tim_trgo). The combination is as follows:

000: Reset - the UG bit from the TIM15_EGR register is used as trigger output (tim_trgo). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on tim_trgo is delayed compared to the actual reset.

001: Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on tim_trgo, except if the master/slave mode is selected (see the MSM bit description in TIM15_SMCR register).

010: Update - The update event is selected as trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer.

011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo).

100: Compare - tim_oc1refc signal is used as trigger output (tim_trgo).

101: Compare - tim_oc2refc signal is used as trigger output (tim_trgo).

Bit 3 CCDS: Capture/compare DMA selection

0: CCx DMA request sent when CCx event occurs

1: CCx DMA requests sent when update event occurs

Bit 2 CCUS: Capture/compare control update selection

0:When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only.

1:When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on tim_trgi.

Note: This bit acts only on channels that have a complementary output.

Bit 1 Reserved, must be kept at reset value.

Bit 0 CCPC: Capture/compare preloaded control

0:CCxE, CCxNE and OCxM bits are not preloaded

1:CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on tim_trgi, depending on the CCUS bit).

Note: This bit acts only on channels that have a complementary output.

30.7.3 TIM15 slave mode control register (TIM15_SMCR)

Address offset: 0x08

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res	SMSPE	Res.	Res	TS[4:3]		Res.	Res	Res.	SMS[3]
							rw			rw	rw				rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	MSM	TS[2:0]			Res.	SMS[2:0]
								rw	rw	rw	rw		rw	rw	rw

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 SMSPE: SMS preload enable

This bit selects whether the SMS[3:0] bitfield is preloaded.

0: SMS[3:0] bitfield is not preloaded

1: SMS[3:0] preload is enabled

Bits 23:22 Reserved, must be kept at reset value.

Bits 19:17 Reserved, must be kept at reset value.

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 MSM: Master/slave mode

0: No action

Bits

21, 20, 6, 5, 4

TS[4:0]: Trigger selection

This bit field selects the trigger input to be used to synchronize the counter.

00000: Internal Trigger 0 (tim_itr0)

00001: Internal Trigger 1 (tim_itr1)

00010: Internal Trigger 2 (tim_itr2)

00011: Internal Trigger 3 (tim_itr3)

00100: tim_ti1 Edge Detector (tim_ti1f_ed)

00101: Filtered Timer Input 1 (tim_ti1fp1)

00110: Filtered Timer Input 2 (tim_ti2fp2)

00111: Reserved

01000: Internal Trigger 4 (tim_itr4)

01001: Internal Trigger 5 (tim_itr5)

01010: Internal Trigger 6 (tim_itr6)

01011: Internal Trigger 7 (tim_itr7)

01100: Internal Trigger 8 (tim_itr8)

01101: Internal Trigger 9 (tim_itr9)

01110: Internal Trigger 10 (tim_itr10)

10000: Internal trigger 12 (tim_itr12)

10001: Internal trigger 13 (tim_itr13)

10010: Internal trigger 14 (tim_itr14)

10011: Internal trigger 15 (tim_itr15)

Others: Reserved

See Section 30.4.2: TIM15/TIM16/TIM17 pins and internal signals for more details on

tim_itrx meaning for each timer.

Note: These bits must be changed only when they are not used (for example when SMS=000) to avoid wrong edge detections at the transition.

Bit 3 Reserved, must be kept at reset value.

Bits $16, 2, 1, 0$ SMS[3:0]: Slave mode selection

When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (refer to ETP bit in TIMx_SMCR for tim_etr_in and

CCxP/CCxNP bits in TIMx_CCER register for tim_ti1fp1 and tim_ti2fp2).

0000: Slave mode disabled - if CEN = '1' then the prescaler is clocked directly by the internal clock.

0001: Reserved

0010: Reserved

0011: Reserved

0100: Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers.

0110: Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). Only the start of the counter is controlled.

0111: External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter.

1000: Combined reset + trigger mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter, generates an update of the registers and starts the counter.

Others: Reserved.

Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS='00100'). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal.

30.7.4 TIM15 DMA/interrupt enable register (TIM15_DIER)

Address offset: 0x0C

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	TDE	COMD E	Res.	Res.	Res.	CC1DE	UDE	BIE	TIE	COMIE	Res.	Res.	CC2IE	CC1IE	UIE
	rw	rw				rw	rw	rw	rw	rw			rw	rw	rw

Bit 15 Reserved, must be kept at reset value.

Bit 14 TDE: Trigger DMA request enable

0: Trigger DMA request disabled

1: Trigger DMA request enabled

Bit 13 COMDE: COM DMA request enable

0: COM DMA request disabled

1: COM DMA request enabled

Bits 12:10 Reserved, must be kept at reset value.

Bit 9 CC1DE: Capture/Compare 1 DMA request enable

0: CC1 DMA request disabled

1: CC1 DMA request enabled

Bit 8 UDE: Update DMA request enable

0: Update DMA request disabled

1: Update DMA request enabled

Bit 7 BIE: Break interrupt enable

0: Break interrupt disabled

1: Break interrupt enabled

Bit 6 TIE: Trigger interrupt enable

0: Trigger interrupt disabled

1: Trigger interrupt enabled

Bit 5 COMIE: COM interrupt enable

0: COM interrupt disabled

1: COM interrupt enabled

Bits 4:3 Reserved, must be kept at reset value.

Bit 2 CC2IE: Capture/Compare 2 interrupt enable

0: CC2 interrupt disabled

1: CC2 interrupt enabled

Bit 1 CC1IE: Capture/Compare 1 interrupt enable

0: CC1 interrupt disabled

1: CC1 interrupt enabled

Bit 0 UIE: Update interrupt enable

0 : Update interrupt disabled

1: Update interrupt enabled

30.7.5 TIM15 status register (TIM15_SR)

Address offset: 0x10

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	CC20F	CC10F	Res.	BIF	TIF	COMIE	Res.	Res.	CC2IF	CC1IF	UIF
					rc_w0	rc_w0		rc_w0	rc_w0	rc_w0			rc_w0	rc_w0	rc_w0

Bits 15:11 Reserved, must be kept at reset value.

Bit 10 CC2OF: Capture/Compare 2 overcapture flag

Refer to CC1OF description

Bit

9

CC10F: Capture/Compare 1 overcapture flag

This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ’ 0 ’.

0 : No overcapture has been detected

1: The counter value has been captured in TIM15_CCR1 register while CC1IF flag was already set

Bit 8 Reserved, must be kept at reset value.

Bit 7 BIF: Break interrupt flag

This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.

0 : No break event occurred

1: An active level has been detected on the break input

Bit 6 TIF: Trigger interrupt flag

This flag is set by hardware on the TRG trigger event (active edge detected on tim_trgi input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is set when the counter starts or stops when gated mode is selected. It is cleared by software.

0 : No trigger event occurred

1: Trigger interrupt pending

Bit 5 COMIF: COM interrupt flag

This flag is set by hardware on a COM event (once the capture/compare control bits

- CCxE

, CCxNE, OCxM- have been updated). It is cleared by software.

0: No COM event occurred

1: COM interrupt pending

Bits 4:3 Reserved, must be kept at reset value.

Bit 2 CC2IF: Capture/Compare 2 interrupt flag

refer to CC1IF description

Bit 1 CC1IF: Capture/Compare 1 interrupt flag

This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only).

0 : No compare match / No input capture occurred

1: A compare match or an input capture occurred

Bit 0 UIF: Update interrupt flag

This bit is set by hardware on an update event. It is cleared by software.

0 : No update occurred.

1: Update interrupt pending. This bit is set by hardware when the registers are updated:

At overflow regarding the repetition counter value (update if repetition counter $= 0$ ) and if the UDIS=0 in the TIM15_CR1 register.

When CNT is reinitialized by software using the UG bit in TIM15_EGR register, if URS=0 and UDIS=0 in the TIM15_CR1 register.

When CNT is reinitialized by a trigger event (refer to Section 30.7.3: TIM15 slave mode control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIM15_CR1 register.

30.7.6 TIM15 event generation register (TIM15_EGR)

Address offset: 0x14

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res	Res.	BG	TG	COMG	Res.	Res.	CC2G	CC1G	UG
								w	w	rw			w	w	w

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 BG: Break generation

This bit is set by software in order to generate an event, it is automatically cleared by hardware.

0: No action

1:A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled.

Bit 6 TG: Trigger generation

This bit is set by software in order to generate an event, it is automatically cleared by hardware.

0: No action

1:The TIF flag is set in TIM15_SR register. Related interrupt or DMA transfer can occur if enabled

Bit 5 COMG: Capture/Compare control update generation

This bit can be set by software, it is automatically cleared by hardware.

0 : No action

1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits

Note: This bit acts only on channels that have a complementary output.

Bits 4:3 Reserved, must be kept at reset value.

Bit 2 CC2G: Capture/Compare 2 generation

Refer to CC1G description

Bit 1 CC1G: Capture/Compare 1 generation

This bit is set by software in order to generate an event, it is automatically cleared by

hardware.

0: No action

1 A capture/compare event is generated on channel 1:

If channel CC1 is configured as output:

CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.

If channel CC1 is configured as input:

The current value of the counter is captured in TIM15_CCR1 register. The CC1IF flag is

set, the corresponding interrupt or DMA request is sent if enabled. The CC10F flag is set

if the CC1IF flag was already high.

Bit 0 UG: Update generation

This bit can be set by software, it is automatically cleared by hardware.

0: No action

1:Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected).

30.7.7 TIM15 capture/compare mode register 1 (TIM15_CCMR1)

Address offset: 0x18

Reset value: 0x00000000

7		1.0	TZ		10			7	0		4	0	4		0
IC2F[3:0]				IC2PSC[1:0]		CC2S[1:0]		IC1F[3:0]				IC1PSC[1:0]		CC1S[1:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Input capture mode

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:12 IC2F[3:0]: Input capture 2 filter

Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler

Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC2 channel is configured as output

01: CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2

10: CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1

11: CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an

internal trigger input is selected through TS bit (TIM15_SMCR register)

Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIM15_CCER).

(TIM15_CCMR1)

Bits 7:4 IC1F[3:0]: Input capture 1 filter

This bit-field defines the frequency used to sample tim_ti1 input and the length of the digital filter applied to tim_ti1. The digital filter is made of an event counter in which

N

consecutive events are needed to validate a transition on the output:

0000: No filter,sampling is done at

f_{D T S}

0001 : f_{SAMPLING = f_{tim_\ker_ck}, N = 2}

0010:

f_{SAMPLING} = f_{tim_ker_ck}, N = 4

0011:

f_{SAMPLING} = f_{tim_ker_ck}, N = 8

0100 : f_{SAMPLING} = f_{DTS} / 2, N = 6

0101 : f_{SAMPLING} = f_{DTS} / 2, N = 8

0110 : f_{SAMPLING} = f_{DTS} / 4, N = 6

0111 : f_{SAMPLING} = f_{DTS} / 4, N = 8

1000:

f_{SAMPLING} = f_{DTS} / 8, N = 6

1001 : f_{SAMPLING} = f_{DTS} / 8, N = 8

1010:

f_{SAMPLING} = f_{DTS} / 16, N = 5

1011:

f_{SAMPLING} = f_{DTS} / 16, N = 6

1100:

f_{SAMPLING} = f_{DTS} / 16, N = 8

1101:

f_{SAMPLING} = f_{DTS} / 32, N = 5

1110:

f_{SAMPLING} = f_{DTS} / 32, N = 6

1111:

f_{SAMPLING} = f_{DTS} / 32, N = 8

Bits 3:2 IC1PSC[1:0]: Input capture 1 prescaler

This bit-field defines the ratio of the prescaler acting on CC1 input (tim_ic1). The prescaler is reset as soon as CC1E='0' (TIM15_CCER register).

00 : no prescaler, capture is done each time an edge is detected on the capture input

01: capture is done once every 2 events

10: capture is done once every 4 events

11: capture is done once every 8 events

Bits 1:0 CC1S[1:0]: Capture/Compare 1 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC1 channel is configured as output

01: CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1

10: CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2

11: CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIM15_SMCR register)

Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIM15_CCER).

30.7.8 TIM15 capture/compare mode register 1 [alternate]

Address offset: 0x18

Reset value: 0x00000000

Output compare mode:

Bits 31:25 Reserved, must be kept at reset value.

Bits 23:17 Reserved, must be kept at reset value.

Bit 15 OC2CE: Output compare 2 clear enable

Bits 24, 14:12 OC2M[3:0]: Output compare 2 mode

Bit 11 OC2PE: Output compare 2 preload enable

Bit 10 OC2FE: Output compare 2 fast enable

Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC2 channel is configured as output.

01: CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2.

10: C2 channel is configured as input, tim_ic2 is mapped on tim_ti1.

11: CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working

only if an internal trigger input is selected through the TS bit (TIM15_SMCR register)

Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIM15_CCER).

Bit 7 OC1CE: Output compare 1 clear enable

0: tim_oc1ref is not affected by the tim_ocref_clr_int input.

1: tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int input.

Bits 16, 6:4 OC1M[3:0]: Output compare 1 mode

These bits define the behavior of the output reference signal tim_oc1ref from which tim_oc1 and tim_oc1n are derived. tim_oc1ref is active high whereas tim_oc1 and tim_oc1n active level depends on CC1P and CC1NP bits.

0000: Frozen - The comparison between the output compare register TIM15_CCR1 and the counter TIM15_CNT has no effect on the outputs. This mode can be used when the timer serves as a software timebase. When the frozen mode is enabled during timer operation, the output keeps the state (active or inactive) it had before entering the frozen state.

0001: Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIM15_CNT matches the capture/compare register 1 (TIM15_CCR1).

0010: Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIM15_CNT matches the capture/compare register 1 (TIM15_CCR1).

0011: Toggle - tim_oc1ref toggles when TIM15_CNT=TIM15_CCR1.

0100: Force inactive level - tim_oc1ref is forced low.

0101: Force active level - tim_oc1ref is forced high.

0110: PWM mode 1 - Channel 1 is active as long as TIM15_CNT

0111: PWM mode 2 - Channel 1 is inactive as long as TIM15_CNT

1010: Reserved

1011: Reserved

1100: Combined PWM mode 1 - tim_oc1ref has the same behavior as in PWM mode 1. tim_oc1refc is the logical OR between tim_oc1ref and tim_oc2ref.

1101: Combined PWM mode 2 - tim_oc1ref has the same behavior as in PWM mode 2. tim_oc1refc is the logical AND between tim_oc1ref and tim_oc2ref.

1110: Reserved,

1111: Reserved,

Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIM15_BDTR register) and CC1S=’00’ (the channel is configured in output). In PWM mode, the OCREF level changes when the result of the comparison changes, when the output compare mode switches from "frozen" mode to "PWM" mode and when the output compare mode switches from "force active/inactive" mode to "PWM" mode.

On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIM15_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated.

0:Preload register on TIM15_CCR1 disabled. TIM15_CCR1 can be written at anytime, the new value is taken in account immediately.

1:Preload register on TIM15_CCR1 enabled. Read/Write operations access the preload register. TIM15_CCR1 preload value is loaded in the active register at each update event.

Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIM15_BDTR register) and CC1S=’00’ (the channel is configured in output).

Bit 2 OC1FE: Output Compare 1 fast enable

0:CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles.

1:An active edge on the trigger input acts like a compare match on CC1 output. Then, tim_ocx is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode.

Bits 1:0 CC1S[1:0]: Capture/Compare 1 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC1 channel is configured as output.

01: CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1.

10: CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2.

11: CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIM15_SMCR register)

Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIM15_CCER).

30.7.9 TIM15 capture/compare enable register (TIM15_CCER)

Address offset: 0x20

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	CC2NP	Res.	CC2P	CC2E	CC1NP	CC1NE	CC1P	CC1E
								rw		rw	rw	rw	rw	rw	rw

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 CC2NP: Capture/Compare 2 complementary output polarity Refer to CC1NP description

Bit 6 Reserved, must be kept at reset value.

Bit 5 CC2P: Capture/Compare 2 output polarity Refer to CC1P description

Bit 4 CC2E: Capture/Compare 2 output enable Refer to CC1E description

Bit 3 OC1PE: Output Compare 1 preload enable

Bit

3

CC1NP: Capture/Compare 1 complementary output polarity

CC1 channel configured as output:

0: tim_oc1n active high

1: tim_oc1n active low

CC1 channel configured as input:

This bit is used in conjunction with CC1P to define the polarity of tim_ti1fp1 and tim_ti2fp1. Refer to CC1P description.

Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register) and CC1S=”00” (the channel is configured in output).

On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIM15_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated.

Bit 2 CC1NE: Capture/Compare 1 complementary output enable

0:Off - tim_oc1n is not active. tim_oc1n level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.

1:On - tim_oc1n signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.

Bit 1 CC1P: Capture/Compare 1 output polarity

CC1 channel configured as output:

0: OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)

1: OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)

When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations.

CC 1 NP = 0, CC 1 P = 0

: non-inverted/rising edge. The circuit is sensitive to TlxFP1 rising edge

(capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode).

CC 1 NP = 0, CC 1 P = 1

: inverted/falling edge. The circuit is sensitive to TlxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode).

CC 1 NP = 1, CC 1 P = 1

: non-inverted/both edges/The circuit is sensitive to both TlxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode).

CC 1 NP = 1, CC 1 P = 0

: this configuration is reserved,it must not be used.

Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register).

On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIM15_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated.

Bit 0 CC1E: Capture/Compare 1 output enable

0: Capture mode disabled / OC1 is not active (see below)

1: Capture mode enabled / OC1 signal is output on the corresponding output pin

When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to Table 301 for details.

Table 301. Output control bits for complementary tim_ocx and tim_ocxn channels with break feature (TIM15)

Control bits					Output states(1)
MOE bit	OSSI bit	OSSR bit	CCxE bit	CCxNE bit	tim_ocx output state	tim_ocxn output state
1	X	X	0	0	Output Disabled (not driven by the timer: Hi-Z) tim_ocx=0 tim_ocxn=0
		0	0	1	Output Disabled (not driven by the timer: Hi-Z) tim_ocx=0	tim ocxref + Polarity tim_ocxn=tim_ocxref XOR CCxNP
		0	1	0	tim ocxref + Polarity tim_ocx=tim_ocxref XOR CCxP	Output Disabled (not driven by the timer: Hi-Z) tim_ocxn=0
		X	1	1	tim ocxref + Polarity + dead-time	Complementary to tim_ocxref (not OCREF) + Polarity + dead- time
		1	0	1	Off-State (output enabled with inactive state) tim $ocx = CCxP$	tim ocxref + Polarity tim ocxn=tim ocxref XOR CCxNP
		1	1	0	tim ocxref + Polarity tim_ocx=tim_ocxref xor CCxP	Off-State (output enabled with inactive state) tim ocxn=CCxNP
0	0	X	X	X	Output disabled (not driven by the timer: Hi-Z)
	1		0	0	Output disabled (not driven by the timer: Hi-Z)
			0	1	Off-State (output enabled with inactive state) Asynchronously: tim_ocx=CCxP, tim_ocxn=CCxNP Then if the clock is present: tim ocx=OISx and tim_ocxn=OISxN after a dead-time, assuming that OISx and OISxN do not correspond to tim_ocx and tim_ocxn both in active state
			1	0
			1	1

When both outputs of a channel are not used (control taken over by GPIO controller), the OISx, OISxN, CCxP and CCxNP bits must be kept cleared.

Note: The state of the external I/O pins connected to the complementary tim_ocx and tim_ocxn channels depends on the tim_ocx and tim_ocxn channel state and GPIO control and alternate function selection registers.

30.7.10 TIM15 counter (TIM15_CNT)

Address offset: 0x24

Reset value: 0x00000000

Bit 31 UIFCPY: UIF Copy

This bit is a read-only copy of the UIF bit in the TIM15_ISR register.

Bits 30:16 Reserved, must be kept at reset value.

Bits 15:0 CNT[15:0]: Counter value

Non-dithering mode (DITHEN = 0)

The register holds the counter value.

Dithering mode (DITHEN = 1)

The register only holds the non-dithered part in CNT[15:0]. The fractional part is not

available.

30.7.11 TIM15 prescaler (TIM15_PSC)

Address offset: 0x28

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0 PSC[15:0]: Prescaler value

The counter clock frequency

(f_{tim_cnt_ck})

is equal to

f_{tim_psc_ck} / (P S C [15 : 0] + 1)

PSC contains the value to be loaded in the active prescaler register at each update event

(including when the counter is cleared through UG bit of TIM15_EGR register or through

trigger controller when configured in "reset mode").

30.7.12 TIM15 auto-reload register (TIM15_ARR)

Address offset: 0x2C

Reset value: 0x0000 FFFF

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:0 ARR[19:0]: Auto-reload value

ARR is the value to be loaded in the actual auto-reload register.

Refer to the Section 30.4.3: Time-base unit on page 1361 for more details about ARR

update and behavior.

The counter is blocked while the auto-reload value is null.

Non-dithering mode (DITHEN = 0)

The register holds the auto-reload value in ARR[15:0]. The ARR[19:16] bits are reset.

Dithering mode (DITHEN = 1)

The register holds the integer part in

ARR [19 : 4]

. The

ARR [3 : 0]

bitfield contains the dithered part.

30.7.13 TIM15 repetition counter register (TIM15_RCR)

Address offset: 0x30

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	REP[7:0]
								rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:8 Reserved, must be kept at reset value.

Bits 7:0 REP[7:0]: Repetition counter reload value

This bitfield defines the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable. It also defines the update interrupt generation rate, if this interrupt is enable.

When the repetition down-counter reaches zero, an update event is generated and it restarts counting from REP value. As the reptition counter is reloaded with REP value only at the repetition update event UEV, any write to the TIM15_RCR register is not taken in account until the next repetition update event.

It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode:

the number of PWM periods in edge-aligned mode

the number of half PWM period in center-aligned mode

30.7.14 TIM15 capture/compare register 1 (TIM15_CCR1)

Address offset: 0x34

Reset value: 0x00000000

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:0 CCR1[19:0]: Capture/compare 1 value

If channel CC1 is configured as output:

CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIM15_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter TIM15_CNT and signaled on tim_oc1 output.

Non-dithering mode (DITHEN = 0)

The register holds the compare value in CCR1[15:0]. The CCR1[19:16] bits are reset. Dithering mode (DITHEN = 1)

The register holds the integer part in CCR1[19:4]. The CCR1[3:0] bitfield contains the dithered part.

If channel CC1 is configured as input:

CR1 is the counter value transferred by the last input capture 1 event (tim_ic1). The TIMx_CCR1 register is read-only and cannot be programmed.

Non-dithering mode (DITHEN = 0)

The register holds the capture value in CCR1[15:0]. The CCR1[19:16] bits are reset. Dithering mode (DITHEN = 1)

The register holds the capture in CCR1[19:4]. The CCR1[3:0] bits are reset.

30.7.15 TIM15 capture/compare register 2 (TIM15_CCR2)

Address offset: 0x38

Reset value: 0x00000000

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:0 CCR2[19:0]: Capture/compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIM15_CCMR2 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter TIM15_CNT and signalled on tim_oc2 output.

Non-dithering mode (DITHEN = 0)

The register holds the compare value in CCR2[15:0]. The CCR2[19:16] bits are reset. Dithering mode (DITHEN = 1)

The register holds the integer part in CCR2[19:4]. The CCR2[3:0] bitfield contains the dithered part.

If channel CC2 is configured as input:

CCR2 is the counter value transferred by the last input capture 1 event (tim_ic2). The

TIMx_CCR2 register is read-only and cannot be programmed.

Non-dithering mode (DITHEN = 0)

The register holds the capture value in CCR2[15:0]. The CCR2[19:16] bits are reset.

Dithering mode (DITHEN = 1)

The register holds the capture in CCR2[19:4]. The CCR2[3:0] bits are reset.

30.7.16 TIM15 break and dead-time register (TIM15_BDTR)

Address offset: 0x44

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	BKBID	Res.	BK DSRM	Res.	Res.	Res.	Res.	Res.	Res.	BKF[3:0]
			rw		rw							rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK[1:0]		DTG[7:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Note: As the BKBID, BKDSRM, BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits may be write-locked depending on the LOCK configuration, it may be necessary to configure all of them during the first write access to the TIM15_BDTR register.

Bits 31:29 Reserved, must be kept at reset value.

Bit 28 BKBID: Break bidirectional

0 : Break input tim_brk in input mode

1: Break input tim_brk in bidirectional mode

In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input

mode and in open drain output mode. Any active break event asserts a low logic level on the

Break input to indicate an internal break event to external devices.

Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register).

Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

Bit 27 Reserved, must be kept at reset value.

Bit 26 BKDSRM: Break disarm

0: Break input tim_brk is armed

1: Break input tim_brk is disarmed

This bit is cleared by hardware when no break source is active.

The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled until it is reset by hardware, indicating that the fault condition has disappeared.

Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

Bits 25:20 Reserved, must be kept at reset value.

Bits 19:16 BKF[3:0]: Break filter

This bit-field defines the frequency used to sample the tim_brk input signal and the length of the digital filter applied to tim_brk. The digital filter is made of an event counter in which

N

events are needed to validate a transition on the output:

0000: No filter, tim_brk acts asynchronously

0001 : f_{SAMPLING} = f_{tim_ker_ck}, N = 2

0010:

f_{SAMPLING} = f_{tim_ker_ck}, N = 4

0011:

f_{SAMPLING} = f_{tim_ker_ck}, N = 8

0100 : f_{SAMPLING} = f_{DTS} / 2, N = 6

0101:

f_{SAMPLING} = f_{DTS} / 2, N = 8

0110 : f_{SAMPLING} = f_{DTS} / 4, N = 6

0111 : f_{SAMPLING} = f_{DTS} / 4, N = 8

1000:

f_{SAMPLING} = f_{DTS} / 8, N = 6

1001:

f_{SAMPLING} = f_{DTS} / 8, N = 8

1010:

f_{SAMPLING} = f_{DTS} / 16, N = 5

1011:

f_{SAMPLING} = f_{DTS} / 16, N = 6

1100:

f_{SAMPLING} = f_{DTS} / 16, N = 8

1101:

f_{SAMPLING} = f_{DTS} / 32, N = 5

1110:

f_{SAMPLING} = f_{DTS} / 32, N = 6

1111:

f_{SAMPLING} = f_{DTS} / 32, N = 8

Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register).

Bit 15 MOE: Main output enable

This bit is cleared asynchronously by hardware as soon as the tim_brk input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output.

0:tim_ocx and tim_ocxn outputs are disabled or forced to idle state depending on the OSSI bit.

1: tim_ocx and tim_ocxn outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIM15_CCER register)

See tim_ocx/tim_ocxn enable description for more details (Section 30.7.9: TIM15

capture/compare enable register (TIM15_CCER) on page 1416).

Bit 14 AOE: Automatic output enable

0: MOE can be set only by software

1: MOE can be set by software or automatically at the next update event (if the break input is not be active)

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register).

Bit 13 BKP: Break polarity

0: Break input tim_brk is active low

1: Break input tim_brk is active high

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register).

Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

Bit 12 BKE: Break enable

0: Break inputs (tim_brk and tim_sys_brk clock failure event) disabled

1; Break inputs (tim_brk and tim_sys_brk clock failure event) enabled

This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in

TIM15_BDTR register).

Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

Bit 11 OSSR: Off-state selection for Run mode

This bit is used when

MOE = 1

on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer.

See tim_ocx/tim_ocxn enable description for more details (Section 30.7.9: TIM15

capture/compare enable register (TIM15_CCER) on page 1416).

0 . When inactive, tim_ocx/tim_ocxn outputs are disabled (the timer releases the output control which is taken over by the GPIO, which forces a Hi-Z state)

1: When inactive, tim_ocx/tim_ocxn outputs are enabled with their inactive level as soon as

CCxE = 1

CCxNE = 1

(the output is still controlled by the timer).

Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIM15_BDTR register).

Bit 10 OSSI: Off-state selection for Idle mode

This bit is used when

MOE = 0

on channels configured as outputs.

See tim_ocx/tim_ocxn enable description for more details (Section 30.7.9: TIM15

capture/compare enable register (TIM15_CCER) on page 1416).

0: When inactive, tim_ocx/tim_ocxn outputs are disabled (tim_ocx/tim_ocxn enable output signal=0)

1: When inactive, tim_ocx/tim_ocxn outputs are forced first with their idle level as soon as

CCxE = 1

CCxNE = 1

. tim_ocx/tim_ocxn enable output signal

= 1

)

Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIM15_BDTR register).

Bits 9:8 LOCK[1:0]: Lock configuration

These bits offer a write protection against software errors.

00: LOCK OFF - No bit is write protected

01: LOCK Level 1 = DTG bits in TIM15_BDTR register, OISx and OISxN bits in TIM15_CR2 register and BKBID/BKE/BKP/AOE bits in TIM15_BDTR register can no longer be written

10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIM15_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.

11: OCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIM15_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.

Note: The LOCK bits can be written only once after the reset. Once the TIM15_BDTR register has been written, their content is frozen until the next reset.

Bits 7:0 DTG[7:0]: Dead-time generator setup

This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration.

DTG [7 : 5] = 0 \times x => DT = DTG [7 : 0] \times t_{dtg}

with

t_{dtg} = t_{DTS}

DTG [7 : 5] = 10 x => DT = (64 + DTG [5 : 0]) \times t_{dtg}

with

T_{dtg} = 2 \times t_{DTS}

DTG [7 : 5] = 110 => DT = (32 + DTG [4 : 0]) {xt}_{dtg}

with

T_{dtg} = 8 {xt}_{DTS}

DTG [7 : 5] = 111 => DT = (32 + DTG [4 : 0]) \times t_{dtg}

with

T_{dtg} = 16 \times t_{DTS}

Example if

T_{D T S} = 125 ns (8 MHz)

,dead-time possible values are:

0 to 15875 ns by 125 ns steps,

16 μ s

31750 ns

250 ns

steps,

32 μ s

63 μ s

1 μ s

steps,

64 µs to

126 μ s

by 2 µs steps

Note: This bit-field can not be modified as long as LOCK level 1,2 or 3 has been programmed (LOCK bits in TIM15_BDTR register).

30.7.17 TIM15 timer deadtime register 2 (TIM15_DTR2)

Address offset: 0x054

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	DTPE	DTAE
														rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	DTGF[7:0]
								rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:18 Reserved, must be kept at reset value.

Bit 17 DTPE: Deadtime preload enable

0 : Deadtime value is not preloaded

1: Deadtime value preload is enabled

Note: This bit can not be modified as long as LOCK level 1,2 or 3 has been programmed (LOCK bits in TIM15_BDTR register).

Bit 16 DTAE: Deadtime asymmetric enable

0: Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register

1: Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits.

Note: This bit can not be modified as long as LOCK level 1,2 or 3 has been programmed (LOCK bits in TIM15_BDTR register).

Bits 15:8 Reserved, must be kept at reset value.

Bits 7:0 DTGF[7:0]: Dead-time falling edge generator setup

This bit-field defines the duration of the dead-time inserted between the complementary outputs, on the falling edge.

DTGF [7 : 5] = 0 x x => DTF = DTGF [7 : 0] x t_{dtg}

with

t_{dtg} = t_{DTS} .

DTGF [7 : 5] = 10 x => DTF = (64 + DTGF [5 : 0]) x t_{dtg}

with

T_{dtg} = 2 x t_{DTS}

DTGF [7 : 5] = 110 => DTF = (32 + DTGF [4 : 0]) \times t_{dtg}

with

T_{dtg} = 8 \times t_{DTS}

DTGF [7 : 5] = 111 => DTF = (32 + DTGF [4 : 0]) \times t_{dtg}

with

T_{dtg} = 16 \times t_{DTS}

Example if

T_{D T S} = 125 ns (8 MHz)

,dead-time possible values are:

0 to 15875 ns by 125 ns steps,

16 us to 31750 ns by 250 ns steps,

32 us to 63 us by 1 us steps,

64 us to 126 us by 2 us steps

Note: This bit-field can not be modified as long as LOCK level 1,2 or 3 has been programmed (LOCK bits in TIM15_BDTR register).

30.7.18 TIM15 input selection register (TIM15_TISEL)

Address offset: 0x5C

Reset value: 0x00000000

Res.	Res.	Res.	Res.	TI2SEL[3:0]				Res.	Res.	Res.	Res.	TI1SEL[3:0]
				rw	rw	rw	rw					rw	rw	rw	rw

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:8 TI2SEL[3:0]: selects tim_ti2_in[15:0] input

0000: TIM15_CH2 input (tim_ti2_in0)

0001: tim_ti2_in1

\dots

1111: tim_ti2_in15

Refer to Section 30.4.2: TIM15/TIM16/TIM17 pins and internal signals for interconnects list.

Bits 7:4 Reserved, must be kept at reset value.

Bits 3:0 TI1SEL[3:0]: selects tim_ti1_in[15:0] input

0000: TIM15_CH1 input (tim_ti1_in0)

0001: tim_ti1_in1

\dots

1111: tim_ti1_in15

Refer to Section 30.4.2: TIM15/TIM16/TIM17 pins and internal signals for interconnects list. 30.7.19 TIM15 alternate function register 1 (TIM15_AF1)

Address offset: 0x060

Reset value: 0x00000001

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.		BK CMP4P	BK CMP3P	BK CMP2P	BK CMP1P	BKINP	BK CMP8E	BK CMP7E	BK CMP6E	BK CMP5E	BK CMP4E	BK CMP3E	BK CMP2E	BK CMP1E	BKINE
		rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Refer to Section 30.4.2: TIM15/TIM16/TIM17 pins and internal signals for product specific implementation.

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 BKCMP4P: tim_brk_cmp4 input polarity

This bit selects the tim_brk_cmp4 input sensitivity. It must be programmed together with the BKP polarity bit.

0: tim_brk_cmp4 input is active high

1: tim_brk_cmp4 input is active low

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register).

Bit 12 BKCMP3P: tim_brk_cmp3 input polarity

This bit selects the tim_brk_cmp3 input sensitivity. It must be programmed together with the BKP polarity bit.

0: tim_brk_cmp3 input is active high

1: tim_brk_cmp3 input is active low

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register).

Bit 11 BKCMP2P: tim_brk_cmp2 input polarity

This bit selects the tim_brk_cmp2 input sensitivity. It must be programmed together with the BKP polarity bit.

0: tim_brk_cmp2 input is active high

1: tim_brk_cmp2 input is active low

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register).

Bit 10 BKCMP1P: tim_brk_cmp1 input polarity

This bit selects the tim_brk_cmp1 input sensitivity. It must be programmed together with the BKP polarity bit.

0: tim_brk_cmp1 input is active high

1: tim_brk_cmp1 input is active low

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register).

Bit 9 BKINP: TIMx_BKIN input polarity

This bit selects the TIMx_BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit.

0: TIMx_BKIN input is active high

1: TIMx_BKIN input is active low

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register).

Bit 8 BKCMP8E: tim_brk_cmp8 enable

This bit enables the tim_brk_cmp8 for the timer's tim_brk input. mdf_brkx output is 'ORed' with the other tim_brk sources.

0: tim_brk_cmp8 input disabled

1: tim_brk_cmp8 input enabled

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register).

Bit 7 BKCMP7E: tim_brk_cmp7 enable

This bit enables the tim_brk_cmp7 for the timer's tim_brk input. COMP7 output is 'ORed' with the other tim_brk sources.

0: tim_brk_cmp7 input disabled

1: tim_brk_cmp7 input enabled

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register).

Bit 6 BKCMP6E: tim_brk_cmp6 enable

This bit enables the tim_brk_cmp6 for the timer's tim_brk input. tim_brk_cmp6 output is 'ORed' with the other tim_brk sources.

0: tim_brk_cmp6 input disabled

1: tim_brk_cmp6 input enabled

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register).

Bit 5 BKCMP5E: tim_brk_cmp5 enable

This bit enables the tim_brk_cmp5 for the timer's tim_brk input. tim_brk_cmp5 output is 'ORed' with the other tim_brk sources.

0: tim_brk_cmp5 input disabled

1: tim_brk_cmp5 input enabled

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register).

Bit 4 BKCMP4E: tim_brk_cmp4 enable

This bit enables the tim_brk_cmp4 for the timer's tim_brk input. tim_brk_cmp4 output is 'ORed' with the other tim_brk sources.

0: tim_brk_cmp4 input disabled

1: tim_brk_cmp4 input enabled

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register).

Bit 3 BKCMP3E: tim_brk_cmp3 enable

This bit enables the tim_brk_cmp3 for the timer's tim_brk input. tim_brk_cmp3 output is

'ORed' with the other tim_brk sources.

0: tim_brk_cmp3 input disabled

1: tim_brk_cmp3 input enabled

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register).

Bit 2 BKCMP2E: tim_brk_cmp2 enable

This bit enables the tim_brk_cmp2 for the timer's tim_brk input. tim_brk_cmp2 output is 'ORed' with the other tim_brk sources.

0: tim_brk_cmp2 input disabled

1: tim_brk_cmp2 input enabled

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register).

Bit 1 BKCMP1E: tim_brk_cmp1 enable

This bit enables the tim_brk_cmp1 for the timer's tim_brk input. tim_brk_cmp1 output is 'ORed' with the other tim_brk sources.

0: tim_brk_cmp1 input disabled

1: tim_brk_cmp1 input enabled

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register).

Bit 0 BKINE: TIMx_BKIN input enable

This bit enables the TIMx_BKIN alternate function input for the timer's tim_brk input.

TIMx_BKIN input is 'ORed' with the other tim_brk sources.

0: TIMx_BKIN input disabled

1: TIMx_BKIN input enabled

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register).

30.7.20 TIM15 alternate function register 2 (TIM15_AF2)

Address offset: 0x064

Reset value: 0x00000000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:16 OCRSEL[2:0]: ocref_clr source selection

These bits select the ocref_clr input source.

000: tim_ocref_clr0

001: tim_ocref_clr1

010: tim_ocref_clr2

011: tim_ocref_clr3

100: tim_ocref_clr4

101: tim_ocref_clr5

110: tim_ocref_clr6

111: tim_ocref_clr7

Refer to Section 30.4.2: TIM15/TIM16/TIM17 pins and internal signals for product specific implementation.

Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM15_BDTR register).

Bits 15:0 Reserved, must be kept at reset value. 30.7.21 TIM15 DMA control register (TIM15_DCR)

Address offset: 0x3DC

Reset value: 0x00000000

Bits 31:13 Reserved, must be kept at reset value.

Bits 12:8 DBL[4:0]: DMA burst length

This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIM15_DMAR address).

00000: 1 transfer,

00001: 2 transfers,

00010: 3 transfers,

10001: 18 transfers.

Bits 7:5 Reserved, must be kept at reset value.

Bits 4:0 DBA[4:0]: DMA base address

This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIM15_DMAR address). DBA is defined as an offset starting from the address of the TIM15_CR1 register.

Example:

0000: TIM15_CR1,

00001: TIM15_CR2,

00010: TIM15_SMCR,

\dots

30.7.22 TIM15 DMA address for full transfer (TIM15_DMAR)

Address offset: 0x3E0

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DMAB[31:16]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:0 DMAB[31:0]: DMA register for burst accesses

A read or write operation to the DMAR register accesses the register located at the address (TIM15_CR1 address) + (DBA + DMA index) x 4

where TIM15_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIM15_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIM15_DCR).

30.7.23 TIM15 register map

TIM15 registers are mapped as 16-bit addressable registers as described in the table below:

Table 302. TIM15 register map and reset values

Offset	Register name	31	30	23	23	27	26	26	24	23	22	21	20	1	1	17	6	IS	4	1	12	11	10	9	8	7	6	5	4	3	2	1	O
0x00	TIM15_CR1	Proof.	PROM	PAR	13	3	3	For	1,050	a	1,010	Proof.	Suppose	PU	Problem 1.	3	Lift	3	REPT	For	3	VW38311		CKD [1:0]		AREE	PART	PART	E	Operation	Univ.	Univ.	CHF
0x00	Reset value																					0		0	0	0				0	0	0	0
0x04	TIM15_CR2	中國	Proof.	Problem 2	E	PAR	For	BUR	商品	13	路	Proof.	3	1,133	E	中心	E	3	Proof.	(1)	PAR	Effective	OS	Over County	OF	THE	MMS[2:0]			Open	COU		COND
0x04	Reset value																						0	0	0	0	0	0	0	0	0		0
0x08	TIM15_SMCR	3	超	PAR	3	PAR	E	新	$\exists$ dSWS		合計	TS [4:3]		PUB	Proof.	3	SSE	3	BUCK	3	Effective	中国	中国	PUB	STRON	MS5	TS[2:0]			PU	SMS[2:0]
0x08	Reset value								0			0	0				0									0	0	0	0		0	0	0
0x0C	TIM15_DIER	BUR	Recurrence	BUB	3	超市	3	HK$’000	BUR	HK$’000	3	SHIP	3,000	BUR	3	超市	BUR	3	TOF	30W00	Supposed	招	33	30100	Jul-20	BEE	正	COND	1,000	33	COND	GUI	当
0x0C	Reset value																		0	0				0	0	0	0	0			0	0	0
0x10	TIM15_SR	1,000	3	S	好	13	3	锅	2.	郎	超	13	:	出租	If	13	Proof.	BUR	SPROP	5,959	锅	Recurrence	30200	20100	3	BUND	千港元	Over County	13	股本	COND	Operation	当
0x10	Reset value																						0	0		0	0	0			0	0	0
0x14	TIM15_EGR	BUR	3	a	33	a	超	股本	路	BRAND	Rec-12	8	鲜	路	2	：	8	33	3	3	好	郎	好	Effective	串	BB	TC	COMPS	EX	3	CO2	COU	S
0x14	Reset value																									0	0	0			0	0	0
0x18	TIM15_CCMR1 Input Capture mode	Proof.	3	股本	股本	a	3	新	S	中国	：	股份	股份	股份	H	股份	3	IC2F[3:0]				IC2 PSC [1:0]		CC2S [1:0]		IC1F[3:0]				IC1 PSC [1:0]		CC1S [1:0]
	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
	TIM15_CCMR1 Output Compare mode	Recurrence	E	SCON	REE	S	：	出	[8]wzoo	电	3,000	CON	SHE	Representation	CON	超市	[8]W100	Oct-CO	OC2M [2:0]			$\exists$ d $\emptyset$ O	3.100	CC28 [1:0]		30100	OC1M [2:0]			Oct-12	3.20	CC1S [1:0]
	Reset value								0								0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x20	TIM15_CCER	PAR	8	股本	BUR	Problem	3	3	路口	E	CHF	B	部	好	股份	串	股份	Proof.	13	好	超	路	股份	6,699	For	dNZOO		Oct-2	COND	dNl O O	3NLOO	COU	COUTE
0x20	Reset value																									0		0	0	0	0	0	0

Table 302. TIM15 register map and reset values (continued)

Offset	Register name	31	300	23	23	27	26	26	24	23	22	21	20	1.	1.	17	16	16	14	13	12	11	10	9	8	7	6	5	4	3	21	0
0x24	TIM15_CNT	'sey jo adju		3	8	4	a	3	中心	BUG	电话	8	3	好	8	S	好	CNT[15:0]
0x24	Reset value	0																0	0	0	0	0	0	0	0	0	0	0	0	0	00	0
0x28	TIM15_PSC	g	8	4,549	您	4,699	3	股本	(3)	13	5,699	8	a	串	5	3gasPSC[15:0]
0x28	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	00	0
0x2C	TIM15_ARR		8		8		1	2	E	E	8		都	ARR[19:0]
0x2C	Reset value													0	0	0	0	1	1	1	1	1	1	1	1	1	1	1	1	1	11	1
0x30	TIM15_RCR		收购		好	ROUND		茶	S	t	8		d		a		中心	郎	鸿	路	E	出	超市	8	1,000		REP[7:0]
0x30	Reset value																									0	0	0	0	0	00	0
0x34	TIM15_CCR1		(a)	PAR	3,000	(3,000)	S	郎	中国	3	6,000		1	CCR1[19:0]
0x34	Reset value													0	0	0	0	0	0	0	0		0	0	0	0	0	0	0	0	00	0
0x38	TIM15_CCR2		3	郎	郎	43		8	16	3	8		中國										CCR2[19:0]
0x38	Reset value													0	0	0	0	0	0	0	0		0	0	0	0	0	0	0	0	00	0
0x38 - 0x40	Reserved	Res.
0x44	TIM15_BDTR		3		BIGE		was avg			8				BKF[3:0]				MOS	AQ4	BKPS	BKK	OS S	OS	LOCK [1:0]		DT[7:0]
0x44	Reset value				0		0							0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	00	0
0x48 - 0x50	Reserved	Res.
0x54	TIM15_DTR2		3		83	3		心		3	1		e			DIPPE	DAKA					郎		Rec		DTGF[7:0]
0x54	Reset value															0	0									0	0	0	0	0	00	0
0x58	Reserved
0x5C	TIM15_TISEL		3		3			│	a		出		A				Proof.	a				TI2SEL[3:0]						粥		TI1SEL[3:0]
0x5C	Reset value																					0	0	0	0					0	00	0
0x60	TIM15_AF1		邮		3		出	79	电	郎	a				N		的	(a)		dtdW0X8	dEdWOX8	d&dW:0*k	dIdWOX8	BMM	38dWOX8	3.2dW0.18	39dWOX8	3. SHOXI	3tdW0X8	$\exists \pounds$ dWoya	$\exists z$ dW0.4831dW0X8	BAKK
0x60	Reset value																			0	0	0	0	0	0	0	0	0	0	0	00	1
0x64	TIM15_AF2		好		好	43		36	第	13	郎		-5		OCR SEL[2:0]								粥	99.00	39	PUB	昭	部	BUR		送5,679
0x64	Reset value														0	0	0
0x68 -0x3D8ReservedRes.

30.8 TIM16/TIM17 registers

Refer to Section 1.2 for a list of abbreviations used in register descriptions.

30.8.1 TIMx control register 1 (TIMx_CR1)(x = 16 to 17)

Address offset: 0x00 Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	DITH EN	UIFRE MAP	Res.	CKD[1:0]		ARPE	Res.	Res.	Res.	OPM	URS	UDIS	CEN
			rw	rw		rw	rw	rw				rw	rw	rw	rw

Bits 15:13 Reserved, must be kept at reset value.

Bit 12 DITHEN: Dithering enable

0 : Dithering disabled

1: Dithering enabled

Note: The DITHEN bit can only be modified when CEN bit is reset.

Bit 11 UIFREMAP: UIF status bit remapping

0 : No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.

1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.

Bit 10 Reserved, must be kept at reset value.

Bits 9:8 CKD[1:0]: Clock division

This bit-field indicates the division ratio between the timer clock (tim_ker_ck) frequency and the dead-time and sampling clock

(t_{D T S})

used by the dead-time generators and the digital filters (tim_tix),

00:

t_{DTS} = t_{tim_\ker_ck}

01:

t_{DTS} = 2^{*} t_{tim_\ker_ck}

10:

t_{DTS} = 4^{*} t_{tim_\ker_ck}

11: Reserved

Bit 7 ARPE: Auto-reload preload enable

0: TIMx_ARR register is not buffered

1: TIMx_ARR register is buffered

Bits 6:4 Reserved, must be kept at reset value.

Bit 3 OPM: One pulse mode

0 : Counter is not stopped at update event

1: Counter stops counting at the next update event (clearing the bit CEN)

Bit 2 URS: Update request source

This bit is set and cleared by software to select the UEV event sources.

0:Any of the following events generate an update interrupt or DMA request if enabled.

These events can be:

Counter overflow/underflow

Setting the UG bit

Update generation through the slave mode controller

1: nly counter overflow/underflow generates an update interrupt or DMA request if enabled.

Bit 1 UDIS: Update disable

This bit is set and cleared by software to enable/disable UEV event generation.

0:UEV enabled. The Update (UEV) event is generated by one of the following events:

Counter overflow/underflow

Setting the UG bit

Update generation through the slave mode controller

Buffered registers are then loaded with their preload values.

1:UEV disabled. The Update event is not generated, shadow registers keep their value

(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.

Bit 0 CEN: Counter enable

0: Counter disabled

1: Counter enabled

Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.

30.8.2 TIMx control register 2 (TIMx_CR2)(x = 16 to 17)

Address offset: 0x04

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	OIS1N	OIS1	Res.	Res.	Res.	Res.	CCDS	ccus	Res.	CCPC
						rw	rw					rw	rw		rw

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 OIS1N: Output Idle state 1 (tim_oc1n output)

0: tim_oc1n=0 after a dead-time when MOE=0

tim_oc 1 n = 1

after a dead-time when

MOE = 0

Note: This bit can not be modified as long as LOCK level 1,2 or 3 has been programmed (LOCK bits in TIMx_BKR register).

Bit 8 OIS1: Output Idle state 1 (tim_oc1 output)

0: tim_oc1=0 after a dead-time when MOE=0

tim_oc 1 = 1

after a dead-time when

MOE = 0

Note: This bit can not be modified as long as LOCK level 1,2 or 3 has been programmed (LOCK bits in TIMx_BKR register).

Bits 7:4 Reserved, must be kept at reset value.

Bit 3 CCDS: Capture/compare DMA selection

0: CCx DMA request sent when CCx event occurs

1: CCx DMA requests sent when update event occurs

Bit 2 CCUS: Capture/compare control update selection

0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only.

1:When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when a rising edge occurs on tim_trgi (if available).

Note: This bit acts only on channels that have a complementary output.

Bit 1 Reserved, must be kept at reset value.

Bit 0 CCPC: Capture/compare preloaded control

0:CCxE, CCxNE and OCxM bits are not preloaded

1:CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set.

Note: This bit acts only on channels that have a complementary output.

30.8.3 TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) Address offset: 0x0C Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	CC1DE	UDE	BIE	Res.	COMIE	Res.	Res	Res.	CC1IE	UIE
						rw	rw	rw		rw				rw	rw

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 CC1DE: Capture/Compare 1 DMA request enable

0: CC1 DMA request disabled

1: CC1 DMA request enabled

Bit 8 UDE: Update DMA request enable

0: Update DMA request disabled

1: Update DMA request enabled

Bit 7 BIE: Break interrupt enable

0: Break interrupt disabled

1: Break interrupt enabled

Bit 6 Reserved, must be kept at reset value.

Bit 5 COMIE: COM interrupt enable

0: COM interrupt disabled

1: COM interrupt enabled

Bits 4:2 Reserved, must be kept at reset value.

Bit 1 CC1IE: Capture/Compare 1 interrupt enable

0: CC1 interrupt disabled

1: CC1 interrupt enabled

Bit 0 UIE: Update interrupt enable

0 : Update interrupt disabled

1: Update interrupt enabled

30.8.4 TIMx status register (TIMx_SR)(x = 16 to 17)

Address offset: 0x10

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	CC10F	Res.	BIF	Res.	COMIF	Res:	Res.	Res.	CC1IF	UIF
						rc_w0		rc_w0		rc_w0				rc_w0	rc_w0

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 CC10F: Capture/Compare 1 overcapture flag

This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ’ 0 ’.

0 : No overcapture has been detected

1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set

Bit 8 Reserved, must be kept at reset value.

Bit 7 BIF: Break interrupt flag

This flag is set by hardware as soon as the tim_brk input goes active. It can be cleared by software if the break input is not active.

0 : No break event occurred

1: An active level has been detected on the break input

Bit 6 Reserved, must be kept at reset value.

Bit 5 COMIF: COM interrupt flag

This flag is set by hardware on a COM event (once the capture/compare control bits

- CCxE

, CCxNE, OCxM- have been updated). It is cleared by software.

0: No COM event occurred

1: COM interrupt pending

Bits 4:2 Reserved, must be kept at reset value.

Bit 1 CC1IF: Capture/Compare 1 interrupt flag

This flag is set by hardware. It is cleared by software (input capture or output compare

mode) or by reading the TIMx_CCR1 register (input capture mode only).

0 : No compare match / No input capture occurred

1: A compare match or an input capture occurred

If channel CC1 is configured as output: this flag is set when the content of the counter

TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of

TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the

counter overflow (in up-counting and up/down-counting modes) or underflow (in down-

counting mode). There are 3 possible options for flag setting in center-aligned mode, refer

to the CMS bits in the TIMx_CR1 register for the full description.

If channel CC1 is configured as input: this bit is set when counter value has been

captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge

sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER).

Bit 0 UIF: Update interrupt flag

This bit is set by hardware on an update event. It is cleared by software.

0 : No update occurred.

1: Update interrupt pending. This bit is set by hardware when the registers are updated: - At overflow regarding the repetition counter value (update if repetition counter

= 0

) and if the UDIS

= 0

in the TIMx_CR1 register.

When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if

URS=0 and UDIS=0 in the TIMx_CR1 register.

30.8.5 TIMx event generation register (TIMx_EGR)(x = 16 to 17)

Address offset: 0x14

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res	Res.	Res.	Res.	Res	Res.	Res.	BG	Res.	COMG	Res.	Res.	Res.	CC1G	UG
								w		w				w	w

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 BG: Break generation

This bit is set by software in order to generate an event, it is automatically cleared by hardware.

0 : No action.

1:A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled.

Bit 6 Reserved, must be kept at reset value.

Bit 5 COMG: Capture/Compare control update generation

This bit can be set by software, it is automatically cleared by hardware.

0 : No action

1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits Note: This bit acts only on channels that have a complementary output.

Bits 4:2 Reserved, must be kept at reset value.

Bit 1 CC1G: Capture/Compare 1 generation

This bit is set by software in order to generate an event, it is automatically cleared by hardware.

0 : No action.

1: A capture/compare event is generated on channel 1:

If channel CC1 is configured as output:

CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.

If channel CC1 is configured as input:

Bit 0 UG: Update generation

This bit can be set by software, it is automatically cleared by hardware.

0 : No action.

1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). 30.8.6 TIMx capture/compare mode register 1 (TIMx_CCMR1)

(x = 16 to 17)

Address offset: 0x18

Reset value: 0x00000000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 IC1F[3:0]: Input capture 1 filter

This bit-field defines the frequency used to sample tim_ti1 input and the length of the digital filter applied to tim_ti1. The digital filter is made of an event counter in which

N

consecutive events are needed to validate a transition on the output:

0000: No filter,sampling is done at

f_{DTS}

0001:

f_{SAMPLING} = f_{tim_ker_ck}, N = 2

0010:

f_{SAMPLING} = f_{tim_ker_ck}, N = 4

0011:

f_{SAMPLING} = f_{tim_ker_ck}, N = 8

0100:

f_{SAMPLING} = f_{DTS} / 2, N =

0101:

f_{SAMPLING} = f_{DTS} / 2, N = 8

0110:

f_{SAMPLING} = f_{DTS} / 4, N = 6

0111:

f_{SAMPLING} = f_{DTS} / 4, N = 8

1000:

f_{SAMPLING} = f_{DTS} / 8, N = 6

1001 : f_{SAMPLING} = f_{DTS} / 8, N = 8

1010:

f_{SAMPLING} = f_{DTS} / 16, N = 5

1011:

f_{SAMPLING} = f_{DTS} / 16, N = 6

1100:

f_{SAMPLING} = f_{DTS} / 16, N = 8

1101:

f_{SAMPLING} = f_{DTS} / 32, N = 5

1110:

f_{SAMPLING} = f_{DTS} / 32, N = 6

1111:

f_{SAMPLING} = f_{DTS} / 32, N = 8

Bits 3:2 IC1PSC[1:0]: Input capture 1 prescaler

This bit-field defines the ratio of the prescaler acting on CC1 input (tim_ic1).

The prescaler is reset as soon as CC1E='0' (TIMx_CCER register).

00 : no prescaler, capture is done each time an edge is detected on the capture input.

01: capture is done once every 2 events

10: capture is done once every 4 events

11: capture is done once every 8 events

Bits 1:0 CC1S[1:0]: Capture/Compare 1 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC1 channel is configured as output

01: CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1

Others: Reserved

Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).

30.8.7 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 16 to 17)

Address offset: 0x18

Reset value: 0x00000000

The same register can be used for output compare mode (this section) or for input capture mode (previous section). The direction of a channel is defined by configuring the

Output compare mode:

Bits 31:17 Reserved, must be kept at reset value.

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 OC1CE: Output Compare 1 clear enable

0: tim_oc1ref is not affected by the tim_ocref_clr input.

1: tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr input.

Bits 16, 6:4 OC1M[3:0]: Output Compare 1 mode

These bits define the behavior of the output reference signal tim_oc1ref from which tim_oc1 and

tim_oc 1 n

are derived.

tim_oc 1 ref is active high whereas tim_oc 1

and

tim_oc 1 n

active level depends on CC1P and CC1NP bits.

0000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. This mode can be used when the timer serves as a software timebase. When the frozen mode is enabled during timer operation, the output keeps the state (active or inactive) it had before entering the frozen state.

0001: Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).

0010: Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).

0011: Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1.

0100: Force inactive level - tim_oc1ref is forced low.

0101: Force active level - tim_oc1ref is forced high.

0110: PWM mode 1 - Channel 1 is active as long as TIMx_CNT

0111: PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT

Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in output). In PWM mode, the OCREF level changes when the result of the comparison changes, when the output compare mode switches from "frozen" mode to "PWM" mode and when the output compare mode switches from "force active/inactive" mode to "PWM" mode.

Bit 3 OC1PE: Output Compare 1 preload enable

0:Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.

1:Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.

Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in output).

Bit 2 OC1FE: Output Compare 1 fast enable

0:CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles.

1:An active edge on the trigger input acts like a compare match on CC1 output. Then, tim_ocx is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode.

Bits 1:0 CC1S[1:0]: Capture/Compare 1 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC1 channel is configured as output

01: CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1

Others: Reserved

Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).

30.8.8 TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17)

Address offset: 0x20

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res:	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	CC1NP	CC1NE	CC1P	CC1E
												rw	rw	rw	rw

Bits 15:4 Reserved, must be kept at reset value.

Bit

3

CC1NP: Capture/Compare 1 complementary output polarity

CC1 channel configured as output:

0: tim_oc1n active high

1: tim_oc1n active low

CC1 channel configured as input:

This bit is used in conjunction with CC1P to define the polarity of tim_ti1fp1. Refer to the description of CC1P.

Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S="00" (the channel is configured in output). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a commutation event is generated.

Bit 2 CC1NE: Capture/Compare 1 complementary output enable

0:Off - tim_oc1n is not active. tim_oc1n level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.

1:On - tim_oc1n signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.

Bit 1 CC1P: Capture/Compare 1 output polarity

0: OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)

1: OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)

When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations.

CC 1 NP = 0, CC 1 P = 0

CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TlxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode).

CC 1 NP = 1, CC 1 P = 1

CC 1 NP = 1, CC 1 P = 0

: this configuration is reserved,it must not be used.

Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).

On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated.

Bit 0 CC1E: Capture/Compare 1 output enable

0: Capture mode disabled / OC1 is not active (see below)

1: Capture mode enabled / OC1 signal is output on the corresponding output pin

When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to Table 303 for details.

Table 303. Output control bits for complementary tim_oc1 and tim_oc1n channels with break feature (TIM16/TIM17)

Control bits					Output states(1)
MOE bit	OSSI bit	OSSR bit	CC1E bit	CC1NE bit	tim_oc1 output state	tim_oc1n output state
1	X	X	0	0	Output Disabled (not driven by the timer: Hi-Z) tim_oc1=0 tim_oc1n=0
		0	0	1	Output Disabled (not driven by the timer: Hi-Z) tim_oc1=0	tim_oc1ref + Polarity tim_oc1n=tim_oc1ref XOR CC1NP
		0	1	0	tim oc1ref + Polarity tim oc1=tim oc1ref XOR CC1P	Output Disabled (not driven by the timer: Hi-Z) tim_oc1n=0
		X	1	1	tim oc1ref + Polarity + dead-time	Complementary to tim_oc1ref (not tim_oc1ref) + Polarity + dead-time
		1	0	1	Off-State (output enabled with inactive state) tim oc1=CC1P	tim oc1ref + Polarity tim oc1n=tim oc1ref XOR CC1NP
		1	1	0	tim oc1ref + Polarity tim oc1=tim oc1ref XOR CC1P	Off-State (output enabled with inactive state) tim oc1n=CC1NP
0	0	X	X	X	Output disabled (not driven by the timer: Hi-Z)
	1		0	0	Output disabled (not driven by the timer: Hi-Z)
			0	1	Off-State (output enabled with inactive state) Asynchronously: tim oc1=CC1P, tim oc1n=CC1NP Then if the clock is present: tim oc1=OIS1 and tim oc1n=OIS1N after a dead-time, assuming that OIS1 and OIS1N do not correspond to tim_oc1 and tim_oc1n both in active state
			1	0
			1	1

When both outputs of a channel are not used (control taken over by GPIO controller), the OIS1, OIS1N, CC1P and CC1NP bits must be kept cleared.

Note: The state of the external I/O pins connected to the complementary tim_oc1 and tim_oc1n channels depends on the tim_oc1 and tim_oc1n channel state and GPIO control and alternate function selection registers. 30.8.9 TIMx counter (TIMx_CNT)(x = 16 to 17)

Address offset: 0x24 Reset value: 0x00000000

Bit 31 UIFCPY: UIF Copy

This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved.

Bits 30:16 Reserved, must be kept at reset value.

Bits 15:0 CNT[15:0]: Counter value

Non-dithering mode (DITHEN = 0)

The register holds the counter value.

Dithering mode (DITHEN = 1)

The register only holds the non-dithered part in CNT[15:0]. The fractional part is not

available.

30.8.10 TIMx prescaler (TIMx_PSC)(x = 16 to 17)

Address offset: 0x28 Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0 PSC[15:0]: Prescaler value

The counter clock frequency (tim_cnt_ck) is equal to

f_{tim_psc_ck} / (P S C [15 : 0] + 1)

PSC contains the value to be loaded in the active prescaler register at each update event

(including when the counter is cleared through UG bit of TIMx_EGR register or through

trigger controller when configured in "reset mode"). 30.8.11 TIMx auto-reload register (TIMx_ARR)(x = 16 to 17)

Address offset: 0x2C

Reset value: 0x0000 FFFF

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:0 ARR[19:0]: Auto-reload value

ARR is the value to be loaded in the actual auto-reload register.

Refer to the Section 30.4.3: Time-base unit on page 1361 for more details about ARR

update and behavior.

The counter is blocked while the auto-reload value is null.

Non-dithering mode (DITHEN = 0)

The register holds the auto-reload value in ARR[15:0]. The ARR[19:16] bits are reset.

Dithering mode (DITHEN = 1)

The register holds the integer part in ARR[19:4]. The ARR[3:0] bitfield contains the dithered part.

30.8.12 TIMx repetition counter register (TIMx_RCR)(x = 16 to 17)

Address offset: 0x30

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	REP[7:0]
								rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:8 Reserved, must be kept at reset value.

Bits 7:0 REP[7:0]: Repetition counter reload value

When the repetition down-counter reaches zero, an update event is generated and it restarts counting from REP value. As the repetition counter is reloaded with REP value only at the repetition update event UEV, any write to the TIMx_RCR register is not taken in account until the next repetition update event.

It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode:

the number of PWM periods in edge-aligned mode

the number of half PWM period in center-aligned mode 30.8.13 TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17)

Address offset: 0x34

Reset value: 0x00000000

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:0 CCR1[19:0]: Capture/Compare 1 value If channel CC1 is configured as output:

The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on tim_oc1 output.

Non-dithering mode (DITHEN = 0)

The register holds the compare value in CCR1[15:0]. The CCR1[19:16] bits are reset. Dithering mode (DITHEN = 1)

The register holds the integer part in CCR1[19:4]. The CCR1[3:0] bitfield contains the dithered part.

If channel CC1 is configured as input:

CCR1 is the counter value transferred by the last input capture 1 event (tim_ic1).

Non-dithering mode (DITHEN = 0)

The register holds the capture value in CCR1[15:0]. The CCR1[19:16] bits are reset.

Dithering mode (DITHEN = 1)

The register holds the capture in CCR1[19:4]. The CCR1[3:0] bits are reset.

30.8.14 TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17)

Address offset: 0x44

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	BKBID	Res.	BK DSRM	Res.	Res.	Res.	Res.	Res.	Res.	BKF[3:0]
			rw		rw							rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK[1:0]		DTG[7:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

te: As the BKBID, BKDSRM, BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits may be write-locked depending on the LOCK configuration, it may be necessary to configure all of them during the first write access to the TIMx_BDTR register.

Bits 31:29 Reserved, must be kept at reset value.

Bit 28 BKBID: Break Bidirectional

0: Break input tim_brk in input mode

1: Break input tim_brk in bidirectional mode

In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices.

Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

Bit 27 Reserved, must be kept at reset value.

Bit 26 BKDSRM: Break Disarm

0 : Break input tim_brk is armed

1: Break input tim_brk is disarmed

This bit is cleared by hardware when no break source is active.

The BKDSRM bit must be set by software to release the bidirectional output control (open-

drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared.

Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

Bits 25:20 Reserved, must be kept at reset value.

Bits 19:16 BKF[3:0]: Break filter

This bit-field defines the frequency used to sample tim_brk input and the length of the digital filter applied to tim_brk. The digital filter is made of an event counter in which

N

events are needed to validate a transition on the output:

0000: No filter, tim_brk acts asynchronously

0001 : f_{SAMPLING = f_{tim_\ker_ck}, N = 2}

0010:

f_{SAMPLING} = f_{tim_ker_ck}, N = 4

0011:

f_{SAMPLING} = f_{tim_ker_ck}, N = 8

0100 : f_{SAMPLING} = f_{DTS} / 2, N = 6

0101:

f_{SAMPLING} = f_{DTS} / 2, N = 8

0110:

f_{SAMPLING} = f_{DTS} / 4, N = 6

0111:

f_{SAMPLING} = f_{DTS} / 4, N = 8

1000:

f_{SAMPLING} = f_{DTS} / 8, N = 6

1001:

f_{SAMPLING} = f_{DTS} / 8, N = 8

1010:

f_{SAMPLING} = f_{DTS} / 16, N = 5

1011:

f_{SAMPLING} = f_{DTS} / 16, N = 6

1100:

f_{SAMPLING} = f_{DTS} / 16, N = 8

1101:

f_{SAMPLING} = f_{DTS} / 32, N = 5

1110:

f_{SAMPLING} = f_{DTS} / 32, N = 6

1111:

f_{SAMPLING} = f_{DTS} / 32, N = 8

This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Bit 15 MOE: Main output enable

0:tim_oc1 and tim_oc1n outputs are disabled or forced to idle state depending on the OSSI bit.

1:tim_oc1 and tim_oc1n outputs are enabled if their respective enable bits are set (CC1E, CC1NE in TIMx_CCER register)

See tim_oc1/tim_oc1n enable description for more details (Section 30.8.8: TIMx

capture/compare enable register (TIMx_CCER)

(x = 16 to 17)

on page 1442).

Bit 14 AOE: Automatic output enable

0:MOE can be set only by software

1:MOE can be set by software or automatically at the next update event (if the tim_brk input is not active)

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Bit 13 BKP: Break polarity

0: Break input tim_brk is active low

1: Break input tim_brk is active high

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

Bit 12 BKE: Break enable

0: Break inputs (tim_brk and tim_sys_brk event) disabled

1; Break inputs (tim_brk and tim_sys_brk event) enabled

Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

Bit 11 OSSR: Off-state selection for Run mode

This bit is used when

MOE = 1

on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer.

See tim_oc1/tim_oc1n enable description for more details (Section 30.8.8: TIMx capture/compare enable register (TIMx_CCER)

(x = 16 to 17)

on page 1442).

0:When inactive, tim_oc1/tim_oc1n outputs are disabled (the timer releases the output control which is taken over by the GPIO, which forces a Hi-Z state)

1:When inactive, tim_oc1/tim_oc1n outputs are enabled with their inactive level as soon as

CC 1 E = 1

CC 1 NE = 1

(the output is still controlled by the timer).

Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).

Bit 10 OSSI: Off-state selection for Idle mode

This bit is used when MOE=0 on channels configured as outputs.

See tim_oc1/tim_oc1n enable description for more details (Section 30.8.8: TIMx

capture/compare enable register (TIMx_CCER)

(x = 16 to 17)

on page 1442).

0:When inactive, tim_oc1/tim_oc1n outputs are disabled (tim_oc1/tim_oc1n enable output signal=0)

1:When inactive, tim_oc1/tim_oc1n outputs are forced first with their idle level as soon as CC1E=1 or CC1NE=1. tim_oc1/tim_oc1n enable output signal=1)

Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).

Bits 9:8 LOCK[1:0]: Lock configuration

These bits offer a write protection against software errors.

00: LOCK OFF - No bit is write protected

01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.

10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.

11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in

TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.

Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.

Bits 7:0 DTG[7:0]: Dead-time generator setup

This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration.

DTG [7 : 5] = 0 xx => DT = DTG [7 : 0] x t_{dtg}

with

t_{dtg} = t_{DTS}

DTG [7 : 5] = 10 x => DT = (64 + DTG [5 : 0]) \times t_{dtg}

with

T_{dtg} = 2 \times t_{DTS}

DTG [7 : 5] = 110 => DT = (32 + DTG [4 : 0]) {xt}_{dtg}

with

T_{dtg} = 8 {xt}_{DTS}

DTG [7 : 5] = 111 => DT = (32 + DTG [4 : 0]) \times t_{dtg}

with

T_{dtg} = 16 \times t_{DTS}

Example if

T_{D T S} = 125 ns (8 MHz)

,dead-time possible values are:

0 to 15875 ns by 125 ns steps,

16 μ s

31750 ns

250 ns

steps,

32 μ s

63 μ s

1 μ s

steps,

64 μ s

126 μ s

2 μ s

steps

Note: This bit-field can not be modified as long as LOCK level 1,2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).

30.8.15 TIMx timer deadtime register 2 (TIMx_DTR2)(x = 16 to 17)

Address offset: 0x054

Reset value: 0x00000000

Bits 31:18 Reserved, must be kept at reset value.

Bit 17 DTPE: Deadtime preload enable

0: Deadtime value is not preloaded

1: Deadtime value preload is enabled

Note: This bit can not be modified as long as LOCK level 1,2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).

Bit 16 DTAE: Deadtime asymmetric enable

0: Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register

1: Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits.

Note: This bit can not be modified as long as LOCK level 1,2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).

Bits 15:8 Reserved, must be kept at reset value.

Bits 7:0 DTGF[7:0]: Dead-time falling edge generator setup

This bit-field defines the duration of the dead-time inserted between the complementary

outputs, on the falling edge.

DTGF [7 : 5] = 0 x x => DTF = DTGF [7 : 0] x t_{dtq}

with

t_{dtq} = t_{DTS}

DTGF [7 : 5] = 10 x => DTF = (64 + DTGF [5 : 0]) x t_{dtg}

with

T_{dtg} = 2 x t_{DTS}

DTGF [7 : 5] = 110 \Rightarrow DTF = (32 + DTGF [4 : 0]) {xt}_{dtg}

with

T_{dtg} = 8 {xt}_{DTS}

DTGF [7 : 5] = 111 => DTF = (32 + DTGF [4 : 0]) \times t_{dtg}

with

T_{dtg} = 16 \times t_{DTS}

Example if

T_{D T S} = 125 ns (8 MHz)

,dead-time possible values are:

0 to 15875 ns by

125 ns

steps,

16 us to 31750 ns by 250 ns steps,

32 us to 63 us by 1 us steps,

64 us to 126 us by 2 us steps

Note: This bit-field can not be modified as long as LOCK level 1,2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).

30.8.16 TIMx input selection register (TIMx_TISEL)(x = 16 to 17)

Address offset: 0x5C

Reset value: 0x00000000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	TI1SEL[3:0]
												rw	rw	rw	rw

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 TI1SEL[3:0]: selects tim_ti1_in[15:0] input

0000: TIMx_CH1 input (tim_ti1_in0)

0001: tim_ti1_in1

\dots

1111: tim_ti1_in15

Refer to Section 30.4.2: TIM15/TIM16/TIM17 pins and internal signals for interconnects list.

30.8.17 TIMx alternate function register 1 (TIMx_AF1)(x = 16 to 17)

Address offset: 0x060

Reset value: 0x00000001

Res.	Res.	BK CMP4P	BK CMP3P	BK CMP2P	BK CMP1P	BKINP	BK CMP8E	BK CMP7E	BK CMP6E	BK CMP5E	BK CMP4E	BK CMP3E	BK CMP2E	BK CMP1E	BKINE
		rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Refer to Section 30.4.2: TIM15/TIM16/TIM17 pins and internal signals for product specific implementation.

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 BKCMP4P: tim_brk_cmp4 input polarity

This bit selects the tim_brk_cmp4 input sensitivity. It must be programmed together with the BKP polarity bit.

0: tim_brk_cmp4 input is active high

1: tim_brk_cmp4 input is active low

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Bit 12 BKCMP3P: tim_brk_cmp3 input polarity

This bit selects the tim_brk_cmp3 input sensitivity. It must be programmed together with the BKP polarity bit.

0: tim_brk_cmp3 input is active high

1: tim_brk_cmp3 input is active low

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Bit 11 BKCMP2P: tim_brk_cmp2 input polarity

This bit selects the tim_brk_cmp2 input sensitivity. It must be programmed together with the BKP polarity bit.

0: tim_brk_cmp2 input is active high

1: tim_brk_cmp2 input is active low

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Bit 10 BKCMP1P: tim_brk_cmp1 input polarity

This bit selects the tim_brk_cmp1 input sensitivity. It must be programmed together with the BKP polarity bit.

0: tim_brk_cmp1 input is active high

1: tim_brk_cmp1 input is active low

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Bit 9 BKINP: TIMx_BKIN input polarity

This bit selects the TIMx_BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit.

0: TIMx_BKIN input is active high

1: TIMx_BKIN input is active low

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Bit 8 BKCMP8E: tim_brk_cmp8 enable

This bit enables the tim_brk_cmp8 for the timer's tim_brk input. mdf_brkx output is 'ORed' with the other tim_brk sources.

0: tim_brk_cmp8 input disabled

1: tim_brk_cmp8 input enabled

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Bit 7 BKCMP7E: tim_brk_cmp7 enable

This bit enables the tim_brk_cmp7 for the timer's tim_brk input. tim_brk_cmp7 output is 'ORed' with the other tim_brk sources.

0: tim_brk_cmp7 input disabled

1: tim_brk_cmp7 input enabled

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Bit 6 BKCMP6E: tim_brk_cmp6 enable

This bit enables the tim_brk_cmp6 for the timer's tim_brk input. tim_brk_cmp6 output is

'ORed' with the other tim_brk sources.

0: tim_brk_cmp6 input disabled

1: tim_brk_cmp6 input enabled

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 5 BKCMP5E: tim_brk_cmp5 enable

This bit enables the tim_brk_cmp5 for the timer's tim_brk input. tim_brk_cmp5 output is 'ORed' with the other tim_brk sources.

0: tim_brk_cmp5 input disabled

1: tim_brk_cmp5 input enabled

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Bit 4 BKCMP4E: tim_brk_cmp4 enable

This bit enables the tim_brk_cmp4 for the timer's tim_brk input. tim_brk_cmp4 output is 'ORed' with the other tim_brk sources.

0: tim_brk_cmp4 input disabled

1: tim_brk_cmp4 input enabled

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Bit 3 BKCMP3E: tim_brk_cmp3 enable

This bit enables the tim_brk_cmp3 for the timer's tim_brk input. tim_brk_cmp3 output is 'ORed' with the other tim_brk sources.

0: tim_brk_cmp3 input disabled

1: tim_brk_cmp3 input enabled

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Bit 2 BKCMP2E: tim_brk_cmp2 enable

This bit enables the tim_brk_cmp2 for the timer's tim_brk input. tim_brk_cmp2 output is 'ORed' with the other tim_brk sources.

0: tim_brk_cmp2 input disabled

1: tim_brk_cmp2 input enabled

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Bit 1 BKCMP1E: tim_brk_cmp1 enable

This bit enables the tim_brk_cmp1 for the timer's tim_brk input. tim_brk_cmp1 output is 'ORed' with the other tim_brk sources.

0: tim_brk_cmp1 input disabled

1: tim_brk_cmp1 input enabled

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Bit 0 BKINE: TIMx_BKIN input enable

This bit enables the TIMx_BKIN alternate function input for the timer's tim_brk input.

TIMx_BKIN input is 'ORed' with the other tim_brk sources.

0: TIMx_BKIN input disabled

1: TIMx_BKIN input enabled

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

30.8.18 TIMx alternate function register 2 (TIMx_AF2)(x = 16 to 17)

Address offset: 0x064

Reset value: 0x00000000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:16 OCRSEL[2:0]: tim_ocref_clr source selection

These bits select the tim_ocref_clr input source.

000: tim_ocref_clr0

001: tim_ocref_clr1

010: tim_ocref_clr2

011: tim_ocref_clr3

100: tim_ocref_clr4

101: tim_ocref_clr5

110: tim_ocref_clr6

111: tim_ocref_clr7

Refer to Section 30.4.2: TIM15/TIM16/TIM17 pins and internal signals for product specific

implementation.

Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK

bits in TIMx_BDTR register).

Bits 15:0 Reserved, must be kept at reset value.

30.8.19 TIMx option register 1 (TIMx_OR1)(x = 16 to 17)

Address offset: 0x68

Reset value: 0x00000000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 HSE32EN: HSE Divided by 32 enable

This bit enables the HSE divider by 32 for the tim_ti1_in3. See Table 290: Interconnect to the tim_ti1 input multiplexer for details.

0: HSE divided by 32 disabled

1: HSE divided by 32 enabled

30.8.20 TIMx DMA control register (TIMx_DCR)(x = 16 to 17)

Address offset: 0x3DC

Reset value: 0x00000000

Res.	Res.	Res.	DBL[4:0]					Res.	Res.	Res.	- -99 DBA[4:0]
			rw	rw	rw	rw	rw				rw	rw	rw	rw	rw

Bits 31:13 Reserved, must be kept at reset value.

Bits 12:8 DBL[4:0]: DMA burst length

This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below).

00000: 1 transfer,

00001: 2 transfers,

00010: 3 transfers,

10001: 18 transfers.

Bits 7:5 Reserved, must be kept at reset value.

Bits 4:0 DBA[4:0]: DMA base address

This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register.

Example:

0000: TIMx_CR1,

00001: TIMx_CR2,

00010: TIMx_SMCR,

Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.

30.8.21 TIM16/TIM17 DMA address for full transfer $(TIMx_DMAR) (x = 16 to 17)$

Address offset: 0x3E0

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DMAB[31:16]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

30.8.22 TIM16/TIM17 register map

TIM16/TIM17 registers are mapped as 16-bit addressable registers as described in the table below:

Table 304. TIM16/TIM17 register map and reset values

Offset	Register name	3,31	30	23	2Q3	27	2Q	23	24	23	22	21	2023	1.	1.	17	1.	1.5	4	1	12	1	1.	9	8	7	6	5	4	3	2	1	O
0x00	TIMx_CR1	(a)	HK$’000	S	8	1	d	3	Proof.	CON	For	3	出	3	B	y	好	RECT	3	8	d	VW3V3In		CKD [1:0]		ARPH		Recurrence	Proof.	Operation	USE	Univ.	CHE
0x00	Reset value																					0		0	0	0				0	0	0	0
0x04	TIMx_CR2	8	45	3	好	2,399	：	股份	13	Proof.	5,459	路	郎	x	30	5,459	BULL	S	出租	33	PU	33	Proof.	Overal County	OF		BUCK	BAR	Proof.	SQ19	Oct-20		Opto
0x04	Reset value																							0	0					0	0		0
0x08	Reserved	Res.
0x0C	TIMx_DIER	中國	3	好	3	Recall	串	3	3,399	PAR	d	3	a	化	COMP	LU	招聘	3	3	COMP	Proof.	3	3	30100	少	BEE		31W00		：		GUI	当
0x0C	Reset value																							0	0	0		0				0	0
0x10	TIMx_SR	路	路	：	：	a	郎	电话	3	PAR	(a)	：	a	此	習	:	3	Recurrence	3	:	商	3	3	20100		BUN		Output	R	3		Q4 5	当
0x10	Reset value																							0		0		0				0	0
0x14	TIMx_EGR	於	: 3	3	股本	郎	13	BRON	給	STA	解	：	好	BALLY	路	: 3	S	3	8	好	a	B	3	(3)		BB		5WOO		超市		COU	S
0x14	Reset value																									0		0				0	0
0x18	TIMx_CCMR1 Input Capture mode	股份	3	SHIP	3	中	BUR	中國	(3,397)	中國	股份	好	郎	化	MAS	好	：	3	Recurrence	：	PROM	3	Effect	E	SHUR	IC1F[3:0]				IC1 PSC [1:0]		CC1 S [1:0]
	Reset value																									0	0	0	0	0	0	0	0
	TIMx_CCMR1 Output Compare mode	3	B	超市	出	部	E	E	3,859	好	部	股本	3	路	金	8	[8]W100		超	出	好	BUR	股本	出		30100	OC1M [2:0]			3d100	3. 1.100	CC1 S [1:0]
	Reset value																0									0	0	0	0	0	0	0	0
0x1C	Reserved	Res
0x20	TIMx_CCER	Effect	BUR	E	MA	电子	Rec	:	3	股份	(a)	3	3	R	心	出	Proof.	CH	出色	3	8	3	好	E	BUB	2021年	超市	d	P	Overally,	COMPS	CON	CON
0x20	Reset value																													0	0	0	0
0x24	TIMx_CNT	'sey jo adjulin		粉	股份	8	3	3	給	y	路	：	a	收	(3,000)	: 3	S		CNT[15:0]
0x24	Reset value	0																0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x28	TIMx_PSC	5,672	好	股份	PAR	E	PROS	路	REPT	B	新	3	郎	出	邮	a	8	PSC[15:0]
0x28	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Table 304. TIM16/TIM17 register map and reset values (continued)

Offset	Register name	31	30	23	23	27	26	26	24	23	22	21	2023	1.	1.	17	伯	IS	4	13	12	1	10	9	8	7	6	5	4	3	21	O
0x2C	TIMx_ARR		粉色	时	好	3	B	3,000	REPT	13.0	3	E	中國ARR[19:0]
0x2C	Reset value													0	0	0	0	1	1	1	1	1	1	1	1	1	1	1	1	1	11	1
0x30	TIMx_RCR		超市	3	好	33	BUR	13	3	Problem	千港元	好	金色	a	路	好	3	Recurrence	3	3	3	3	郎	路口	串			REP[7:0]
0x30	Reset value																									0	0	0	0	0	00	0
0x34	TIMx_CCR1		REE	a			：	8	SHIP	Proof.	邮	：	13	CCR1[19:0]
0x34	Reset value													0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	00	0
0x38 - 0x40	ReservedRes.
0x44	TIMx_BDTR	：	Proof.		BIRD		WYSCHA		8	品	PROS	a	都	BKF[3:0]				MOS	AQ4	BRD	BKK	OS S	OS CO	LOC K [1:0]		DT[7:0]
0x44	Reset value				0		0							0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	00	0
0x48 - 0x50	ReservedRes.
0x54	TIMx_DTR2		The	3,049		郎	中	Proof.	部	电	超	3	d		：	DEE	DAKA		心	都	PHY	3	8	HK$’000	中	DTGF[7:0]
0x54	Reset value															0	0									0	0	0	0	0	00	0
0x58	Reserved
0x5C	TIMx_TISEL		4	的	电子	(a)	a	心	(a)	PR	d	3	RECT		Proof.	(a)		REPHY	4	B		e	d	中心	d	中	Proof.	Proof.	1	TI1SEL[3:0]
0x5C	Reset value																													0	00	0
0x60	TIMx_AF1	COM	到	(a)	BUG	都	R	中	3	8	Recall	3	8	Recurrence	8	超	电子	1		dtdW0*	dEdWOX8	d&dW:0*k	dldW0X8	BMM	38dWOX8	$\exists$ 2dW0>18	39dW0X8	3 SdWOX8	স্র্র্র্র	300	300 20083 LdWOX8	3NIX8
0x60	Reset value																			0	0	0	0	0	0	0	0	0	0	0	00	1
0x64	TIMx_AF2		电子	至今	1,131	电话	郎	串串	SCO	好	3	5	出		OCR SEL[2:0]				PARTHE						心		Proof.	PRO	2	不	3PAR	PE
0x64	Reset value														0	0	0
0x68	TIMx_OR1		REPHY	PU	PROM	d	3	3	3,699	1,000	郎	都	品	2	PH	9	(1)	RAM	3	好的	8	8	3	中國	部	PHY	3	Represent	Proof.	Proof.	REPER	N3783SH
0x68	Reset value																															0
0x6C - 0x3D8	Reserved	Res.
0x3DC	TIMx_DCR		E	.4		0	馮	3	y	E	好	a	粥		心						DBL[4:0]					a	13	超市	DBA[4:0]
0x3DC	Reset value																				0	0	0	0	0				0	0	00	0
0x3E0	TIMx_DMAR	DMAB[31:0]
0x3E0	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	00	0

31 Basic timers (TIM6/TIM7)

31.1 TIM6/TIM7 introduction

The basic timers TIM6/TIM7 consist in a 16-bit auto-reload counter driven by a programmable prescaler.

They may be used as generic timers for time-base generation.

The basic timer can also be used for triggering the digital-to-analog converter. This is done with the trigger output of the timer.

The timers are completely independent, and do not share any resources.

31.2 TIM6/TIM7 main features

Basic timer (TIM6/TIM7) features include:

16-bit auto-reload upcounter

16-bit programmable prescaler used to divide (also "on the fly") the counter clock frequency by any factor between 1 and 65535

Synchronization circuit to trigger the DAC

Interrupt/DMA generation on the update event: counter overflow

31.3.3 TIM6/TIM7 clocks

The timer bus interface is clocked by the tim_pclk APB clock.

The counter clock tim_ker_ck is connected to the tim_pclk input.

The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except for UG that remains cleared automatically). As soon as the CEN bit is written to 1 , the prescaler is clocked by the internal clock tim_ker_ck.

Figure 481 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler.

Figure 481. Control circuit in normal mode, internal clock divided by 1

31.3.4 Time-base unit

The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler.

The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.

The time-base unit includes:

Counter Register (TIMx_CNT)

Prescaler Register (TIMx_PSC)

Auto-Reload Register (TIMx_ARR)

The auto-reload register is preloaded. The preload register is accessed each time an attempt is made to write or read the auto-reload register. The contents of the preload register are transferred into the shadow register permanently or at each update event UEV, depending on the auto-reload preload enable bit (ARPE) in the TIMx_CR1 register. The update event is sent when the counter reaches the overflow value and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration.

The counter is clocked by the prescaler output tim_cnt_ck, which is enabled only when the counter enable bit (CEN) in the TIMx_CR1 register is set.

Note that the actual counter enable signal tim_cnt_en is set 1 clock cycle after CEN bit set.

Prescaler description

The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as the TIMx_PSC control register is buffered. The new prescaler ratio is taken into account at the next update event.

Figure 482 and Figure 483 give some examples of the counter behavior when the prescaler ratio is changed on the fly.

Figure 482. Counter timing diagram with prescaler division change from 1 to 2

Figure 483. Counter timing diagram with prescaler division change from 1 to 4

31.3.5 Counting mode

The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event.

An update event can be generate at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).

The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This avoids updating the shadow registers while writing new values into the preload registers. In this way, no update event occurs until the UDIS bit has been written to 0 , however, the counter and the prescaler counter both restart from 0 (but the prescale rate does not change). In addition, if the URS (update request selection) bit in the TIMx_CR1 register is set, setting the UG bit generates an update event UEV, but the UIF flag is not set (so no interrupt or DMA request is sent).

When an update event occurs, all the registers are updated and the update flag (UIF bit in the TIMx_SR register) is set (depending on the URS bit):

The buffer of the prescaler is reloaded with the preload value (contents of the TIMx_PSC register)

The auto-reload shadow register is updated with the preload value (TIMx_ARR)

The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR

= 0 \times 36

Figure 489. Counter timing diagram, update event when ARPE=1 (TIMx_ARR

Dithering mode

The time base effective resolution can be increased by enabling the dithering mode, using the DITHEN bit in the TIMx_CR1 register. This affects the way the TIMx_ARR is behaving, and is useful for adjusting the average counter period when the timer is used as a trigger (typically for a DAC).

The operating principle is to have the actual ARR value slightly changed (adding or not one timer clock period) over 16 consecutive counting periods, with predefined patterns. This allows a 16-fold resolution increase, considering the average counting period.

The Figure 490 below presents the dithering principle applied to 4 consecutive counting periods.

Figure 490. Dithering principle

When the dithering mode is enabled, the register coding is changed as following (see Figure 491 for example):

the 4 LSBs are coding for the enhanced resolution part (fractional part)

The MSBs are left-shifted to the bits 19:4 and are coding for the base value

The ARR values are updated automatically if the DITHEN bit is set / reset (for instance, if ARR= 0x05 with DITHEN=0, it is updated to ARR = 0x50 with DITHEN = 1). The following sequence must be followed when resetting the DITHEN bit:

CEN and ARPE bits must be reset

The ARR[3:0] bits must be reset

The DITHEN bit must be reset

The CEN bit can be set ( eventually with ARPE = 1).

Figure 491. Data format and register coding in dithering mode

The minimum frequency is given by the following formula:

Resolution = \frac{F_{Tim}}{F_{pwm}} \Rightarrow F_{pwmMin} = \frac{F_{Tim}}{{Max}_{Resolution}}

Dithering mode disabled: F_{pwmMin} = \frac{F_{Tim}}{65536}

Dithering mode enabled: F_{pwmMin} = \frac{F_{Tim}}{65535 + \frac{15}{16}}

, to: The maximum TIMx_ARR value is limited to 0xFFFEF in dithering mode (corresponds to 65534 for the integer part and 15 for the dithered part).

As shown on the Figure 492 below, the dithering mode is used to increase the PWM resolution whatever the PWM frequency.

Figure 492.

F_{Cnt}

resolution vs frequency

The period changes are spread over 16 consecutive periods, as described in the Figure 493 below.

Figure 493. PWM dithering pattern

The auto-reload and compare values increments are spread following specific patterns described in the Table 306 below. The dithering sequence is done to have increments distributed as evenly as possible and minimize the overall ripple.

Table 306. TIMx_ARR register change dithering pattern

-	PWM period
LSB value	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16
0000	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
0001	+1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
0010	+1	-	-	-	-	-	-	-	+1	-	-	-	-	-	-	-
0011	+1	-	-	-	+1	-	-	-	+1	-	-	-	-	-	-	-
0100	+1	-	-	-	+1	-	-	-	+1	-	-	-	+1	-	-	-
0101	+1	-	+1	-	+1	-	-	$-$	+1	-	-	-	+1	-	-	-
0110	+1	-	+1	-	+1	-	-	-	+1	-	+1	-	+1	-	-	-
0111	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-	-	-
1000	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-
1001	+1	+1	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-
1010	+1	+1	+1	-	+1	-	+1	-	+1	+1	+1	-	+1	-	+1	-
1011	+1	+1	+1	-	+1	+1	+1	-	+1	+1	+1	-	+1	-	+1	-
1100	+1	+1	+1	-	+1	+1	+1	-	+1	+1	+1	-	+1	+1	+1	-
1101	+1	+1	+1	+1	+1	+1	+1	-	+1	+1	+1	-	+1	+1	+1	-
1110	+1	+1	+1	+1	+1	+1	+1	-	+1	+1	+1	+1	+1	+1	+1	-
1111	+1	+1	+1	+1	+1	+1	+1	+1	+1	+1	+1	+1	+1	+1	+1	-

31.3.6 UIF bit remapping

The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the Update Interrupt Flag UIF into the timer counter register's bit 31 (TIMxCNT[31]). This is used to atomically read both the counter value and a potential roll-over condition signaled by the UIFCPY flag. In particular cases, it can ease the calculations by avoiding race conditions caused for instance by a processing shared between a background task (counter reading) and an interrupt (Update Interrupt).

There is no latency between the assertions of the UIF and UIFCPY flags.

31.3.7 ADC triggers

The timer can generate an ADC triggering event with various internal signals, such as reset, enable or compare events.

Note: The clock of the slave peripherals (such as timer, ADC) receiving the tim_trgo signal must be enabled prior to receiving events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.

31.3.8 TIM6/TIM7 DMA requests

The TIM6/TIM7 can generate a single DMA request, as shown in Table 307.

Table 307. DMA request

DMA request signal	DMA acronym	DMA request	Enable control bit
tim_upd_dma	TIM_UP	Update	UDE

31.3.9 Debug mode

When the microcontroller enters debug mode (Cortex®-M4 with FPU core halted),the TIMx counter can either continue to work normally or be stopped.

The behavior in debug mode can be programmed with a dedicated configuration bit per timer in the Debug support (DBG) module.

For more details, refer to section Debug support (DBG).

31.3.10 TIM6/TIM7 low-power modes

Table 308. Effect of low-power modes on TIM6/TIM7

Mode	Description
Sleep	No effect, peripheral is active. The interrupts can cause the device to exit from Sleep mode.
Stop	The timer operation is stopped and the register content is kept. No interrupt can be generated.
Standby	The timer is powered-down and must be reinitialized after exiting the Standby mode

31.3.11 TIM6/TIM7 interrupts

The TIM6/TIM7 can generate a single interrupt, as shown in Table 309.

Table 309. Interrupt request

Interrupt acronym	Interrupt event	Event flag	Enable control bit	Interrupt clear method	Exit from Sleep mode	Exit from Stop and Standby mode
TIM6 TIM7	Update	UIF	UIE	write 0 in UIF	Yes	No

31.4 TIM6/TIM7 registers

Refer to Section 1.2 on page 73 for a list of abbreviations used in register descriptions.

The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

31.4.1 TIMx control register 1 (TIMx_CR1)(x = 6 to 7)

Address offset: 0x00

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	DITH EN	UIFRE MAP	Res.	Res.	Res.	ARPE	Res.	Res	Res.	OPM	URS	UDIS	CEN
			rw	rw				rw				rw	rw	rw	rw

Bits 15:13 Reserved, must be kept at reset value.

Bit 12 DITHEN: Dithering enable

0: Dithering disabled

1: Dithering enabled

Note: The DITHEN bit can only be modified when CEN bit is reset.

Bit 11 UIFREMAP: UIF status bit remapping

0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.

1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.

Bits 10:8 Reserved, must be kept at reset value.

Bit 7 ARPE: Auto-reload preload enable

0: TIMx_ARR register is not buffered.

1: TIMx_ARR register is buffered.

Bits 6:4 Reserved, must be kept at reset value.

Bit 3 OPM: One-pulse mode

0 : Counter is not stopped at update event

1: Counter stops counting at the next update event (clearing the CEN bit).

Bit 2 URS: Update request source

This bit is set and cleared by software to select the UEV event sources.

0: Any of the following events generates an update interrupt or DMA request if enabled.

These events can be:

Counter overflow/underflow

Setting the UG bit

Update generation through the slave mode controller

1: Only counter overflow/underflow generates an update interrupt or DMA request if

enabled.

Bit 1 UDIS: Update disable

This bit is set and cleared by software to enable/disable UEV event generation.

0: UEV enabled. The Update (UEV) event is generated by one of the following events:

Counter overflow/underflow

Setting the UG bit

Update generation through the slave mode controller

Buffered registers are then loaded with their preload values.

1: UEV disabled. The Update event is not generated, shadow registers keep their value

(ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if

a hardware reset is received from the slave mode controller.

Bit 0 CEN: Counter enable

0: Counter disabled

1: Counter enabled

CEN is cleared automatically in one-pulse mode, when an update event occurs.

31.4.2 TIMx control register 2 (TIMx_CR2)(x = 6 to 7)

Address offset: 0x04

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	MMS[2:0]			Res.	Res.	Res.	Res.
									rw	rw	rw

Bits 15:7 Reserved, must be kept at reset value.

Bits 6:4 MMS[2:0]: Master mode selection

These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:

000: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (tim_trgo).

001: Enable - the Counter enable signal, tim_cnt_en, is used as a trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated when the CEN control bit is written.

010: Update - The update event is selected as a trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer.

Note: The clock of the slave timer or he peripheral receiving the tim_trgo must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

Bits 3:0 Reserved, must be kept at reset value.

31.4.3 TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7)

Address offset: 0x0C

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	UDE	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIE
							rw								rw

Bits 15:9 Reserved, must be kept at reset value.

Bit 8 UDE: Update DMA request enable

0: Update DMA request disabled.

1: Update DMA request enabled.

Bits 7:1 Reserved, must be kept at reset value.

Bit 0 UIE: Update interrupt enable

0 : Update interrupt disabled.

1: Update interrupt enabled.

31.4.4 TIMx status register (TIMx_SR)(x = 6 to 7)

Address offset: 0x10

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res:	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIF
															rc_w0

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 UIF: Update interrupt flag

This bit is set by hardware on an update event. It is cleared by software.

0 : No update occurred.

1: Update interrupt pending. This bit is set by hardware when the registers are updated:

On counter overflow if UDIS $= 0$ in the TIMx_CR1 register.

When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if

URS

= 0

and UDIS

= 0

in the TIMx_CR1 register.

31.4.5 TIMx event generation register (TIMx_EGR)(x = 6 to 7)

Address offset: 0x14

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UG
															w

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 UG: Update generation

This bit can be set by software, it is automatically cleared by hardware.

0 : No action.

1: Re-initializes the timer counter and generates an update of the registers. Note that the

prescaler counter is cleared too (but the prescaler ratio is not affected).

31.4.6 TIMx counter (TIMx_CNT)(x = 6 to 7)

Address offset: 0x24 Reset value: 0x00000000

Bit 31 UIFCPY: UIF copy

This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in

TIMx_CR1 is reset, bit 31 is reserved and read as 0 .

Bits 30:16 Reserved, must be kept at reset value.

Bits 15:0 CNT[15:0]: Counter value

Non-dithering mode (DITHEN = 0)

The register holds the counter value.

Dithering mode (DITHEN = 1)

The register only holds the non-dithered part in CNT[15:0]. The fractional part is not

available.

31.4.7 TIMx prescaler (TIMx_PSC)(x = 6 to 7)

Address offset: 0x28

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0 PSC[15:0]: Prescaler value

The counter clock frequency

f_{tim_cnt_ck}

is equal to

f_{tim_psc_ck} / (P S C [15 : 0] + 1)

PSC contains the value to be loaded into the active prescaler register at each update event.

(including when the counter is cleared through UG bit of TIMx_EGR register.

31.4.8 TIMx auto-reload register (TIMx_ARR)(x = 6 to 7)

Address offset: 0x2C

Reset value: 0x0000 FFFF

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res	Res.	Res.	Res.	Res.	Res.	ARR[19:16]
												rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:0 ARR[19:0]: Auto-reload value

ARR is the value to be loaded into the actual auto-reload register.

Refer to Section 31.3.4: Time-base unit on page 1462 for more details about ARR update and behavior.

The counter is blocked while the auto-reload value is null.

Non-dithering mode (DITHEN = 0)

The register holds the auto-reload value in ARR[15:0]. The ARR[19:16] bits are reserved.

Dithering mode (DITHEN = 1)

The register holds the integer part in ARR[19:4]. The ARR[3:0] bitfield contains the dithered part.

31.4.9 TIMx register map

TIMx registers are mapped as 16-bit addressable registers as described in the table below:

Table 310. TIMx register map and reset values

Offset	Register name	31	30	23	23	27	2625	24	23	22	21	20	9	1.	17	16	1.5	14	1.3	12	11	10	9	8	7	6	5	4	3	2	1	O
0x00	TIMx_CR1	e a	3,000	1,000	3	Proof.	Proof.Proof.	3	3	3	3	留	3	Recurrence	好	Proof.	Proof.	中华	PRO	NEHILIC	VW3V3In		：	S	ARPH	时间	Proof.	1,471	Operation	USE	Space	CHF
0x00	Reset value																			0	0				0				0	0	0	0
0x04	TIMx_CR2	：	S	Proof.	股本	股本	13串	E	13	Problem 2	股份	SHUD		平平	Proof.	HK$’000	Recall	Problem 1.	千港元	13	Problem 2			：	中國	MMS [2:0]			金	好	S	Proof.
0x04	Reset value																									0	0	0
0x08	Reserved
0x0C	TIMx_DIER	Problem Controllection	1.0	Proof.	Proof.	：	Proof.路	3	BUS	Effective	3	2	Let	好	1,010	Represent	1,000	中华	Ester	For	明日	超		195	For	1,010	中心	：	1,000	For	3	当
0x0C	Reset value																							0								0
0x10	TIMx_SR	1.00	3	For	招聘	招	BULL出	3	股份	3,399	STRAND	股份	新	3	招工	134	BULL	SHIP	好的	好	3	BUR	1,649	新	SECT	好好	BUS	S	3	Recall	股份	当
0x10	Reset value																															0
0x14	TIMx_EGR	好好	1.00	时	1,133	3	Proof.好	Proof.	PORT	Proof.	BUR	SHIP	2.00	股本	：	股份	Problem	5,399	STRATE	8	Proof.	1,000	BUB	Problem Controllection	股本	PAR	股本	S	3,133	SCA	8	S
0x14	Reset value																															0
0x18- 0x20	Reserved
0x24	TIMx_CNT	say 10 AdOsIn	3	3	招聘	出	PARTE13	3	中國	3	部	股份	SHUDE	SE	招工	3	CNT[15:0]
0x24	Reset value	0															0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x28	TIMx_PSC	超市	中國	Proof.	3	路	3招聘	3	Proof.	3	千港元	千港元	：	路	的	粉丝	PSC[15:0]
0x28	Reset value																0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x2C	TIMx_ARR		：	1,000	股本	33	38	好	8	33	部	第	ARR[19:0]
0x2C	Reset value												0	0	0	0	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

Refer to Section 2.2 on page 81 for the register boundary addresses.

32 Low-power timer (LPTIM)

32.1 Introduction

The LPTIM is a 16-bit timer that benefits from the ultimate developments in power consumption reduction. Thanks to its diversity of clock sources, the LPTIM is able to keep running in all power modes except for Standby mode. Given its capability to run even with no internal clock source, the LPTIM can be used as a "Pulse Counter" which can be useful in some applications. Also, the LPTIM capability to wake up the system from low-power modes, makes it suitable to realize "Timeout functions" with extremely low power consumption.

The LPTIM introduces a flexible clock scheme that provides the needed functionalities and performance, while minimizing the power consumption.

32.2 LPTIM main features

16 bit upcounter

3-bit prescaler with 8 possible dividing factors $(1, 2, 4, 8, 16, 32, 64, 128)$

Selectable clock

Internal clock sources: configurable internal clock source (see RCC section)

External clock source over LPTIM input (working with no embedded oscillator running, used by Pulse Counter application)

16 bit ARR autoreload register

16 bit compare register

Continuous/One-shot mode

Selectable software/hardware input trigger

Programmable Digital Glitch filter

Configurable output: Pulse, PWM

Configurable I/O polarity

Encoder mode

Table 312. LPTIM1 external trigger connection (continued)

TRIGSEL	External trigger
lptim_ext_trig3	RTC_TAMP1_OUT
lptim_ext_trig4	RTC_TAMP2_OUT
lptim_ext_trig5	RTC_TAMP3_OUT
lptim_ext_trig6	COMP1_OUT
lptim_ext_trig7	COMP2_OUT
lptim_ext_trig8	COMP3_OUT
lptim_ext_trig9	COMP4_OUT
lptim_ext_trig10	COMP5_OUT
lptim_ext_trig11	COMP6_OUT
lptim_ext_trig12	COMP7_OUT

Table 313. LPTIM1 input 1 connection

lptim_in1_mux	LPTIM1 input 1 connected to
lptim_in1_0	GPIO pin as LPTIM1_IN1 alternate function
lptim_in1_1	COMP1
lptim_in1_2	COMP3
lptim_in1_3	COMP5
lptim_in1_4	COMP7

Table 314. LPTIM1 input 2 connection

lptim_in2_mux	LPTIM1 input 2 connected to
lptim_in2_0	GPIO pin as LPTIM1_IN2 alternate function
lptim_in2_1	COMP2
lptim_in2_2	COMP4
lptim_in2_3	COMP6
lptim_in2_4	COMP6

32.4.3 LPTIM reset and clocks

The LPTIM can be clocked using several clock sources. It can be clocked using an internal clock signal which can be any configurable internal clock source selectable through the RCC (see RCC section for more details). Also, the LPTIM can be clocked using an external clock signal injected on its external Input1. When clocked with an external clock source, the LPTIM may run in one of these two possible configurations:

The first configuration is when the LPTIM is clocked by an external signal but in the same time an internal clock signal is provided to the LPTIM from configurable internal clock source (see RCC section).

The second configuration is when the LPTIM is solely clocked by an external clock source through its external Input1. This configuration is the one used to realize Timeout function or Pulse counter function when all the embedded oscillators are turned off after entering a low-power mode.

Programming the CKSEL and COUNTMODE bits allows controlling whether the LPTIM will use an external clock source or an internal one.

When configured to use an external clock source, the CKPOL bits are used to select the external clock signal active edge. If both edges are configured to be active ones, an internal clock signal should also be provided (first configuration). In this case, the internal clock signal frequency should be at least four times higher than the external clock signal frequency.

32.4.4 Glitch filter

The LPTIM inputs, either external (mapped to GPIOs) or internal (mapped on the chip-level to other embedded peripherals), are protected with digital filters that prevent any glitches and noise perturbations to propagate inside the LPTIM. This is in order to prevent spurious counts or triggers.

Before activating the digital filters, an internal clock source should first be provided to the LPTIM. This is necessary to guarantee the proper operation of the filters.

The digital filters are divided into two groups:

The first group of digital filters protects the LPTIM external inputs. The digital filters sensitivity is controlled by the CKFLT bits

The second group of digital filters protects the LPTIM internal trigger inputs. The digital filters sensitivity is controlled by the TRGFLT bits.

Note: The digital filters sensitivity is controlled by groups. It is not possible to configure each digital filter sensitivity separately inside the same group.

The filter sensitivity acts on the number of consecutive equal samples that should be detected on one of the LPTIM inputs to consider a signal level change as a valid transition. Figure 495 shows an example of glitch filter behavior in case of a 2 consecutive samples programmed.

Note:

Figure 495. Glitch filter timing diagram

In case no internal clock signal is provided, the digital filter must be deactivated by setting the CKFLT and TRGFLT bits to ’ 0 ’. In that case, an external analog filter may be used to protect the LPTIM external inputs against glitches.

32.4.5 Prescaler

The LPTIM 16-bit counter is preceded by a configurable power-of-2 prescaler. The prescaler division ratio is controlled by the PRESC[2:0] 3-bit field. The table below lists all the possible division ratios:

Table 315. Prescaler division ratios

programming	dividing factor
000	/1
001	12
010	14
011	18
100	/16
101	/32
110	/64
111	/128

32.4.6 Trigger multiplexer

The LPTIM counter may be started either by software or after the detection of an active edge on one of the 13 trigger inputs.

TRIGEN[1:0] is used to determine the LPTIM trigger source:

When TRIGEN[1:0] equals '00', The LPTIM counter is started as soon as one of the CNTSTRT or the SNGSTRT bits is set by software. The three remaining possible values for the TRIGEN[1:0] are used to configure the active edge used by the trigger inputs. The LPTIM counter starts as soon as an active edge is detected.

When TRIGEN[1:0] is different than '00', TRIGSEL[2:0] is used to select which of the 13 trigger inputs is used to start the counter.

The external triggers are considered asynchronous signals for the LPTIM. So after a trigger detection, a two-counter-clock period latency is needed before the timer starts running due to the synchronization.

If a new trigger event occurs when the timer is already started it will be ignored (unless timeout function is enabled).

Note:

The timer must be enabled before setting the SNGSTRT/CNTSTRT bits. Any write on these bits when the timer is disabled will be discarded by hardware.

Note: When starting the counter by software (TRIGEN[1:0] = 00), there is a delay of 3 kernel clock cycles between the LPTIM_CR register update (set one of SNGSTRT or CNTSTRT bits) and the effective start of the counter.

32.4.7 Operating mode

The LPTIM features two operating modes:

The Continuous mode: the timer is free running, the timer is started from a trigger event and never stops until the timer is disabled

One-shot mode: the timer is started from a trigger event and stops when reaching the ARR value.

One-shot mode

To enable the one-shot counting, the SNGSTRT bit must be set.

A new trigger event will re-start the timer. Any trigger event occurring after the counter starts and before the counter reaches ARR will be discarded.

In case an external trigger is selected, each external trigger event arriving after the SNGSTRT bit is set, and after the counter register has stopped (contains zero value), will start the counter for a new one-shot counting cycle as shown in Figure 496.

Figure 496. LPTIM output waveform, single counting mode configuration

Set-once mode activated:

It should be noted that when the WAVE bit-field in the LPTIM_CFGR register is set, the Set-once mode is activated. In this case, the counter is only started once following the first trigger, and any subsequent trigger event is discarded as shown in Figure 497.

Figure 497. LPTIM output waveform, Single counting mode configuration and Set-once mode activated (WAVE bit is set)

In case of software start (TRIGEN[1:0] = ‘00’), the SNGSTRT setting will start the counter for one-shot counting.

Continous mode

To enable the continuous counting, the CNTSTRT bit must be set.

In case an external trigger is selected, an external trigger event arriving after CNTSTRT is set will start the counter for continuous counting. Any subsequent external trigger event will be discarded as shown in Figure 498.

In case of software start (TRIGEN[1:0] = '00'), setting CNTSTRT will start the counter for continuous counting.

Figure 498. LPTIM output waveform, Continuous counting mode configuration

SNGSTRT and CNTSTRT bits can only be set when the timer is enabled (The ENABLE bit is set to ‘1’). It is possible to change “on the fly” from One-shot mode to Continuous mode.

If the Continuous mode was previously selected, setting SNGSTRT will switch the LPTIM to the One-shot mode. The counter (if active) will stop as soon as it reaches ARR.

If the One-shot mode was previously selected, setting CNTSTRT will switch the LPTIM to the Continuous mode. The counter (if active) will restart as soon as it reaches ARR.

32.4.8 Timeout function

The detection of an active edge on one selected trigger input can be used to reset the LPTIM counter. This feature is controlled through the TIMOUT bit.

The first trigger event will start the timer, any successive trigger event will reset the counter and the timer will restart.

A low-power timeout function can be realized. The timeout value corresponds to the compare value; if no trigger occurs within the expected time frame, the MCU is waked-up by the compare match event.

32.4.9 Waveform generation

Two 16-bit registers, the LPTIM_ARR (autoreload register) and LPTIM_CMP (compare register), are used to generate several different waveforms on LPTIM output

The timer can generate the following waveforms:

The PWM mode: the LPTIM output is set as soon as the counter value in LPTIM_CNT exceeds the compare value in LPTIM_CMP. The LPTIM output is reset as soon as a match occurs between the LPTIM_ARR and the LPTIM_CNT registers.

The One-pulse mode: the output waveform is similar to the one of the PWM mode for the first pulse, then the output is permanently reset

The Set-once mode: the output waveform is similar to the One-pulse mode except that the output is kept to the last signal level (depends on the output configured polarity).

The above described modes require that the LPTIM_ARR register value be strictly greater than the LPTIM_CMP register value.

The LPTIM output waveform can be configured through the WAVE bit as follow:

Resetting the WAVE bit to ' 0 ' forces the LPTIM to generate either a PWM waveform or a One pulse waveform depending on which bit is set: CNTSTRT or SNGSTRT.

Setting the WAVE bit to '1' forces the LPTIM to generate a Set-once mode waveform.

The WAVPOL bit controls the LPTIM output polarity. The change takes effect immediately, so the output default value will change immediately after the polarity is re-configured, even before the timer is enabled.

Signals with frequencies up to the LPTIM clock frequency divided by 2 can be generated. Figure 499 below shows the three possible waveforms that can be generated on the LPTIM output. Also, it shows the effect of the polarity change using the WAVPOL bit.

Figure 499. Waveform generation

32.4.10 Register update

The LPTIM_ARR register and LPTIM_CMP register are updated immediately after the APB bus write operation, or at the end of the current period if the timer is already started.

The PRELOAD bit controls how the LPTIM_ARR and the LPTIM_CMP registers are updated:

When the PRELOAD bit is reset to ' 0 ', the LPTIM_ARR and the LPTIM_CMP registers are immediately updated after any write access.

When the PRELOAD bit is set to '1', the LPTIM_ARR and the LPTIM_CMP registers are updated at the end of the current period, if the timer has been already started.

The LPTIM APB interface and the LPTIM kernel logic use different clocks, so there is some latency between the APB write and the moment when these values are available to the counter comparator. Within this latency period, any additional write into these registers must be avoided.

The ARROK flag and the CMPOK flag in the LPTIM_ISR register indicate when the write operation is completed to respectively the LPTIM_ARR register and the LPTIM_CMP register.

After a write to the LPTIM_ARR register or the LPTIM_CMP register, a new write operation to the same register can only be performed when the previous write operation is completed. Any successive write before respectively the ARROK flag or the CMPOK flag be set, will lead to unpredictable results.

32.4.11 Counter mode

The LPTIM counter can be used to count external events on the LPTIM Input1 or it can be used to count internal clock cycles. The CKSEL and COUNTMODE bits control which source will be used for updating the counter.

In case the LPTIM is configured to count external events on Input1, the counter can be updated following a rising edge, falling edge or both edges depending on the value written to the CKPOL[1:0] bits.

The count modes below can be selected, depending on CKSEL and COUNTMODE values:

CKSEL = 0: the LPTIM is clocked by an internal clock source

COUNTMODE $= 0$

The LPTIM is configured to be clocked by an internal clock source and the LPTIM counter is configured to be updated following each internal clock pulse.

COUNTMODE = 1

The LPTIM external Input1 is sampled with the internal clock provided to the LPTIM.

Consequently, in order not to miss any event, the frequency of the changes on the external Input1 signal should never exceed the frequency of the internal clock provided to the LPTIM. Also, the internal clock provided to the LPTIM must not be prescaled (PRESC[2:0] = 000).

CKSEL = 1: the LPTIM is clocked by an external clock source

COUNTMODE value is don't care.

In this configuration, the LPTIM has no need for an internal clock source (except if the glitch filters are enabled). The signal injected on the LPTIM external Input1 is used as system clock for the LPTIM. This configuration is suitable for operation modes where no embedded oscillator is enabled.

For this configuration, the LPTIM counter can be updated either on rising edges or falling edges of the input 1 clock signal but not on both rising and falling edges.

Since the signal injected on the LPTIM external Input1 is also used to clock the LPTIM kernel logic, there is some initial latency (after the LPTIM is enabled) before the counter is incremented. More precisely, the first five active edges on the LPTIM external Input1 (after LPTIM is enable) are lost.

32.4.12 Timer enable

The ENABLE bit located in the LPTIM_CR register is used to enable/disable the LPTIM kernel logic. After setting the ENABLE bit, a delay of two counter clock is needed before the LPTIM is actually enabled.

The LPTIM_CFGR and LPTIM_IER registers must be modified only when the LPTIM is disabled.

32.4.13 Timer counter reset

In order to reset the content of LPTIM_CNT register to zero, two reset mechanisms are implemented:

The synchronous reset mechanism: the synchronous reset is controlled by the COUNTRST bit in the LPTIM_CR register. After setting the COUNTRST bit-field to '1', the reset signal is propagated in the LPTIM kernel clock domain. So it is important to note that a few clock pulses of the LPTIM kernel logic will elapse before the reset is taken into account. This will make the LPTIM counter count few extra pluses between the time when the reset is trigger and it become effective. Since the COUNTRST bit is located in the APB clock domain and the LPTIM counter is located in the LPTIM kernel clock domain, a delay of 3 clock cycles of the kernel clock is needed to synchronize the reset signal issued by the APB clock domain when writing '1' to the COUNTRST bit.

The asynchronous reset mechanism: the asynchronous reset is controlled by the RSTARE bit located in the LPTIM_CR register. When this bit is set to '1', any read access to the LPTIM_CNT register will reset its content to zero. Asynchronous reset should be triggered within a timeframe in which no LPTIM core clock is provided. For example when LPTIM Input1 is used as external clock source, the asynchronous reset should be applied only when there is enough insurance that no toggle will occur on the LPTIM Input1.

It should be noted that to read reliably the content of the LPTIM_CNT register two successive read accesses must be performed and compared. A read access can be considered reliable when the value of the two read accesses is equal. Unfortunately when asynchronous reset is enabled there is no possibility to read twice the LPTIM_CNT register.

Warning: There is no mechanism inside the LPTIM that prevents the two reset mechanisms from being used simultaneously. So developer should make sure that these two mechanisms are used exclusively.

32.4.14 Encoder mode

This mode allows handling signals from quadrature encoders used to detect angular position of rotary elements. Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value programmed into the LPTIM_ARR register ( 0 up to ARR or ARR down to 0 depending on the direction). Therefore LPTIM_ARR must be configured before starting the counter. From the two external input signals, Input1 and Input2, a clock signal is generated to clock the LPTIM counter. The phase between those two signals determines the counting direction.

The Encoder mode is only available when the LPTIM is clocked by an internal clock source. The signals frequency on both Input1 and Input2 inputs must not exceed the LPTIM internal clock frequency divided by 4 . This is mandatory in order to guarantee a proper operation of the LPTIM.

Direction change is signalized by the two Down and Up flags in the LPTIM_ISR register. Also, an interrupt can be generated for both direction change events if enabled through the DOWNIE bit.

To activate the Encoder mode the ENC bit has to be set to '1'. The LPTIM must first be configured in Continuous mode.

When Encoder mode is active, the LPTIM counter is modified automatically following the speed and the direction of the incremental encoder. Therefore, its content always represents the encoder's position. The count direction, signaled by the Up and Down flags, correspond to the rotation direction of the encoder rotor.

According to the edge sensitivity configured using the CKPOL[1:0] bits, different counting scenarios are possible. The following table summarizes the possible combinations, assuming that Input1 and Input2 do not switch at the same time.

Table 316. Encoder counting scenarios

Active edge	Level on opposite signal (Input1 for Input2, Input2 for Input1)	Input1 signal		Input2 signal
Active edge		Rising	Falling	Rising	Falling
Rising Edge	High	Down	No count	Up	No count
Rising Edge	Low	Up	No count	Down	No count
Falling Edge	High	No count	Up	No count	Down
Falling Edge	Low	No count	Down	No count	Up
Both Edges	High	Down	Up	Up	Down
Both Edges	Low	Up	Down	Down	Up

The following figure shows a counting sequence for Encoder mode where both-edge sensitivity is configured.

Caution: In this mode the LPTIM must be clocked by an internal clock source, so the CKSEL bit must be maintained to its reset value which is equal to ’ 0 ’. Also, the prescaler division ratio must be equal to its reset value which is 1 (PRESC[2:0] bits must be '000').

32.4.15 Debug mode

When the microcontroller enters debug mode (core halted), the LPTIM counter either continues to work normally or stops, depending on the DBG_LPTIM_STOP configuration bit in the DBG module.

32.5 LPTIM low-power modes

Table 317. Effect of low-power modes on the LPTIM

Mode	Description
Sleep	No effect. LPTIM interrupts cause the device to exit Sleep mode.
Low-power run	No effect.
Low-power sleep	No effect. LPTIM interrupts cause the device to exit the Low-power sleep mode.
Stop 0 / Stop 1	No effect when LPTIM is clocked by LSE or LSI. LPTIM interrupts cause the device to exit Stop 0 and Stop 1.
Standby	The LPTIM peripheral is powered down and must be reinitialized after exiting Standby or Shutdown mode
Shutdown

32.6 LPTIM interrupts

The following events generate an interrupt/wake-up event, if they are enabled through the

LPTIM_IER register:

Compare match

Auto-reload match (whatever the direction if encoder mode)

External trigger event

Autoreload register write completed

Compare register write completed

Direction change (encoder mode), programmable (up / down / both).

Note: If any bit in the LPTIM_IER register (Interrupt Enable Register) is set after that its corresponding flag in the LPTIM_ISR register (Status Register) is set, the interrupt is not asserted.

Table 318. Interrupt events

Interrupt event	Description
Compare match	Interrupt flag is raised when the content of the Counter register (LPTIM_CNT) matches the content of the compare register (LPTIM_CMP).
Auto-reload match	Interrupt flag is raised when the content of the Counter register (LPTIM_CNT) matches the content of the Auto-reload register (LPTIM_ARR).
External trigger event	Interrupt flag is raised when an external trigger event is detected
Auto-reload register update OK	Interrupt flag is raised when the write operation to the LPTIM_ARR register is complete.
Compare register update OK	Interrupt flag is raised when the write operation to the LPTIM_CMP register is complete.
Direction change	Used in Encoder mode. Two interrupt flags are embedded to signal direction change: – UP flag signals up-counting direction change – DOWN flag signals down-counting direction change.

32.7 LPTIM registers

Refer to Section 1.2: List of abbreviations for registers for a list of abbreviations used in register descriptions.

The peripheral registers can only be accessed by words (32-bit).

32.7.1 LPTIM interrupt and status register (LPTIM_ISR)

Address offset: 0x000

Reset value: 0x00000000

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 DOWN: Counter direction change up to down

In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register.

Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to Section 32.3: LPTIM implementation.

Bit 5 UP: Counter direction change down to up

In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register.

Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to Section 32.3: LPTIM implementation.

Bit 4 ARROK: Autoreload register update OK

ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.

Bit 3 CMPOK: Compare register update OK

CMPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_CMP register has been successfully completed. CMPOK flag can be cleared by writing 1 to the CMPOKCF bit in the LPTIM_ICR register.

Bit 2 EXTTRIG: External trigger edge event

EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.

Bit 1 ARRM: Autoreload match

ARRM is set by hardware to inform application that LPTIM_CNT register's value reached the

LPTIM_ARR register's value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the

LPTIM_ICR register.

Bit 0 CMPM: Compare match

The CMPM bit is set by hardware to inform application that LPTIM_CNT register value reached the

LPTIM_CMP register's value. CMPM flag can be cleared by writing 1 to the CMPMCF bit in the

LPTIM_ICR register.

32.7.2 LPTIM interrupt clear register (LPTIM_ICR)

Address offset: 0x004

Reset value: 0x00000000

Res.	Res.	Res.	Res.	Res.	Resr	Res.	Res.	Res.	DOWN CF	UPCF	ARRO KCF	CMPO KCF	EXTTR IGCF	ARRM CF	CMPM CF
									w	w	w	w	w	w	w

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 DOWNCF: Direction change to down clear flag

Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register.

Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to

Section 32.3: LPTIM implementation.

Bit 5 UPCF: Direction change to UP clear flag

Writing 1 to this bit clear the UP flag in the LPTIM_ISR register.

Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to

Section 32.3: LPTIM implementation.

Bit 4 ARROKCF: Autoreload register update OK clear flag

Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register

Bit 3 CMPOKCF: Compare register update OK clear flag

Writing 1 to this bit clears the CMPOK flag in the LPTIM_ISR register

Bit 2 EXTTRIGCF: External trigger valid edge clear flag

Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register

Bit 1 ARRMCF: Autoreload match clear flag

Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register

Bit 0 CMPMCF: Compare match clear flag

Writing 1 to this bit clears the CMPM flag in the LPTIM_ISR register

32.7.3 LPTIM interrupt enable register (LPTIM_IER)

Address offset: 0x008

Reset value: 0x00000000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	DOWNI E	UPIE	ARRO KIE	CMPO KIE	EXT TRIGIE	ARRM IE	CMPM IE
									rw	rw	rw	rw	rw	rw	rw

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 DOWNIE: Direction change to down Interrupt Enable

0: DOWN interrupt disabled

1: DOWN interrupt enabled

Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to

Section 32.3: LPTIM implementation.

Bit 5 UPIE: Direction change to UP Interrupt Enable

0: UP interrupt disabled

1: UP interrupt enabled

Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to

Section 32.3: LPTIM implementation.

Bit 4 ARROKIE: Autoreload register update OK Interrupt Enable

0: ARROK interrupt disabled

1: ARROK interrupt enabled

Bit 3 CMPOKIE: Compare register update OK Interrupt Enable

0: CMPOK interrupt disabled

1: CMPOK interrupt enabled

Bit 2 EXTTRIGIE: External trigger valid edge Interrupt Enable

0: EXTTRIG interrupt disabled

1: EXTTRIG interrupt enabled

Bit 1 ARRMIE: Autoreload match Interrupt Enable

0: ARRM interrupt disabled

1: ARRM interrupt enabled

Bit 0 CMPMIE: Compare match Interrupt Enable

0: CMPM interrupt disabled

1: CMPM interrupt enabled

Caution: The LPTIM_IER register must only be modified when the LPTIM is disabled (ENABLE bit reset to '0')

32.7.4 LPTIM configuration register (LPTIM_CFGR)

Address offset: 0x00C

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	TRIG SEL [3]	Res.	Res.	Res.	Res.	ENC	COUNT MODE	PRELOAD	WAVPOL	WAVE	TIMOUT	TRIGEN[1:0]		Res.
		rw					rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGSEL[2:0]			Res.	PRESC[2:0]			Res:	TRGFLT[1:0]		Res.	CKFLT[1:0]		CKPOL[1:0]		CKSEL
rw	rw	rw		rw	rw	rw		rw	rw		rw	rw	rw	rw	rw

Bits 31:30 Reserved, must be kept at reset value.

Bits 28:25 Reserved, must be kept at reset value.

Bit 24 ENC: Encoder mode enable

The ENC bit controls the Encoder mode

0: Encoder mode disabled

1: Encoder mode enabled

Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to

Section 32.3: LPTIM implementation.

Bit 23 COUNTMODE: counter mode enabled

The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:

0: the counter is incremented following each internal clock pulse

1: the counter is incremented following each valid clock pulse on the LPTIM external Input1

Bit 22 PRELOAD: Registers update mode

The PRELOAD bit controls the LPTIM_ARR and the LPTIM_CMP registers update modality

0: Registers are updated after each APB bus write access

1: Registers are updated at the end of the current LPTIM period

Bit 21 WAVPOL: Waveform shape polarity

The WAVEPOL bit controls the output polarity

0: The LPTIM output reflects the compare results between LPTIM_CNT and LPTIM_CMP

registers

1: The LPTIM output reflects the inverse of the compare results between LPTIM_CNT and LPTIM_CMP registers

Bit 20 WAVE: Waveform shape

The WAVE bit controls the output shape

0: Deactivate Set-once mode

1: Activate the Set-once mode

Bit 19 TIMOUT: Timeout enable

The TIMOUT bit controls the Timeout feature

0: A trigger event arriving when the timer is already started will be ignored

1: A trigger event arriving when the timer is already started will reset and restart the counter

Bits 18:17 TRIGEN[1:0]: Trigger enable and polarity

The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the

external trigger option is selected, three configurations are possible for the trigger active edge:

00: software trigger (counting start is initiated by software)

01: rising edge is the active edge

10: falling edge is the active edge

11: both edges are active edges

Bit 16 Reserved, must be kept at reset value.

Bits 29, TRIGSEL[3:0]: Trigger selector

15,14,13 The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 13 available sources:

0000: lptim_ext_trig0

0001: lptim_ext_trig1

0010: Iptim_ext_trig2

0011: lptim_ext_trig3

0100: lptim_ext_trig4

0101: lptim_ext_trig5

0110: lptim_ext_trig6

0111: Iptim_ext_trig7

1000: lptim_ext_trig8

1001: lptim_ext_trig9

1010: lptim_ext_trig10

1011: lptim_ext_trig11

1100: lptim_ext_trig12

Others: Reserved

See Section 32.4.2: LPTIM input and trigger mapping for details.

Bit 12 Reserved, must be kept at reset value.

Bits 11:9 PRESC[2:0]: Clock prescaler

The PRESC bits configure the prescaler division factor. It can be one among the following division factors:

000: /1

001: /2

010: 14

011: 78

100: /16

101: /32

110: /64

111: /128

Bit 8 Reserved, must be kept at reset value.

Bits 7:6 TRGFLT[1:0]: Configurable digital filter for trigger

The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature

00: any trigger active level change is considered as a valid trigger

01: trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger.

10: trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger.

11: trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger.

Bit 5 Reserved, must be kept at reset value. Bits 4:3 CKFLT[1:0]: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature

00: any external clock signal level change is considered as a valid transition

01: external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition.

10: external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition.

11: external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition.

Bits 2:1 CKPOL[1:0]: Clock polarity

If LPTIM is clocked by an external clock source:

When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter:

00 :the rising edge is the active edge used for counting.

If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. 01:the falling edge is the active edge used for counting If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. 10:both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency.

If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. 11: not allowed

Refer to Section 32.4.14: Encoder mode for more details about Encoder mode sub-modes.

Bit 0 CKSEL: Clock selector

The CKSEL bit selects which clock source the LPTIM will use:

0: LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)

1: LPTIM is clocked by an external clock source through the LPTIM external Input1

Caution: The LPTIM_CFGR register must only be modified when the LPTIM is disabled (ENABLE bit reset to '0').

32.7.5 LPTIM control register (LPTIM_CR)

Address offset: 0x010

Reset value: 0x00000000

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 RSTARE: Reset after read enable

This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register will asynchronously reset LPTIM_CNT register content.

This bit can be set only when the LPTIM is enabled. Bit 3 COUNTRST: Counter reset

This bit is set by software and cleared by hardware. When set to ’1’ this bit will trigger a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock).

This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware.

Caution: COUNTRST must never be set to '1' by software before it is already cleared to ' 0 ' by hardware. Software should consequently check that COUNTRST bit is already cleared to ' 0 ' before attempting to set it to '1'. Bit 2 CNTSTRT: Timer start in Continuous mode

This bit is set by software and cleared by hardware.

In case of software start (TRIGEN[1:0] = '00'), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than '00'), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected.

If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode.

This bit can be set only when the LPTIM is enabled. It will be automatically reset by hardware.

Bit 1 SNGSTRT: LPTIM start in Single mode

This bit is set by software and cleared by hardware.

In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode.

If the software start is disabled (TRIGEN[1:0] different than '00'), setting this bit starts the LPTIM in

single pulse mode as soon as an external trigger is detected.

If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the

following match between LPTIM_ARR and LPTIM_CNT registers.

This bit can only be set when the LPTIM is enabled. It will be automatically reset by hardware.

Bit 0 ENABLE: LPTIM enable

The ENABLE bit is set and cleared by software.

0:LPTIM is disabled

1:LPTIM is enabled

32.7.6 LPTIM compare register (LPTIM_CMP)

Address offset: 0x014

Reset value: 0x00000000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 CMP[15:0]: Compare value

CMP is the compare value used by the LPTIM.

Caution: The LPTIM_CMP register must only be modified when the LPTIM is enabled (ENABLE bit set to '1').

32.7.7 LPTIM autoreload register (LPTIM_ARR)

Address offset: 0x018

Reset value: 0x00000001

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 ARR[15:0]: Auto reload value

ARR is the autoreload value for the LPTIM.

This value must be strictly greater than the CMP[15:0] value.

Caution: The LPTIM_ARR register must only be modified when the LPTIM is enabled (ENABLE bit set to '1').

32.7.8 LPTIM counter register (LPTIM_CNT)

Address offset: 0x01C

Reset value: 0x00000000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 CNT[15:0]: Counter value

When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.

It should be noted that for a reliable LPTIM_CNT register read access, two consecutive read accesses must be performed and compared. A read access can be considered reliable when the values of the two consecutive read accesses are equal.

32.7.9 LPTIM option register (LPTIM_OR)

Address offset: 0x020

Reset value: 0x00000000

Res.	Resr	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	IN2[2:1]		IN1[2:1]		IN2[0]	IN1[0]
										rw	rw	rw	rw	rw	rw

Bits 31:6 Reserved, must be kept at reset value.

Bits 5:4 IN2[2:1]: LPTimer input 2 remap extension

Set and cleared by software.

00: connected to COMP2

01: connected to COMP4

10: connected to COMP6

11: connected to COMP6

32.7.10 LPTIM register map

The following table summarizes the LPTIM registers.

Table 319. LPTIM register map and reset values

Offset	Register name	31	300	23	23	27	26	23	24	23	22	21	2021	9	- 00	17	(6)	16	4	13	12	11	10	9	8	7	6	5	4	3	2	1	O
0x000	LPTIM_ISR		BOOD	y	THE	中华	30	8	COUT	5	BOOD	SHIP	SON	1,010	：	SCON	S	TOUT	中华	Suppose	3	时	坊中	时	新中心	Suppose	1)NMOC	PAR	HOYY	HOdWO	01811X3	Art	CHFF
0x000	Reset value																										0	0	0	0	0	0	0
0x004	LPTIM_ICR		a	3	3	y	y	3	CON	奶	3	3	3	CONDER	y y	：	3	8	3	3	3	3	y y	3	3	30	(1)	(1)	JOXOYY	HOXODIWO	HOONILLX3	JOWY	30WdW0
0x004	Reset value																										0	0	0	0	0	0	0
0x008	LPTIM_IER	3	3	3	超	3	3	38	S	3	3	La	gé	3	3	y y	1,010	3	y	5	3	：	STA	y1	3	好	.)3INMOC	(1) 3.1dN	JIJIOUV	31)10dW0	3101811.1X3	31WYY	3IWdWO
0x008	Reset value																										0	0	0	0	0	0	0
0x00C	LPTIM_CFGR	时	M	[8]hasonal	3	：	BUR	Suppose	Europe	EXCOWINNOC	avoid	70d3AVM	VALL	inowil	N351Y1		Light		[0.2]hasonal		mid	PEE			mi	17:1981		REPT	CHF		COND		13SYO
0x00C	Reset value			0					0	0	0	0	0	0	0	0		0	0	0		0	0	0		0	0		0	0	0	0	0
0x010	LPTIM_CR	时	：	y	3	y	部	好的	34	y	的	S	8	好	y	：	：	y	y	8	g	34	g	Let	鲜	8	y y	8	JYVISY	LSYINNOC	IVISINO	IVISONS	379VN3
0x010	Reset value																												0	0	0	0	0
0x014	LPTIM_CMP				d	a	(a)		3					8	8	d		CMP[15:0]
0x014	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x018	LPTIM_ARR				y	y	89	协	8	8	福	8	的	8	电	8	ARR[15:0]
0x018	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
0x01C	LPTIM_CNT																CNT[15:0]
0x01C	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x020	LPTIM OR			好	串串	3	：	8	LATE	明日	S	：	STRICAL	LIG	明日	13	华	串	a	串	中國	si	邮	3	：	B			NEW2	NEW-12		Nov-20	IMPO
0x020	Reset value																											0	0	0	0	0	0

If LPTIM does not support encoder mode feature, this bit is reserved. Please refer to Section 32.3: LPTIM implementation.

Refer to Section 2.2 on page 81 for the register boundary addresses.

33 Infrared interface (IRTIM)

An infrared interface (IRTIM) for remote control is available on the device. It can be used with an infrared LED to perform remote control functions.

It uses internal connections withTIM16, and TIM17 as shown in Figure 501.

To generate the infrared remote control signals, the IR interface must be enabled and TIM16 channel 1 (TIM16_OC1) and TIM17 channel 1 (TIM17_OC1) must be properly configured to generate correct waveforms.

The infrared receiver can be implemented easily through a basic input capture mode.

Figure 501. IRTIM internal hardware connections with TIM16 and TIM17

All standard IR pulse modulation modes can be obtained by programming the two timer output compare channels.

TIM17 is used to generate the high frequency carrier signal, while TIM16 generates the modulation envelope.

The infrared function is output on the IR_OUT pin. The activation of this function is done through the GPIOx_AFRx register by enabling the related alternate function bit.

The high sink LED driver capability (only available on the PB9 and PA13 pins) can be activated through the I2C_PB9_FMP bit in the SYSCFG_CFGR1 register and used to sink the high current needed to directly control an infrared LED.

34 AES hardware accelerator (AES)

34.1 Introduction

The AES hardware accelerator (AES) encrypts or decrypts data, using an algorithm and implementation fully compliant with the advanced encryption standard (AES) defined in Federal information processing standards (FIPS) publication 197.

The peripheral supports CTR, GCM, GMAC, CCM, ECB, and CBC chaining modes for key sizes of 128 or 256 bits.

AES is an AMBA AHB slave peripheral accessible through 32-bit single accesses only. Other access types generate an AHB error, and other than 32-bit writes may corrupt the register content.

The peripheral supports DMA single transfers for incoming and outgoing data (two DMA channels required).

34.2 AES main features

Compliance with NIST "Advanced encryption standard (AES), FIPS publication 197" from November 2001

128-bit data block processing

Support for cipher key lengths of 128-bit and 256-bit

Encryption and decryption with multiple chaining modes:

Electronic codebook (ECB) mode

Cipher block chaining (CBC) mode

Counter (CTR) mode

Galois counter mode (GCM)

Galois message authentication code (GMAC) mode

Counter with CBC-MAC (CCM) mode

51 or 75 clock cycle latency in ECB mode for processing one 128-bit block of data with, respectively, 128-bit or 256-bit key

Integrated round key scheduler to compute the last round key for ECB/CBC decryption

AMBA AHB slave peripheral, accessible through 32-bit word single accesses only

256-bit register for storing the cryptographic key (eight 32-bit registers)

128-bit register for storing initialization vector (four 32-bit registers)

32-bit buffer for data input and output

Automatic data flow control with support of single-transfer direct memory access (DMA) using two channels (one for incoming data, one for processed data)

Data-swapping logic to support 1-, 8-, 16- or 32-bit data

Possibility for software to suspend a message if AES needs to process another message with a higher priority, then resume the original message

34.3 AES implementation

The devices have one AES peripheral.

34.4 AES functional description

34.4.1 AES block diagram

Figure 502 shows the block diagram of AES.

34.4.2 AES internal signals

Table 320 describes the user relevant internal signals interfacing the AES peripheral.

Table 320. AES internal input/output signals

Signal name	Signal type	Description
aes_hclk	Input	AHB bus clock
aes_it	Output	AES interrupt request
aes_in_dma	Input/Output	Input DMA single request/acknowledge
aes_out_dma	Input/Output	Output DMA single request/acknowledge

34.4.3 AES cryptographic core

Overview

The AES cryptographic core consists of the following components:

AES core algorithm (AEA)

multiplier over a binary Galois field (GF2mul)

key input

initialization vector (IV) input

chaining algorithm logic (XOR, feedback/counter, mask)

The AES core works on 128-bit data blocks (four words) with 128-bit or 256-bit key length. Depending on the chaining mode, the AES requires zero or one 128-bit initialization vector IV.

The AES features the following modes of operation:

Mode 1:

Plaintext encryption using a key stored in the AES_KEYRx registers

Mode 2:

ECB or CBC decryption key preparation. It must be used prior to selecting Mode 3 with ECB or CBC chaining modes. The key prepared for decryption is stored automatically in the AES_KEYRx registers. Now the AES peripheral is ready to switch to Mode 3 for executing data decryption.

Mode 3:

Ciphertext decryption using a key stored in the AES_KEYRx registers. When ECB and CBC chaining modes are selected, the key must be prepared beforehand, through Mode 2.

Mode 4:

ECB or CBC ciphertext single decryption using the key stored in the AES_KEYRx registers (the initial key is derived automatically).

Note: Mode 2 and mode 4 are only used when performing ECB and CBC decryption.

When Mode 4 is selected only one decryption can be done, therefore usage of Mode 2 and Mode 3 is recommended instead.

The operating mode is selected by programming the MODE[1:0] bitfield of the AES_CR register. It may be done only when the AES peripheral is disabled.

Typical data processing

Typical usage of the AES is described in Section 34.4.4: AES procedure to perform a cipher operation on page 1512.

Note: The outputs of the intermediate AEA stages are never revealed outside the cryptographic boundary, with the exclusion of the IVI bitfield.

Chaining modes

The following chaining modes are supported by AES, selected through the CHMOD[2:0] bitfield of the AES_CR register:

Electronic code book (ECB)

Counter (CTR)

Galois counter mode (GCM)

Galois message authentication code (GMAC)

Counter with CBC-MAC (CCM)

Note: The chaining mode may be changed only when AES is disabled (bit EN of the AES_CR register cleared).

Principle of each AES chaining mode is provided in the following subsections.

Detailed information is in dedicated sections, starting from Section 34.4.8: AES basic chaining modes (ECB, CBC).

Galois/counter mode (GCM)

In Galois/counter mode (GCM), the plaintext message is encrypted while a message authentication code (MAC) is computed in parallel, thus generating the corresponding ciphertext and its MAC (also known as authentication tag). It is defined in NIST Special Publication 800-38D, Recommendation for Block Cipher Modes of Operation - Galois/Counter Mode (GCM) and GMAC.

GCM mode is based on AES in counter mode for confidentiality. It uses a multiplier over a fixed finite field for computing the message authentication code. It requires an initial value and a particular 128-bit block at the end of the message.

Galois message authentication code (GMAC) principle GMAC is similar to GCM, except that it is applied on a message composed only by plaintext authenticated data (that is, only header, no payload).

Figure 507. GMAC authentication principle

Galois message authentication code (GMAC) allows authenticating a message and generating the corresponding message authentication code (MAC). It is defined in NIST Special Publication 800-38D, Recommendation for Block Cipher Modes of Operation - Galois/Counter Mode (GCM) and GMAC.

Counter with CBC-MAC (CCM) principle

Figure 508. CCM encryption and authentication principle

In Counter with cipher block chaining-message authentication code (CCM) mode, the plaintext message is encrypted while a message authentication code (MAC) is computed in parallel, thus generating the corresponding ciphertext and the corresponding MAC (also known as tag). It is described by NIST in Special Publication 800-38C, Recommendation for Block Cipher Modes of Operation - The CCM Mode for Authentication and Confidentiality.

CCM mode is based on AES in counter mode for confidentiality and it uses CBC for computing the message authentication code. It requires an initial value.

Like GCM, the CCM chaining mode can be applied on a message composed only by plaintext authenticated data (that is, only header, no payload). Note that this way of using CCM is not called CMAC (it is not similar to GCM/GMAC), and its use is not recommended by NIST.

34.4.4 AES procedure to perform a cipher operation

Introduction

A typical cipher operation is explained below. Detailed information is provided in sections starting from Section 34.4.8: AES basic chaining modes (ECB, CBC).

Initialization of AES

To initialize AES, first disable it by clearing the EN bit of the AES_CR register. Then perform the following steps in any order:

Configure the AES mode, by programming the MODE[1:0] bitfield of the AES_CR register.

For encryption, select Mode 1 (MODE[1:0] = 00).

For decryption, select Mode 3 (MODE[1:0] = 10), unless ECB or CBC chaining modes are used. In this latter case, perform an initial key derivation of the encryption key, as described in Section 34.4.5: AES decryption round key preparation.

Select the chaining mode, by programming the CHMOD[2:0] bitfield of the AES_CR register.

Configure the data type (1-, 8-, 16- or 32-bit), with the DATATYPE[1:0] bitfield in the AES_CR register.

When it is required (for example in CBC or CTR chaining modes), write the initialization vector into the AES_IVRx registers.

Configure the key size (128-bit or 256-bit), with the KEYSIZE bitfield of the AES_CR register.

Write a symmetric key into the AES_KEYRx registers (4 or 8 registers depending on the key size).

Data append

This section describes different ways of appending data for processing, where the size of data to process is not a multiple of 128 bits.

For ECB or CBC mode, refer to Section 34.4.6: AES ciphertext stealing and data padding. The last block management in these cases is more complex than in the sequence described in this section.

Data append through polling

This method uses flag polling to control the data append through the following sequence:

Enable the AES peripheral by setting the EN bit of the AES_CR register.

Repeat the following sub-sequence until the payload is entirely processed:

a) Write four input data words into the AES_DINR register.

b) Wait until the status flag CCF is set in the AES_SR, then read the four data words from the AES_DOUTR register.

c) Clear the CCF flag, by setting the CCFC bit of the AES_CR register.

d) If the data block just processed is the second-last block of the message and the significant data in the last block to process is inferior to 128 bits, pad the remainder of the last block with zeros and, in case of GCM payload encryption or CCM payload decryption, specify the number of non-valid bytes, using the NPBLB bitfield of the AES_CR register, for AES to compute a correct tag;.

As it is the last block, discard the data that is not part of the data, then disable the AES peripheral by clearing the EN bit of the AES_CR register.

Note: Up to three wait cycles are automatically inserted between two consecutive writes to the AES_DINR register, to allow sending the key to the AES processor.

NPBLB bits are not used in header phase of GCM, GMAC and CCM chaining modes.

Data append using interrupt

The method uses interrupt from the AES peripheral to control the data append, through the following sequence:

Enable interrupts from AES by setting the CCFIE bit of the AES_CR register.

Enable the AES peripheral by setting the EN bit of the AES_CR register.

Write first four input data words into the AES_DINR register.

Handle the data in the AES interrupt service routine, upon interrupt:

a) Read four output data words from the AES_DOUTR register.

b) Clear the CCF flag and thus the pending interrupt, by setting the CCFC bit of the AES_CR register.

c) If the data block just processed is the second-last block of an message and the significant data in the last block to process is inferior to 128 bits, pad the remainder of the last block with zeros and, in case of GCM payload encryption or CCM payload decryption, specify the number of non-valid bytes, using the NPBLB bitfield of the AES_CR register, for AES to compute a correct tag;. Then proceed with point

4 e

d) If the data block just processed is the last block of the message, discard the data that is not part of the data, then disable the AES peripheral by clearing the EN bit of the AES_CR register and quit the interrupt service routine.

e) Write next four input data words into the AES_DINR register and quit the interrupt service routine.

Note: AES is tolerant of delays between consecutive read or write operations, which allows, for example, an interrupt from another peripheral to be served between two AES computations.

NPBLB bits are not used in header phase of GCM, GMAC and CCM chaining modes.

With this method, all the transfers and processing are managed by DMA and AES. To use the method, proceed as follows:

Prepare the last four-word data block (if the data to process does not fill it completely), by padding the remainder of the block with zeros.

Configure the DMA controller so as to transfer the data to process from the memory to the AES peripheral input and the processed data from the AES peripheral output to the memory, as described in Section 34.4.16: AES DMA interface. Configure the DMA controller so as to generate an interrupt on transfer completion. In case of GCM payload encryption or CCM payload decryption, DMA transfer must not include the last four-word block if padded with zeros. The sequence described in Data append through polling must be used instead for this last block, because NPBLB bits must be setup before processing the block, for AES to compute a correct tag.

Enable the AES peripheral by setting the EN bit of the AES_CR register

Enable DMA requests by setting the DMAINEN and DMAOUTEN bits of the AES_CR

Upon DMA interrupt indicating the transfer completion, get the AES-processed data from the memory.

Note: The CCF flag has no use with this method, because the reading of the AES_DOUTR register is managed by DMA automatically, without any software action, at the end of the computation phase.

NPBLB bits are not used in header phase of GCM, GMAC, and CCM chaining modes.

34.4.5 AES decryption round key preparation

Internal key schedule is used to generate AES round keys. In AES encryption, the round 0 key is the one stored in the key registers. AES decryption must start using the last round key. As the encryption key is stored in memory, a special key scheduling must be performed to obtain the decryption key. This key scheduling is only required for AES decryption in ECB and CBC modes.

Recommended method is to select the Mode 2 by setting to 01 the MODE[1:0] bitfield of the AES_CR (key process only), then proceed with the decryption by setting MODE[1:0] to 10 (Mode 3, decryption only). Mode 2 usage is described below:

Disable the AES peripheral by clearing the EN bit of the AES_CR register.

Select Mode 2 by setting to 01 the MODE[1:0] bitfield of the AES_CR. The CHMOD[2:0] bitfield is not significant in this case because this key derivation mode is independent of the chaining algorithm selected.

Set key length to 128 or 256 bits, via KEYSIZE bit of AES_CR register.

Write the AES_KEYRx registers (128 or 256 bits) with encryption key, as shown in Figure 509. Writes to the AES_IVRx registers have no effect.

Enable the AES peripheral, by setting the EN bit of the AES_CR register.

Wait until the CCF flag is set in the AES_SR register.

Clear the CCF flag. Derived key is available in AES core, ready to use for decryption. Application can also read the AES_KEYRx register to obtain the derived key if needed, as shown in Figure 509 (the processed key is loaded automatically into the AES_KEYRx registers).

Note: The AES is disabled by hardware when the derivation key is available.

To restart a derivation key computation, repeat steps 4, 5, 6, and 7.

Figure 509. Encryption key derivation for ECB/CBC decryption (Mode 2)

If the software stores the initial key prepared for decryption, it is enough to do the key schedule operation only once for all the data to be decrypted with a given cipher key.

Note: The operation of the key preparation lasts 59 or 82 clock cycles, depending on the key size (128- or 256-bit).

34.4.6 AES ciphertext stealing and data padding

When using AES in ECB or CBC modes to manage messages the size of which is not a multiple of the block size (128 bits), ciphertext stealing techniques are used, such as those described in NIST Special Publication 800-38A, Recommendation for Block Cipher Modes of Operation: Three Variants of Ciphertext Stealing for CBC Mode. Since the AES peripheral does not support such techniques, the application must complete the last block of input data using data from the second last block.

Note: Ciphertext stealing techniques are not documented in this reference manual.

Similarly, when AES is used in other modes than ECB or CBC, an incomplete input data block (that is, block with input data shorter than 128 bits) must be padded with zeros prior to encryption (that is, extra bits must be appended to the trailing end of the data string). After decryption, the extra bits must be discarded. As AES does not implement automatic data padding operation to the last block, the application must follow the recommendation given in Section 34.4.4: AES procedure to perform a cipher operation on page 1512 to manage messages the size of which is not a multiple of 128 bits.

Note:

DATATYPE[1:0] field of the AES_CR register (see Section 34.4.13: AES data registers and data swapping for details).

34.4.7 AES task suspend and resume

A message can be suspended if another message with a higher priority must be processed. When this highest priority message is sent, the suspended message can resume in both encryption or decryption mode.

Suspend/resume operations do not break the chaining operation and the message processing can resume as soon as AES is enabled again to receive the next data block.

Figure 510 gives an example of suspend/resume operation: Message 1 is suspended in order to send a shorter and higher-priority Message 2. A detailed description of suspend/resume operations is in the sections dedicated to each AES mode.

Figure 510. Example of suspend mode management

34.4.8 AES basic chaining modes (ECB, CBC)

Overview

This section gives a brief explanation of the four basic operation modes provided by the AES core: ECB encryption, ECB decryption, CBC encryption and CBC decryption. For detailed information, refer to the FIPS publication 197 from November 26, 2001.

Figure 511 illustrates the electronic codebook (ECB) encryption.

Figure 511. ECB encryption

In ECB encrypt mode, the 128-bit plaintext input data block Px in the AES_DINR register first goes through bit/byte/half-word swapping. The swap result Ix is processed with the AES core set in encrypt mode, using a 128- or 256-bit key. The encryption result Ox goes through bit/byte/half-word swapping, then is stored in the AES_DOUTR register as 128-bit ciphertext output data block Cx. The ECB encryption continues in this way until the last complete plaintext block is encrypted.

Figure 512 illustrates the electronic codebook (ECB) decryption.

Figure 512. ECB decryption

To perform an AES decryption in the ECB mode, the secret key has to be prepared by collecting the last-round encryption key (which requires to first execute the complete key schedule for encryption), and using it as the first-round key for the decryption of the ciphertext. This preparation is supported by the AES core. In ECB decrypt mode, the 128-bit ciphertext input data block C1 in the AES_DINR register first goes through bit/byte/half-word swapping. The keying sequence is reversed compared to that of the ECB encryption. The swap result I1 is processed with the AES core set in decrypt mode, using the formerly prepared decryption key. The decryption result goes through bit/byte/half-word swapping, then is stored in the AES_DOUTR register as 128-bit plaintext output data block P1. The ECB decryption continues in this way until the last complete ciphertext block is decrypted.

Figure 513 illustrates the cipher block chaining (CBC) encryption.

Figure 513. CBC encryption

In CBC encrypt mode, the first plaintext input block, after bit/byte/half-word swapping (P1'), is XOR-ed with a 128-bit IVI bitfield (initialization vector and counter), producing the I1 input data for encrypt with the AES core, using a 128- or 256-bit key. The resulting 128-bit output block O1, after swapping operation, is used as ciphertext C1. The O1 data is then XOR-ed with the second-block plaintext data P2' to produce the I2 input data for the AES core to produce the second block of ciphertext data. The chaining of data blocks continues in this way until the last plaintext block in the message is encrypted.

If the message size is not a multiple of 128 bits, the final partial data block is encrypted in the way explained in Section 34.4.6: AES ciphertext stealing and data padding.

Figure 514 illustrates the cipher block chaining (CBC) decryption. In CBC decrypt mode, like in ECB decrypt mode, the secret key must be prepared to perform an AES decryption.

Figure 514. CBC decryption

After the key preparation process, the decryption goes as follows: the first 128-bit ciphertext block (after the swap operation) is used directly as the AES core input block I1 for decrypt operation, using the 128-bit or 256-bit key. Its output O1 is XOR-ed with the 128-bit IVI field (that must be identical to that used during encryption) to produce the first plaintext block P1.

The second ciphertext block is processed in the same way as the first block, except that the I1 data from the first block is used in place of the initialization vector.

The decryption continues in this way until the last complete ciphertext block is decrypted.

If the message size is not a multiple of 128 bits, the final partial data block is decrypted in the way explained in Section 34.4.6: AES ciphertext stealing and data padding.

For more information on data swapping, refer to Section 34.4.13: AES data registers and data swapping.

ECB/CBC encryption sequence

The sequence of events to perform an ECB/CBC encryption (more detail in Section 34.4.4):

Disable the AES peripheral by clearing the EN bit of the AES_CR register.

Select the Mode 1 by setting to 00 the MODE[1:0] bitfield of the AES_CR register and select ECB or CBC chaining mode by setting the CHMOD[2:0] bitfield of the AES_CR register to 000 or 001 , respectively. Data type can also be defined, using DATATYPE[1:0] bitfield.

Select 128- or 256-bit key length through the KEYSIZE bit of the AES_CR register.

Write the AES_KEYRx registers (128 or 256 bits) with encryption key. Fill the

AES_IVRx registers with the initialization vector data if CBC mode has been selected.

Enable the AES peripheral by setting the EN bit of the AES_CR register.

Write the AES_DINR register four times to input the plaintext (MSB first), as shown in Figure 515.

Wait until the CCF flag is set in the AES_SR register.

Read the AES_DOUTR register four times to get the ciphertext (MSB first) as shown in Figure 515. Then clear the CCF flag by setting the CCFC bit of the AES_CR register.

Repeat steps 6-7-8 to process all the blocks with the same encryption key.

Figure 515. ECB/CBC encryption (Mode 1)

ECB/CBC decryption sequence

The sequence of events to perform an AES ECB/CBC decryption is as follows (More detail in Section 34.4.4).

Follow the steps described in Section 34.4.5: AES decryption round key preparation, in order to prepare the decryption key in AES core.

Select the Mode 3 by setting to 10 the MODE[1:0] bitfield of the AES_CR register and select ECB or CBC chaining mode by setting the CHMOD[2:0] bitfield of the AES_CR register to 000 or 001 , respectively. Data type can also be defined, using DATATYPE[1:0] bitfield. KEYSIZE bitfield must be kept as-is.

Write the AES_IVRx registers with the initialization vector (required in CBC mode only).

Enable AES by setting the EN bit of the AES_CR register.

Write the AES_DINR register four times to input the cipher text (MSB first), as shown in Figure 516.

Wait until the CCF flag is set in the AES_SR register.

Read the AES_DOUTR register four times to get the plain text (MSB first), as shown in Figure 516. Then clear the CCF flag by setting the CCFC bit of the AES_CR register.

Repeat steps 5-6-7 to process all the blocks encrypted with the same key.

Figure 516. ECB/CBC decryption (Mode 3)

Suspend/resume operations in ECB/CBC modes

To suspend the processing of a message, proceed as follows:

If DMA is used, stop the AES DMA transfers to the IN FIFO by clearing the DMAINEN bit of the AES_CR register.

If DMA is not used, read four times the AES_DOUTR register to save the last processed block. If DMA is used, wait until the CCF flag is set in the AES_SR register then stop the DMA transfers from the OUT FIFO by clearing the DMAOUTEN bit of the AES_CR register.

If DMA is not used, poll the CCF flag of the AES_SR register until it becomes 1 (computation completed).

Clear the CCF flag by setting the CCFC bit of the AES_CR register.

Save initialization vector registers (only required in CBC mode as AES_IVRx registers are altered during the data processing).

Disable the AES peripheral by clearing the bit EN of the AES_CR register.

Save the AES_CR register and clear the key registers if they are not needed, to process the higher priority message.

If DMA is used, save the DMA controller status (pointers for IN and OUT data transfers, number of remaining bytes, and so on).

Note:

In point 7, the derived key information stored in AES_KEYRx registers can optionally be saved in memory if the interrupted process is a decryption. Otherwise those registers do not need to be saved as the original key value is known by the application

To resume the processing of a message, proceed as follows:

If DMA is used, configure the DMA controller so as to complete the rest of the FIFO IN and FIFO OUT transfers.

Disable the AES peripheral by clearing the EN bit of the AES_CR register.

Restore AES_CR register (with correct KEYSIZE) then restore AES_KEYRx registers. In case of decryption, derived key information can be written in AES_KEYRx register instead of the original key value.

Prepare the decryption key as described in Section 34.4.5: AES decryption round key preparation (only required for ECB or CBC decryption). This step is not necessary if derived key information is loaded in AES_KEYRx registers.

Restore AES_IVRx registers using the saved configuration (only required in CBC mode).

Enable the AES peripheral by setting the EN bit of the AES_CR register.

If DMA is used, enable AES DMA transfers by setting the DMAINEN and DMAOUTEN bits of the AES_CR register.

Alternative single ECB/CBC decryption using Mode 4

The sequence of events to perform a single round of ECB/CBC decryption using Mode 4 is:

Disable the AES peripheral by clearing the EN bit of the AES_CR register.

Select the Mode 4 by setting to 11 the MODE[1:0] bitfield of the AES_CR register and select ECB or CBC chaining mode by setting the CHMOD[2:0] bitfield of the AES_CR register to $0 \times 0$ or $0 \times 1$ ,respectively.

Select key length of 128 or 256 bits via KEYSIZE bitfield of the AES_CR register.

Write the AES_KEYRx registers with the encryption key. Write the AES_IVRx registers if the CBC mode is selected.

Enable the AES peripheral by setting the EN bit of the AES_CR register.

Write the AES_DINR register four times to input the cipher text (MSB first).

Wait until the CCF flag is set in the AES_SR register.

Read the AES_DOUTR register four times to get the plain text (MSB first). Then clear the CCF flag by setting the CCFC bit of the AES_CR register.

Note: When mode 4 is selected mode 3 cannot be used.

In mode 4, the AES_KEYRx registers contain the encryption key during all phases of the processing. No derivation key is stored in these registers. It is stored internally in AES.

34.4.9 AES counter (CTR) mode

Overview

The counter mode (CTR) uses AES as a key-stream generator. The generated keys are then XOR-ed with the plaintext to obtain the ciphertext.

CTR chaining is defined in NIST Special Publication 800-38A, Recommendation for Block Cipher Modes of Operation. A typical message construction in CTR mode is given in Figure 517.

Figure 517. Message construction in CTR mode

MSv42156V1

The structure of this message is:

A 16-byte initial counter block (ICB), composed of two distinct fields:

Initialization vector (IV): a 96-bit value that must be unique for each encryption cycle with a given key.

Counter: a 32-bit big-endian integer that is incremented each time a block processing is completed. The initial value of the counter must be set to 1 .

The plaintext $P$ is encrypted as ciphertext $C$ ,with a known length. This length can be non-multiple of 16 bytes, in which case a plaintext padding is required.

CTR encryption and decryption

Figure 518 and Figure 519 describe the CTR encryption and decryption process, respectively, as implemented in the AES peripheral. The CTR mode is selected by writing 010 to the CHMOD[2:0] bitfield of AES_CR register.

Figure 519. CTR decryption

In CTR mode, the cryptographic core output (also called keystream) Ox is XOR-ed with relevant input block (Px' for encryption, Cx' for decryption), to produce the correct output block (Cx' for encryption, Px' for decryption). Initialization vectors in AES must be initialized as shown in Table 321.

Table 321. CTR mode initialization vector definition

AES_IVR3[31:0]	AES_IVR2[31:0]	AES_IVR1[31:0]	AES_IVR0[31:0]
IVI[127:96]	IVI[95:64]	IVI[63:32]	IVI[31:0\} 32-bit counter = 0x0001

Unlike in CBC mode that uses the AES_IVRx registers only once when processing the first data block, in CTR mode AES_IVRx registers are used for processing each data block, and the AES peripheral increments the counter bits of the initialization vector (leaving the nonce bits unchanged).

CTR decryption does not differ from CTR encryption, since the core always encrypts the current counter block to produce the key stream that is then XOR-ed with the plaintext (CTR encryption) or ciphertext (CTR decryption) input. In CTR mode, the MODE[1:0] bitfield setting 01 (key derivation) is forbidden and all the other settings default to encryption mode.

The sequence of events to perform an encryption or a decryption in CTR chaining mode:

Disable the AES peripheral by clearing the EN bit of the AES_CR register.

Select CTR chaining mode by setting to 010 the CHMOD[2:0] bitfield of the AES_CR register. Set MODE[1:0] bitfield to any value other than 01.

Initialize the AES_KEYRx registers, and load the AES_IVRx registers as described in Table 321.

Set the EN bit of the AES_CR register, to start encrypting the current counter (EN is automatically reset when the calculation finishes).

If it is the last block, pad the data with zeros to have a complete block, if needed.

Append data in AES, and read the result. The three possible scenarios are described in Section 34.4.4: AES procedure to perform a cipher operation.

Repeat the previous step till the second-last block is processed. For the last block, apply the two previous steps and discard the bits that are not part of the payload (if the size of the significant data in the last input block is less than 16 bytes).

Suspend/resume operations in CTR mode

Like for the CBC mode, it is possible to interrupt a message to send a higher priority message, and resume the message that was interrupted. Detailed CBC suspend/resume sequence is described in Section 34.4.8: AES basic chaining modes (ECB, CBC).

Note: Like for CBC mode, the AES_IVRx registers must be reloaded during the resume operation.

34.4.10 AES Galois/counter mode (GCM)

Overview

The AES Galois/counter mode (GCM) allows encrypting and authenticating a plaintext message into the corresponding ciphertext and tag (also known as message authentication code). To ensure confidentiality, GCM algorithm is based on AES counter mode. It uses a multiplier over a fixed finite field to generate the tag.

GCM chaining is defined in NIST Special Publication 800-38D, Recommendation for Block Cipher Modes of Operation - Galois/Counter Mode (GCM) and GMAC. A typical message construction in GCM mode is given in Figure 520.

Figure 520. Message construction in GCM

The message has the following structure:

16-byte initial counter block (ICB), composed of two distinct fields:

Initialization vector (IV): a 96-bit value that must be unique for each encryption cycle with a given key. Note that the GCM standard supports IVs with less than 96 bits, but in this case strict rules apply.

Counter: a 32-bit big-endian integer that is incremented each time a block processing is completed. According to NIST specification, the counter value is 0x2 when processing the first block of payload.

Authenticated header AAD (also knows as additional authentication data) has a known length $Len (A)$ that may be a non-multiple of 16 bytes,and must not exceed $2^{64} - 1$ bits. This part of the message is only authenticated,not encrypted.

Plaintext message $P$ is both authenticated and encrypted as ciphertext $C$ ,with a known length $Len (P)$ that may be non-multiple of 16 bytes,and cannot exceed $2^{32} - 2$ 128-bit blocks.

Last block contains the AAD header length (bits [32:63]) and the payload length (bits [96:127]) information, as shown in Table 322.

The GCM standard specifies that ciphertext

C

has the same bit length as the plaintext

P

When a part of the message (AAD or P) has a length that is a non-multiple of 16-bytes a special padding scheme is required.

Table 322. GCM last block definition

Endianness	Bit[0] --------- Bit[31]	Bit[32]---------- Bit[63]	Bit[64] -------- Bit[95]	Bit[96] -------- Bit[127]
Input data	0x0	AAD length[31:0]	0x0	Payload length[31:0]

GCM processing

Figure 521 describes the GCM implementation in the AES peripheral. The GCM is selected by writing 011 to the CHMOD[2:0] bitfield of the AES_CR register.

The mechanism for the confidentiality of the plaintext in GCM mode is similar to that in the Counter mode, with a particular increment function (denoted 32-bit increment) that generates the sequence of input counter blocks.

AES_IVRx registers keeping the counter block of data are used for processing each data block. The AES peripheral automatically increments the Counter[31:0] bitfield. The first counter block (CB1) is derived from the initial counter block ICB by the application software (see Table 323).

Table 323. Initialization of AES_IVRx registers in GCM mode

AES_IVR3[31:0]	AES_IVR2[31:0]	AES_IVR1[31:0]	AES_IVR0[31:0]
ICB[127:96]	ICB[95:64]	ICB[63:32]	ICB[31:0] 32-bit counter = 0x0002

The authentication mechanism in GCM mode is based on a hash function called GF2mul that performs multiplication by a fixed parameter,called hash subkey

(H)

,within a binary Galois field.

A GCM message is processed through the following phases, further described in next subsections:

Init phase: AES prepares the GCM hash subkey (H).

Header phase: AES processes the additional authenticated data (AAD), with hash computation only.

Payload phase: AES processes the plaintext (P) with hash computation, counter block encryption and data XOR-ing. It operates in a similar way for ciphertext (C).

Final phase: AES generates the authenticated tag (T) using the last block of the message.

GCM init phase

During this first step,the GCM hash subkey

(H)

is calculated and saved internally,to be used for processing all the blocks. The recommended sequence is:

Disable the AES peripheral by clearing the EN bit of the AES_CR register.

Select GCM chaining mode, by setting to 011 the CHMOD[2:0] bitfield of the AES_CR register, and optionally, set the DATATYPE[1:0] bitfield.

Indicate the Init phase, by setting to 00 the GCMPH[1:0] bitfield of the AES_CR register.

Set the MODE[1:0] bitfield of the AES_CR register to 00 or 10. Although the bitfield is only used in payload phase, it is recommended to set it in the Init phase and keep it unchanged in all subsequent phases.

Initialize the AES_KEYRx registers with a key, and initialize AES_IVRx registers with the information as defined in Table 323.

Start the calculation of the hash key, by setting to 1 the EN bit of the AES_CR register (EN is automatically reset when the calculation finishes).

Wait until the end of computation, indicated by the CCF flag of the AES_SR transiting to 1. Alternatively, use the corresponding interrupt.

Clear the CCF flag of the AES_SR register, by setting the CCFC bit of the AES_CR register.

GCM header phase

This phase coming after the GCM Init phase must be completed before the payload phase.

The sequence to execute, identical for encryption and decryption, is:

Indicate the header phase, by setting to 01 the GCMPH[1:0] bitfield of the AES_CR register. Do not modify the MODE[1:0] bitfield as set in the Init phase.

Enable the AES peripheral by setting the EN bit of the AES_CR register.

If it is the last block and the AAD size in the block is inferior to 128 bits, pad the remainder of the block with zeros. Then append the data block into AES in one of ways described in Section 34.4.4: AES procedure to perform a cipher operation. No data is read during this phase.

Repeat the step 3 until the last additional authenticated data block is processed.

Note:

The header phase can be skipped if there is no AAD, that is, Len(A) = 0.

GCM payload phase

This phase, identical for encryption and decryption, is executed after the GCM header

phase. During this phase, the encrypted/decrypted payload is stored in the AES_DOUTR register. The sequence to execute is:

Indicate the payload phase, by setting to 10 the GCMPH[1:0] bitfield of the AES_CR register. Do not modify the MODE[1:0] bitfield as set in the Init phase.

If the header phase was skipped, enable the AES peripheral by setting the EN bit of the AES_CR register.

If it is the last block and the plaintext (encryption) or ciphertext (decryption) size in the block is inferior to 128 bits, pad the remainder of the block with zeros.

Append the data block into AES in one of ways described in Section 34.4.4: AES procedure to perform a cipher operation on page 1512, and read the result.

Repeat the previous step till the second-last plaintext block is encrypted or till the last block of ciphertext is decrypted. For the last block of plaintext (encryption only), execute the two previous steps. For the last block, discard the bits that are not part of the payload when the last block size is less than 16 bytes.

Note: The payload phase can be skipped if there is no payload data, that is, Len(C) = 0 (see GMAC mode).

GCM final phase

In this last phase, the AES peripheral generates the GCM authentication tag and stores it in the AES_DOUTR register. The sequence to execute is:

Indicate the final phase, by setting to 11 the GCMPH[1:0] bitfield of the AES_CR

Compose the data of the block, by concatenating the AAD bit length and the payload bit length, as shown in Table 322. Write the block into the AES_DINR register.

Wait until the end of computation, indicated by the CCF flag of the AES_SR transiting to 1 .

Get the GCM authentication tag, by reading the AES_DOUTR register four times.

Clear the CCF flag of the AES_SR register, by setting the CCFC bit of the AES_CR register.

Disable the AES peripheral, by clearing the bit EN of the AES_CR register. If it is an authenticated decryption, compare the generated tag with the expected tag passed with the message.

Note: In the final phase, data is written to AES_DINR normally (no swapping), while swapping is applied to tag data read from AES_DOUTR.

When transiting from the header or the payload phase to the final phase, the AES peripheral must not be disabled, otherwise the result is wrong.

Suspend/resume operations in GCM mode

To suspend the processing of a message, proceed as follows:

If DMA is used, stop the AES DMA transfers to the IN FIFO by clearing the DMAINEN bit of the AES_CR register. If DMA is not used, make sure that the current computation is completed, which is indicated by the CCF flag of the AES_SR register set to 1.

In the payload phase, if DMA is not used, read four times the AES_DOUTR register to save the last-processed block. If DMA is used, wait until the CCF flag is set in the AES_SR register then stop the DMA transfers from the OUT FIFO by clearing the DMAOUTEN bit of the AES_CR register.

Clear the CCF flag of the AES_SR register, by setting the CCFC bit of the AES_CR register.

Save the AES_SUSPxR registers in the memory,where $x$ is from 0 to 7 .

In the payload phase, save the AES_IVRx registers as, during the data processing, they changed from their initial values. In the header phase, this step is not required.

Disable the AES peripheral, by clearing the EN bit of the AES_CR register.

Save the current AES configuration in the memory, excluding the initialization vector registers AES_IVRx. Key registers do not need to be saved as the original key value is known by the application.

If DMA is used, save the DMA controller status (pointers for IN data transfers, number of remaining bytes, and so on). In the payload phase, pointers for OUT data transfers must also be saved.

To resume the processing of a message, proceed as follows:

If DMA is used, configure the DMA controller in order to complete the rest of the FIFO IN transfers. In the payload phase, the rest of the FIFO OUT transfers must also be configured in the DMA controller.

Disable the AES peripheral by clearing the EN bit of the AES_CR register.

Write the suspend register values, previously saved in the memory, back into their corresponding AES_SUSPxR registers,where $x$ is from 0 to 7 .

In the payload phase, write the initialization vector register values, previously saved in the memory, back into their corresponding AES_IVRx registers. In the header phase, write initial setting values back into the AES_IVRx registers.

Restore the initial setting values in the AES_CR and AES_KEYRx registers.

Enable the AES peripheral by setting the EN bit of the AES_CR register.

If DMA is used, enable AES DMA requests by setting the DMAINEN bit (and DMAOUTEN bit if in payload phase) of the AES_CR register.

34.4.11 AES Galois message authentication code (GMAC)

Overview

The Galois message authentication code (GMAC) allows the authentication of a plaintext, generating the corresponding tag information (also known as message authentication code). It is based on GCM algorithm, as defined in NIST Special Publication 800-38D, Recommendation for Block Cipher Modes of Operation - Galois/Counter Mode (GCM) and GMAC.

Suspend/resume operations in GMAC

In GMAC mode, the sequence described for the GCM applies except that only the header phase can be interrupted.

34.4.12 AES counter with CBC-MAC (CCM)

Overview

The AES counter with cipher block chaining-message authentication code (CCM) algorithm allows encryption and authentication of plaintext, generating the corresponding ciphertext and tag (also known as message authentication code). To ensure confidentiality, the CCM algorithm is based on AES in counter mode. It uses cipher block chaining technique to generate the message authentication code. This is commonly called CBC-MAC.

Note: NIST does not approve this CBC-MAC as an authentication mode outside the context of the CCM specification.

CCM chaining is specified in NIST Special Publication 800-38C, Recommendation for Block Cipher Modes of Operation - The CCM Mode for Authentication and Confidentiality. A typical message construction for CCM is given in Figure 524.

Figure 524. Message construction in CCM mode

The structure of the message is:

16-byte first authentication block (B0), composed of three distinct fields:

Q: a bit string representation of the octet length of $P (Len (P))$

Nonce (N): a single-use value (that is, a new nonce must be assigned to each new communication) of $Len (N)$ size. The sum $Len (N) + Len (P)$ must be equal to 15 bytes.

Flags: most significant octet containing four flags for control information, as specified by the standard. It contains two 3-bit strings to encode the values $t$ (MAC length expressed in bytes) and $Q$ (plaintext length such that Len(P) $< 2^{8 q}$ bytes). The counter blocks range associated to $Q$ is equal to $2^{8 Q - 4}$ ,that is,if the maximum value of $Q$ is 8,the counter blocks used in cipher must be on 60 bits.

16-byte blocks (B) associated to the Associated Data (A).

This part of the message is only authenticated, not encrypted. This section has a

known length

Len (A)

that can be a non-multiple of 16 bytes (see Figure 524). The standard also states that, on MSB bits of the first message block (B1), the associated data length expressed in bytes (a) must be encoded as follows:

If $0 < a < 2^{16} - 2^{8}$ ,then it is encoded as ${[a]}_{16}$ ,that is,on two bytes.

If $2^{16} - 2^{8} < a < 2^{32}$ ,then it is encoded as 0 xff $∥ 0$ xfe $∥ {[a]}_{32}$ ,that is,on six bytes.

If $2^{32} < a < 2^{64}$ ,then it is encoded as 0xff $∥$ 0xff $∥ {[a]}_{64}$ ,that is,on ten bytes.

16-byte blocks (B) associated to the plaintext message $P$ ,which is both authenticated and encrypted as ciphertext $C$ ,with a known length $Len (P)$ . This length can be a nonmultiple of 16 bytes (see Figure 524).

Encrypted MAC (T) of length Len(T) appended to the ciphertext C of overall length $Len (C)$ .

When a part of the message (A or P) has a length that is a non-multiple of 16-bytes, a special padding scheme is required.

Note: CCM chaining mode can also be used with associated data only (that is, no payload).

As an example, the C. 1 section in NIST Special Publication 800-38C gives the following values (hexadecimal numbers):

N : 10111213141516 (Len (N) = 56 bits or 7 bytes)

A: 00010203 04050607 (Len(A) = 64 bits or 8 bytes)

P: 20212223 (Len(P) = 32 bits or 4 bytes)

T: 6084341B (Len(T) = 32 bits or t = 4)

B0: 4F101112 13141516 00000000 00000004

B1: 00080001 02030405 06070000 00000000

B2: 20212223 00000000 00000000 00000000

CTR0: 0710111213 141516 00000000 00000000

CTR1: 0710111213 141516 00000000 00000001

Generation of formatted input data blocks Bx (especially B0 and B1) must be managed by the application.

CCM processing

Figure 525 describes the CCM implementation within the AES peripheral (encryption example). This mode is selected by writing 100 into the CHMOD[2:0] bitfield of the AES_CR register.

Figure 525. CCM mode authenticated encryption

The data input to the generation-encryption process are a valid nonce, a valid payload string, and a valid associated data string, all properly formatted. The CBC chaining mechanism is applied to the formatted plaintext data to generate a MAC, with a known length. Counter mode encryption that requires a sufficiently long sequence of counter blocks as input, is applied to the payload string and separately to the MAC. The resulting ciphertext

C

is the output of the generation-encryption process on plaintext

P

AES_IVRx registers are used for processing each data block, AES automatically incrementing the CTR counter with a bit length defined by the first block B0. Table 324 shows how the application must load the B0 data.

Note: The AES peripheral in CCM mode supports counters up to 64 bits, as specified by NIST.

Table 324. Initialization of AES_IVRx registers in CCM mode

AES_IVR3[31:0]	AES_IVR2[31:0]	AES_IVR1[31:0]	AES_IVR0[31:0]
B0[127:96]	B0[95:64]	B0[63:32]	B0[31:0]

Note: In this mode, the settings 01 and 11 of the MODE[1:0] bitfield are forbidden.

A CCM message is processed through the following phases, further described in next subsections:

Init phase: AES processes the first block and prepares the first counter block.

Header phase: AES processes associated data (A), with tag computation only.

Payload phase: IP processes plaintext (P), with tag computation, counter block encryption, and data XOR-ing. It works in a similar way for ciphertext (C).

Final phase: AES generates the message authentication code (MAC).

CCM Init phase

In this phase, the first block B0 of the CCM message is written into the AES_IVRx register. The AES_DOUTR register does not contain any output data. The recommended sequence is:

Disable the AES peripheral by clearing the EN bit of the AES_CR register.

Select CCM chaining mode, by setting to 100 the CHMOD[2:0] bitfield of the AES_CR register, and optionally, set the DATATYPE[1:0] bitfield.

Indicate the Init phase, by setting to 00 the GCMPH[1:0] bitfield of the AES_CR register.

Set the MODE[1:0] bitfield of the AES_CR register to 00 or 10. Although the bitfield is only used in payload phase, it is recommended to set it in the Init phase and keep it unchanged in all subsequent phases.

Initialize the AES_KEYRx registers with a key, and initialize AES_IVRx registers with B0 data as described in Table 324.

Start the calculation of the counter, by setting to 1 the EN bit of the AES_CR register (EN is automatically reset when the calculation finishes).

Wait until the end of computation, indicated by the CCF flag of the AES_SR transiting to 1. Alternatively, use the corresponding interrupt.

Clear the CCF flag in the AES_SR register, by setting to 1 the CCFC bit of the AES_CR register.

CCM header phase

This phase coming after the GCM Init phase must be completed before the payload phase. During this phase, the AES_DOUTR register does not contain any output data.

The sequence to execute, identical for encryption and decryption, is:

Indicate the header phase, by setting to 01 the GCMPH[1:0] bitfield of the AES_CR register. Do not modify the MODE[1:0] bitfield as set in the Init phase.

Enable the AES peripheral by setting the EN bit of the AES_CR register.

If it is the last block and the AAD size in the block is inferior to 128 bits, pad the remainder of the block with zeros. Then append the data block into AES in one of ways described in Section 34.4.4: AES procedure to perform a cipher operation. No data is read during this phase.

Repeat the step 3 until the last additional authenticated data block is processed.

Note: The header phase can be skipped if there is no associated data, that is, Len(A) = 0. The first block of the associated data (B1) must be formatted by software, with the associated data length.

CCM payload phase (encryption or decryption)

This phase, identical for encryption and decryption, is executed after the CCM header phase. During this phase, the encrypted/decrypted payload is stored in the AES_DOUTR register. The sequence to execute is:

Indicate the payload phase, by setting to 10 the GCMPH[1:0] bitfield of the AES_CR register. Do not modify the MODE[1:0] bitfield as set in the Init phase.

If the header phase was skipped, enable the AES peripheral by setting the EN bit of the AES_CR register.

If it is the last data block to encrypt and the plaintext size in the block is inferior to 128 bits, pad the remainder of the block with zeros.

Append the data block into AES in one of ways described in Section 34.4.4: AES procedure to perform a cipher operation on page 1512, and read the result.

Repeat the previous step till the second-last plaintext block is encrypted or till the last block of ciphertext is decrypted. For the last block of plaintext (encryption only), apply the two previous steps. For the last block, discard the data that is not part of the payload when the last block size is less than 16 bytes.

Note: The payload phase can be skipped if there is no payload data,that is,Len(P) = 0 or

Len (C) = Len (T)

Remove

{LSB}_{Len (T)} (C)

encrypted tag information when decrypting ciphertext

C

CCM final phase

In this last phase, the AES peripheral generates the GCM authentication tag and stores it in the AES_DOUTR register. The sequence to execute is:

Indicate the final phase, by setting to 11 the GCMPH[1:0] bitfield of the AES_CR

Wait until the end-of-computation flag CCF of the AES_SR register is set.

Read four times the AES_DOUTR register: the output corresponds to the CCM

Clear the CCF flag of the AES_SR register by setting the CCFC bit of the AES_CR register.

Disable the AES peripheral, by clearing the EN bit of the AES_CR register.

For authenticated decryption, compare the generated encrypted tag with the encrypted tag padded in the ciphertext.

Note:

In this final phase,swapping is applied to tag data read from AES_DOUTR register.

When transiting from the header phase to the final phase, the AES peripheral must not be disabled, otherwise the result is wrong.

Application must mask the authentication tag output with tag length to obtain a valid tag.

Suspend/resume operations in CCM mode

To suspend the processing of a message in header or payload phase, proceed as follows:

If DMA is used, stop the AES DMA transfers to the IN FIFO by clearing the DMAINEN bit of the AES_CR register. If DMA is not used, make sure that the current computation is completed, which is indicated by the CCF flag of the AES_SR register set to 1 .

In the payload phase, if DMA is not used, read four times the AES_DOUTR register to save the last-processed block. If DMA is used, wait until the CCF flag is set in the AES_SR register then stop the DMA transfers from the OUT FIFO by clearing the DMAOUTEN bit of the AES_CR register.

Clear the CCF flag of the AES_SR register, by setting to 1 the CCFC bit of the AES_CR register.

Save the AES_SUSPxR registers (where $x$ is from 0 to 7 ) in the memory.

Save the AES_IVRx registers as, during the data processing, they changed from their initial values.

Disable the AES peripheral, by clearing the EN bit of the AES_CR register.

Save the current AES configuration in the memory, excluding the initialization vector registers AES_IVRx. Key registers do not need to be saved as the original key value is known by the application.

If DMA is used, save the DMA controller status (pointers for IN data transfers, number of remaining bytes, and so on). In the payload phase, pointers for OUT data transfers must also be saved.

To resume the processing of a message, proceed as follows:

If DMA is used, configure the DMA controller in order to complete the rest of the FIFO IN transfers. In the payload phase, the rest of the FIFO OUT transfers must also be configured in the DMA controller.

Disable the AES peripheral by clearing the EN bit of the AES_CR register.

Write the suspend register values, previously saved in the memory, back into their corresponding AES_SUSPxR registers (where x is from 0 to 7).

Write the initialization vector register values, previously saved in the memory, back into their corresponding AES_IVRx registers.

Restore the initial setting values in the AES_CR and AES_KEYRx registers.

Enable the AES peripheral by setting the EN bit of the AES_CR register.

If DMA is used, enable AES DMA requests by setting to 1 the DMAINEN bit (and DMAOUTEN bit if in payload phase) of the AES_CR register.

34.4.13 AES data registers and data swapping

Data input and output

A 128-bit data block is entered into the AES peripheral with four successive 32-bit word writes into the AES_DINR register (bitfield DIN[31:0]), the most significant word (bits [127:96]) first, the least significant word (bits [31:0]) last.

A 128-bit data block is retrieved from the AES peripheral with four successive 32-bit word reads from the AES_DOUTR register (bitfield DOUT[31:0]), the most significant word (bits [127:96]) first, the least significant word (bits [31:0]) last.

The 32-bit data word for AES_DINR register or from AES_DOUTR register is organized in big endian order, that is:

the most significant byte of a word to write into AES_DINR must be put on the lowest address out of the four adjacent memory locations keeping the word to write, or

the most significant byte of a word read from AES_DOUTR goes to the lowest address out of the four adjacent memory locations receiving the word

For using DMA for input data block write into AES, the four words of the input block must be stored in the memory consecutively and in big-endian order, that is, the most significant word on the lowest address. See Section 34.4.16: AES DMA interface.

Data swapping

The AES peripheral can be configured to perform a bit-, a byte-, a half-word-, or no swapping on the input data word in the AES_DINR register, before loading it to the AES processing core, and on the data output from the AES processing core, before sending it to the AES_DOUTR register. The choice depends on the type of data. For example, a byte swapping is used for an ASCII text stream.

The data swap type is selected through the DATATYPE[1:0] bitfield of the AES_CR register. The selection applies both to the input and the output of the AES core.

For different data swap types, Figure 526 shows the construction of AES processing core input buffer data P127 to P0, from the input data entered through the AES_DINR register, or the construction of the output data available through the AES_DOUTR register, from the AES processing core output buffer data P127 to P0.

Figure 526. 128-bit block construction with respect to data swap

RM0440 Rev 8

Note: The data in AES key registers (AES_KEYRx) and initialization registers (AES_IVRx) are not sensitive to the swap mode selection.

Data padding

Figure 526 also gives an example of memory data block padding with zeros such that the zeroed bits after the data swap form a contiguous zone at the MSB end of the AES core input buffer. The example shows the padding of an input data block containing:

48 message bits,with DATATYPE[1:0] = 01

56 message bits,with DATATYPE[1:0] $= 10$

34 message bits,with DATATYPE[1:0] $= 11$

34.4.14 AES key registers

The AES_KEYRx registers store the encryption or decryption key bitfield KEY[127:0] or

KEY [255 : 0]

. The data to write to or to read from each register is organized in the memory in little-endian order, that is, with most significant byte on the highest address.

The key is spread over eight registers as shown in Table 325.

Table 325. Key endianness in AES_KEYRx registers (128- or 256-bit key length)

AES_KEYR7 [31:0]	AES_KEYR6 [31:0]	AES_KEYR5 [31:0]	AES_KEYR4 [31:0]	AES_KEYR3 [31:0]	AES_KEYR2 [31:0]	AES_KEYR1 [31:0]	AES_KEYR0 [31:0]
，	-	，	-	KEY[127:96]	KEY[95:64]	KEY[63:32]	KEY[31:0]
KEY[255:224]	KEY[223:192]	KEY[191:160]	KEY[159:128]	KEY[127:96]	KEY[95:64]	KEY[63:32]	KEY[31:0]

The key for encryption or decryption may be written into these registers when the AES peripheral is disabled, by clearing the EN bit of the AES_CR register.

The key registers are not affected by the data swapping controlled by DATATYPE[1:0] bitfield of the AES_CR register.

34.4.15 AES initialization vector registers

The four AES_IVRx registers keep the initialization vector input bitfield IVI[127:0]. The data to write to or to read from each register is organized in the memory in little-endian order, that is, with most significant byte on the highest address. The registers are also ordered from lowest address (AES_IVR0) to highest address (AES_IVR3).

The signification of data in the bitfield depends on the chaining mode selected. When used, the bitfield is updated upon each computation cycle of the AES core.

Write operations to the AES_IVRx registers when the AES peripheral is enabled have no effect to the register contents. For modifying the contents of the AES_IVRx registers, the EN bit of the AES_CR register must first be cleared.

Reading the AES_IVRx registers returns the latest counter value (useful for managing suspend mode).

The AES_IVRx registers are not affected by the data swapping feature controlled by the DATATYPE[1:0] bitfield of the AES_CR register.

34.4.16 AES DMA interface

The AES peripheral provides an interface to connect to the DMA (direct memory access)

controller. The DMA operation is controlled through the AES_CR register.

Data input using DMA

Setting the DMAINEN bit of the AES_CR register enables DMA writing into AES. The AES peripheral then initiates a DMA request during the input phase each time it requires to write a 128-bit block (quadruple word) to the AES_DINR register, as shown in Figure 527.

Note: According to the algorithm and the mode selected, special padding / ciphertext stealing might be required. For example, in case of AES GCM encryption or AES CCM decryption, a DMA transfer must not include the last block. For details, refer to Section 34.4.4: AES procedure to perform a cipher operation.

Figure 527. DMA transfer of a 128-bit data block during input phase

Data output using DMA

Setting the DMAOUTEN bit of the AES_CR register enables DMA reading from AES. The AES peripheral then initiates a DMA request during the Output phase each time it requires to read a 128-bit block (quadruple word) to the AES_DINR register, as shown in Figure 528.

Note: According to the message size, extra bytes might need to be discarded by application in the last block.

Figure 528. DMA transfer of a 128-bit data block during output phase

DMA operation in different operating modes

DMA operations are usable when Mode 1 (encryption) or Mode 3 (decryption) are selected via the MODE[1:0] bitfield of the register AES_CR. As in Mode 2 (key derivation) the AES_KEYRx registers must be written by software, enabling the DMA transfer through the DMAINEN and DMAOUTEN bits of the AES_CR register have no effect in that mode.

DMA single requests are generated by AES until it is disabled. So, after the data output phase at the end of processing of a 128-bit data block, AES switches automatically to a new data input phase for the next data block, if any.

When the data transferring between AES and memory is managed by DMA, the CCF flag has no use because the reading of the AES_DOUTR register is managed by DMA automatically at the end of the computation phase. The CCF flag must only be cleared when transiting back to data transferring managed by software. See Section 34.4.4: AES procedure to perform a cipher operation, subsection Data append, for details.

34.4.17 AES error management

AES configuration can be changed at any moment by clearing the EN bit of the AES_CR register.

Read error flag (RDERR)

Unexpected read attempt of the AES_DOUTR register sets the RDERR flag of the AES_SR register, and returns zero.

RDERR is triggered during the computation phase or during the input phase.

Note: AES is not disabled upon a RDERR error detection and continues processing.

An interrupt is generated if the ERRIE bit of the AES_CR register is set. For more details, refer to Section 34.5: AES interrupts.

The RDERR flag is cleared by setting the ERRIE bit of the AES_CR register.

Write error flag (WDERR)

Unexpected write attempt of the AES_DINR register sets the WRERR flag of the AES_SR register, and has no effect on the AES_DINR register. The WRERR is triggered during the computation phase or during the output phase.

Note: AES is not disabled after a WRERR error detection and continues processing.

An interrupt is generated if the ERRIE bit of the AES_CR register is set. For more details, refer to Section 34.5: AES interrupts.

The WRERR flag is cleared by setting the ERRC bit of the AES_CR register.

34.5 AES interrupts

Individual maskable interrupt sources generated by the AES peripheral signal the following events:

computation completed

read error

write error

These sources are combined into a common interrupt signal from the AES peripheral that connects to the

{Arm}^{®} {Cortex}^{®}

interrupt controller. Each can individually be

enabled/disabled, by setting/clearing the corresponding enable bit of the AES_CR register, and cleared by setting the corresponding bit of the AES_CR register.

The status of each can be read from the AES_SR register.

Table 326 gives a summary of the interrupt sources, their event flags and enable bits.

Table 326. AES interrupt requests

Interrupt acronym	AES interrupt event	Event flag	Enable bit	Interrupt clear method
AES	computation completed flag	CCF	CCFIE	set CCFC(1)
	read error flag	RDERR	ERRIE	set ${ERRC}^{(1)}$
	write error flag	WRERR	ERRIE	set ${ERRC}^{(1)}$

Bit of the AES_CR register.

34.6 AES processing latency

The tables below summarize the latency to process a 128-bit block for each mode of operation.

Table 327. Processing latency for ECB, CBC and CTR

Key size	Mode of operation	Algorithm	Clock cycles
128-bit	Mode 1: Encryption	ECB, CBC, CTR	51
	Mode 2: Key derivation	-	59
	Mode 3: Decryption	ECB, CBC, CTR	51
	Mode 4: Key derivation then decryption	ECB, CBC	106

Table 327. Processing latency for ECB, CBC and CTR (continued)

Key size	Mode of operation	Algorithm	Clock cycles
256-bit	Mode 1: Encryption	ECB, CBC, CTR	75
	Mode 2: Key derivation	-	82
	Mode 3: Decryption	ECB, CBC, CTR	75
	Mode 4: Key derivation then decryption	ECB, CBC	145

Table 328. Processing latency for GCM and CCM (in clock cycles)

Key size	Mode of operation	Algorithm	Init Phase	Header phase(1)	Payload phase(1)	Tag phase(1)
128-bit	Mode 1: Encryption/ Mode 3: Decryption	GCM	64	35	51	59
128-bit	Mode 1: Encryption/ Mode 3: Decryption	CCM	63	55	114	58
256-bit	Mode 1: Encryption/ Mode 3: Decryption	GCM	88	35	75	75
256-bit	Mode 1: Encryption/ Mode 3: Decryption	CCM	87	79	162	82

Data insertion can include wait states forced by AES on the AHB bus (maximum 3 cycles, typical 1 cycle).

34.7 AES registers

34.7.1 AES control register (AES_CR)

Address offset: 0x00

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	NPBLB[3:0]				Res.	3ZISA3Y	Res.	[8] gowho
								rw	rw	rw	rw		rw		rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	GCMPH[1:0]		NELNOVING	N3NIVWO	ERRIE	CCFIE	ERRC	CCFC	CHMOD[1:0]		MODE[1:0]		DATATYPE[1:0]		EN
	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:20 NPBLB[3:0]: Number of padding bytes in last block

The bitfield sets the number of padding bytes in last block of payload:

0000: All bytes are valid (no padding)

0001: Padding for one least-significant byte of last block

\dots

1111: Padding for 15 least-significant bytes of last block

Bit 19 Reserved, must be kept at reset value.

Bit 18 KEYSIZE: Key size selection

This bitfield defines the length of the key used in the AES cryptographic core, in bits:

0: 128

1: 256

Attempts to write the bit are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access.

Bit 17 Reserved, must be kept at reset value.

Bit 15 Reserved, must be kept at reset value.

Bits 14:13 GCMPH[1:0]: GCM or CCM phase selection

This bitfield selects the phase of GCM, GMAC or CCM algorithm:

00: Init phase

01: Header phase

10: Payload phase

11: Final phase

The bitfield has no effect if other than GCM, GMAC or CCM algorithms are selected (through the

ALGOMODE bitfield).

Bit 12 DMAOUTEN: DMA output enable

This bit enables/disables data transferring with DMA, in the output phase:

0: Disable

1: Enable

When the bit is set, DMA requests are automatically generated by AES during the output data

phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0]

bitfield. It is not effective for Mode 2 (key derivation).

Use of DMA with Mode 4 (single decryption) is not recommended.

Bit 11 DMAINEN: DMA input enable

This bit enables/disables data transferring with DMA, in the input phase:

0: Disable

1: Enable

When the bit is set, DMA requests are automatically generated by AES during the input data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation).

Use of DMA with Mode 4 (single decryption) is not recommended.

Bit 10 ERRIE: Error interrupt enable

This bit enables or disables (masks) the AES interrupt generation when RDERR and/or WRERR is

set:

0: Disable (mask)

1: Enable

Bit 9 CCFIE: CCF interrupt enable

This bit enables or disables (masks) the AES interrupt generation when CCF (computation complete

flag) is set:

0: Disable (mask)

1: Enable

Bit 8 ERRC: Error flag clear

Upon written to 1, this bit clears the RDERR and WRERR error flags in the AES_SR register:

0 : No effect

1: Clear RDERR and WRERR flags

Reading the flag always returns zero.

Bit 7 CCFC: Computation complete flag clear

Upon written to 1, this bit clears the computation complete flag (CCF) in the AES_SR register: 0 : No effect

1: Clear CCF

Reading the flag always returns zero.

Bits 16, 6:5 CHMOD[2:0]: Chaining mode selection

This bitfield selects the AES chaining mode:

000: Electronic codebook (ECB)

001: Cipher-block chaining (CBC)

010: Counter mode (CTR)

011: Galois counter mode (GCM) and Galois message authentication code (GMAC)

100: Counter with CBC-MAC (CCM)

others: Reserved

Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the

write access and it is not cleared by that write access.

Bits 4:3 MODE[1:0]: AES operating mode

This bitfield selects the AES operating mode:

00: Mode 1: encryption

01: Mode 2: key derivation (or key preparation for ECB/CBC decryption)

10: Mode 3: decryption

11: Mode 4: key derivation then single decryption

Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access. Any attempt to selecting Mode 4 while either ECB or CBC chaining mode is not selected, defaults to effective selection of Mode 3. It is not possible to select a Mode 3 following a Mode 4.

Bits 2:1 DATATYPE[1:0]: Data type selection

This bitfield defines the format of data written in the AES_DINR register or read from the

AES_DOUTR register, through selecting the mode of data swapping:

00: None

01: Half-word (16-bit)

10: Byte (8-bit)

11: Bit

For more details, refer to Section 34.4.13: AES data registers and data swapping.

Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the

write access and it is not cleared by that write access.

Bit 0 EN: AES enable

This bit enables/disables the AES peripheral:

0: Disable

1: Enable

At any moment, clearing then setting the bit re-initializes the AES peripheral.

This bit is automatically cleared by hardware upon the completion of the key preparation (Mode 2) and upon the completion of GCM/GMAC/CCM initial phase.

34.7.2 AES status register (AES_SR)

Address offset: 0x04

Reset value: 0x00000000

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 BUSY: Busy

This flag indicates whether AES is idle or busy during GCM payload encryption phase: 0: Idle

1: Busy

When the flag indicates "idle", the current GCM encryption processing may be suspended to process a higher-priority message. In other chaining modes, or in GCM phases other than payload encryption, the flag must be ignored for the suspend process.

Bit 2 WRERR: Write error

This flag indicates the detection of an unexpected write operation to the AES_DINR register (during computation or data output phase):

0 : Not detected

1: Detected

The flag is set by hardware. It is cleared by software upon setting the ERRC bit of the AES_CR register.

Upon the flag setting, an interrupt is generated if enabled through the ERRIE bit of the AES_CR register.

The flag setting has no impact on the AES operation. Unexpected write is ignored.

Bit 1 RDERR: Read error flag

This flag indicates the detection of an unexpected read operation from the AES_DOUTR register (during computation or data input phase):

0 : Not detected

1: Detected

The flag is set by hardware. It is cleared by software upon setting the ERRC bit of the AES_CR register.

Upon the flag setting, an interrupt is generated if enabled through the ERRIE bit of the AES_CR register.

The flag setting has no impact on the AES operation. Unexpected read returns zero.

Bit 0 CCF: Computation completed flag

This flag indicates whether the computation is completed:

0 : Not completed

1: Completed

The flag is set by hardware upon the completion of the computation. It is cleared by software, upon setting the CCFC bit of the AES_CR register.

Upon the flag setting, an interrupt is generated if enabled through the CCFIE bit of the AES_CR register.

The flag is significant only when the DMAOUTEN bit is 0 . It may stay high when DMA_EN is 1 .

34.7.3 AES data input register (AES_DINR)

Address offset: 0x08

Reset value: 0x00000000

Only 32-bit access type is supported.

DIN[15:0]

Bits 31:0 DIN[31:0]: Input data word

A four-fold sequential write to this bitfield during the input phase results in writing a complete 128-bit block of input data to the AES peripheral. From the first to the fourth write, the corresponding data weights are [127:96], [95:64], [63:32], and [31:0]. Upon each write, the data from the 32-bit input buffer are handled by the data swap block according to the DATATYPE[1:0] bitfield, then written into the AES core 128-bit input buffer.

The data signification of the input data block depends on the AES operating mode:

Mode 1 (encryption): plaintext

Mode 2 (key derivation): the bitfield is not used (AES_KEYRx registers used for input)

Mode 3 (decryption) and Mode 4 (key derivation then single decryption): ciphertext

The data swap operation is described in Section 34.4.13: AES data registers and data swapping on page 1536.

34.7.4 AES data output register (AES_DOUTR)

Address offset: 0x0C

Reset value: 0x00000000

Only 32-bit read access type is supported.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DOUT[31:16]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DOUT[15:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:0 DOUT[31:0]: Output data word

This read-only bitfield fetches a 32-bit output buffer. A four-fold sequential read of this bitfield, upon the computation completion (CCF set), virtually reads a complete 128-bit block of output data from the AES peripheral. Before reaching the output buffer, the data produced by the AES core are handled by the data swap block according to the DATATYPE[1:0] bitfield.

Data weights from the first to the fourth read operation are: [127:96], [95:64], [63:32], and [31:0].

The data signification of the output data block depends on the AES operating mode: - Mode 1 (encryption): ciphertext

Mode 2 (key derivation): the bitfield is not used (AES_KEYRx registers used for output)

Mode 3 (decryption) and Mode 4 (key derivation then single decryption): plaintext

The data swap operation is described in Section 34.4.13: AES data registers and data swapping on page 1536.

34.7.5 AES key register 0 (AES_KEYR0)

Address offset: 0x10

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
KEY[31:16]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:0 KEY[31:0]: Cryptographic key, bits [31:0]

This bitfield contains the bits [31:0] of the AES encryption or decryption key, depending on the operating mode:

In Mode 1 (encryption), Mode 2 (key derivation) and Mode 4 (key derivation then single decryption): the value to write into the bitfield is the encryption key.

In Mode 3 (decryption): the value to write into the bitfield is the encryption key to be derived before being used for decryption. After writing the encryption key into the bitfield, its reading before

enabling AES returns the same value. Its reading after enabling AES and after the CCF flag is set returns the decryption key derived from the encryption key.

Note: In mode 4 (key derivation then single decryption) the bitfield always contains the encryption key.

The AES_KEYRx registers may be written only when KEYSIZE value is correct and when the AES peripheral is disabled (EN bit of the AES_CR register cleared). Note that, if, the key is directly loaded to AES_KEYRx registers (hence writes to key register is ignored and KEIF is set).

Refer to Section 34.4.14: AES key registers on page 1538 for more details.

34.7.6 AES key register 1 (AES_KEYR1)

Address offset: 0x14

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
KEY[63:48]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY[47:32]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:0 KEY[63:32]: Cryptographic key, bits [63:32]

Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

34.7.7 AES key register 2 (AES_KEYR2)

Address offset: 0x18

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
KEY[95:80]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY[79:64]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:0 KEY[95:64]: Cryptographic key, bits [95:64]

Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

34.7.8 AES key register 3 (AES_KEYR3)

Address offset: 0x1C

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
KEY[127:112]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY[111:96]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:0 KEY[127:96]: Cryptographic key, bits [127:96]

Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

34.7.9 AES initialization vector register 0 (AES_IVR0)

Address offset: 0x20 Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IVI[31:16]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IVI[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:0 IVI[31:0]: Initialization vector input, bits [31:0]

Refer to Section 34.4.15: AES initialization vector registers on page 1538 for description of the IVI[127:0] bitfield.

The initialization vector is only used in chaining modes other than ECB.

The AES_IVRx registers may be written only when the AES peripheral is disabled

34.7.10 AES initialization vector register 1 (AES_IVR1)

Address offset: 0x24

Reset value: 0x00000000

TVT[47,02]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:0 IVI[63:32]: Initialization vector input, bits [63:32]

Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield.

34.7.11 AES initialization vector register 2 (AES_IVR2)

Address offset: 0x28

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IVI[95:80]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IVI[79:64]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:0 IVI[95:64]: Initialization vector input, bits [95:64]

Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield. 34.7.12 AES initialization vector register 3 (AES_IVR3) Address offset: 0x2C Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IVI[127:112]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IVI[111:96]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:0 IVI[127:96]: Initialization vector input, bits [127:96]

Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield.

34.7.13 AES key register 4 (AES_KEYR4)

Address offset: 0x30

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
KEY[159:144]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY[143:128]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:0 KEY[159:128]: Cryptographic key, bits [159:128]

Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

34.7.14 AES key register 5 (AES_KEYR5)

Address offset: 0x34

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
KEY[191:176]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY[175:160]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:0 KEY[191:160]: Cryptographic key, bits [191:160]

Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

34.7.15 AES key register 6 (AES_KEYR6)

Address offset: 0x38

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
KEY[223:208]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY[207:192]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:0 KEY[223:192]: Cryptographic key, bits [223:192]

Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

34.7.16 AES key register 7 (AES_KEYR7)

Address offset: 0x3C

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
KEY[255:240]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY[239:224]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:0 KEY[255:224]: Cryptographic key, bits [255:224]

Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

Note: The key registers from 4 to 7 are used only when the key length of 256 bits is selected. They have no effect when the key length of 128 bits is selected (only key registers 0 to 3 are used in that case).

34.7.17 AES suspend registers (AES_SUSPxR)

Address offset:

0 \times 040 + 0 \times 4 * x, (x = 0 to 7)

Reset value: 0x00000000

These registers contain the complete internal register states of the AES processor when the AES processing of the current task is suspended to process a higher-priority task.

Upon suspend,the software reads and saves the AES_SUSPxR register contents (where

x

is from 0 to 7) into memory, before using the AES processor for the higher-priority task. Upon completion, the software restores the saved contents back into the corresponding suspend registers, before resuming the original task.

Note: These registers are used only when GCM, GMAC, or CCM chaining mode is selected.

These registers can be read only when AES is enabled. Reading these registers while AES is disabled returns

0 x 00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SUSP[31:16]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SUSP[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:0 SUSP[31:0]: AES suspend

Upon suspend operation, this bitfield of the corresponding AES_SUSPxR register takes the value of one of internal AES registers.

34.7.18 AES register map

Table 329. AES register map and reset values

Offset	Register	31	30	23	2Q3	27	26	26	2423	22	21	20	1.	1.	17	1.6	16	14	13	12	11	10	9	8	7	6	5	4	3	2	1	O
0x000	AES_CR	1.5	中心	LIG	Let	S	LIG	SHIP	BUS	[0:8]879dN			STO	3ZISA3Y		[Z]GOWHO		[OIL]HdWOO		NELNOVWA	N3NIVWO	Europe	Output	Effect	Output	[O'1] GOWHO		$[0 : 1] \exists$ GOW		$[0 : 1] \exists d ⋏ 1 \forall 1 \forall 0$		1.00
0x000	Reset value								0	0	0	0		0		0		0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x004	AES_SR	3	STE	y	6	3	好好	3,399	3S	3	SHIP	1.5	a	SHOP	y	SHUD	SHI	3	3	3	3	3,399	y	3	3	3	金融	BUR	BSTS	JYJYM	YYJOY	8
0x004	Reset value																												0	0	0	0
0x008	AES_DINR	DIN[31:0]
0x008	Reset value	0	0	0	0	0	0	0	00	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x00C	AES_DOUTR	DOUT[31:0]
0x00C	Reset value	0	0	0	0	0	0	0	00	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x010	AES_KEYR0	KEY[31:0]
0x010	Reset value	0	0	0	0	0	0	0	00	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x014	AES_KEYR1	KEY[63:32]
0x014	Reset value	0	0	0	0	0	0	0	00	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x018	AES_KEYR2	KEY[95:64]
0x018	Reset value	0	0	0	0	0	0	0	00	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x01C	AES_KEYR3	KEY[127:96]
0x01C	Reset value	0	0	0	0	0	0	0	00	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x020	AES_IVR0	IVI[31:0]
0x020	Reset value	0	0	0	0	0	0	0	00	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x024	AES_IVR1	IVI[63:32]
0x024	Reset value	0	0	0	0	0	0	0	00	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x028	AES_IVR2	IVI[95:64]
0x028	Reset value	0	0	0	0	0	0	0	00	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Table 329. AES register map and reset values (continued)

Offset	Register	31	30	23	2Q3	27	26	26	2423	22	21	20	1.	1.	17	1.5	1.5	1.4	13	12	11	10	9	8	7	6	5	4	3	2	1	O
0x02C	AES_IVR3	IVI[127:96]
0x02C	Reset value	0	0	0	0	0	0	0	00	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x030	AES_KEYR4	KEY[159:128]
0x030	Reset value	0	0	0	0	0	0	0	00	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x034	AES_KEYR5	KEY[191:160]
0x034	Reset value	0	0	0	0	0	0	0	00	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x038	AES_KEYR6	KEY[223:192]
0x038	Reset value	0	0	0	0	0	0	0	00	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x03C	AES_KEYR7KEY[255:224]
0x03C	Reset value	0	0	0	0	0	0	0	00	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x040	AES_SUSPOR	SUSP[31:0]
0x040	Reset value	0	0	0	0	0	0	0	00	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x044	AES_SUSP1RSUSP[31:0]
0x044	Reset value	0	0	0	0	0	0	0	00	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x048	AES_SUSP2R	SUSP[31:0]
0x048	Reset value	0	0	0	0	0	0	0	00	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x04C	AES_SUSP3R	SUSP[31:0]
0x04C	Reset value	0	0	0	0	0	0	0	00	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x050	AES SUSP4R	SUSP[31:0]
0x050	Reset value	0	0	0	0	0	0	0	00	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x054	AES SUSP5R	SUSP[31:0]
0x054	Reset value	0	0	0	0	0	0	0	00	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x058	AES SUSP6R	SUSP[31:0]
0x058	Reset value	0	0	0	0	0	0	0	00	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x05C	AES SUSP7R	SUSP[31:0]
0x05C	Reset value	0	0	0	0	0	0	0	00	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x060- 0x3FF	Reserved	13	83	S	13	3	3	3	8a	8	S	:	3	:	3	:	3	S	23	3	3	3	8		13	8	a	福		3	3	13

Refer to Section 2.2 on page 81 for the register boundary addresses.

35 Real-time clock (RTC)

35.1 Introduction

The RTC provides an automatic wakeup to manage all low-power modes.

The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-of-day clock/calendar with programmable alarm interrupts.

As long as the supply voltage remains in the operating range, the RTC never stops,

regardless of the device status (Run mode, low-power mode or under reset).

The RTC is functional in

V_{BAT}

mode.

35.2 RTC main features

The RTC supports the following features (see Figure 529: RTC block diagram):

Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format.

Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.

Two programmable alarms.

On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock.

Reference clock detection: a more precise second source clock (50 or $60 Hz$ ) can be used to enhance the calendar precision.

Digital calibration circuit with $0.95 ppm$ resolution,to compensate for quartz crystal inaccuracy.

Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to $V_{BAT}$ mode.

17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period.

The RTC is supplied through a switch that takes power either from the

V_{D D}

supply when present or from the

V_{BAT}

pin.

The RTC clock sources can be:

A 32.768 kHz external crystal (LSE)

An external resonator or oscillator (LSE)

The internal low power RC oscillator (LSI,with typical frequency of $32 kHz$ )

The high-speed external clock (HSE), divided by a prescaler in the RCC.

The RTC is functional in

V_{BAT}

mode and in all low-power modes when it is clocked by the LSE. When clocked by the LSI,the RTC is not functional in

V_{BAT}

mode,but is functional in all low-power modes except Shutdown mode.

All RTC events (Alarm, WakeUp Timer, Timestamp) can generate an interrupt and wakeup the device from the low-power modes.

35.3.2 RTC pins and internal signals

Table 330. RTC input/output pins

Pin name	Signal type	Description
RTC_TS	Input	RTC timestamp input
RTC_REFIN	Input	RTC 50 or 60 Hz reference clock input
RTC_OUT1	Output	RTC output 1
RTC_OUT2	Output	RTC output 2

RTC_OUT1 and RTC_OUT2 which selects one of the following two outputs:

CALIB: 512 Hz or 1 Hz clock output (with an LSE frequency of $32.768 kHz$ ). This output is enabled by setting the COE bit in the RTC_CR register.

TAMPALRM: This output is the OR between TAMP and ALARM outputs.

ALARM is enabled by configuring the OSEL[1:0] bits in the RTC_CR register which select the alarm A, alarm B or wakeup outputs. TAMP is enabled by setting the TAMPOE bit in the RTC_CR register which selects the tamper event outputs.

Table 331. RTC internal input/output signals

Internal signal name	Signal type	Description
rtc_ker_ck	Input	RTC kernel clock, also named RTCCLK in this document
rtc_pclk	Input	RTC APB clock
rtc_its	Input	RTC internal timestamp event
rtc_tamp_evt	Input	Tamper event (internal or external) detected in TAMP peripheral
rtc_it	Output	RTC interrupts (refer to Section 35.5: RTC interrupts for details)
rtc_alra_trg	Output	RTC alarm A event detection trigger
rtc_alrb_trg	Output	RTC alarm B event detection trigger
rtc_wut_trg	Output	RTC wakeup timer event detection trigger
rtc_calovf	Output	RTC calendar overflow

The RTC kernel clock is usually the LSE at

32.768 kHz

although it is possible to select other clock sources in the RCC (refer to RCC for more details). Some functions are not available in some low-power modes or

V_{BAT}

when the selected clock is not LSE. Refer to Section 35.4: RTC low-power modes for more details.

Table 332. RTC interconnection

Signal name	Source/destination
rtc_its	From power controller (PWR): main power loss/switch to $V_{BAT}$ detection output
rtc_tamp_evt	From TAMP peripheral: tamp_evt
rtc_calovf	To TAMP peripheral: tamp_itamp5

The triggers outputs can be used as triggers for other peripherals.

35.3.3 GPIOs controlled by the RTC and TAMP

The GPIOs included in the Battery Backup Domain

(V_{BAT})

are directly controlled by the peripherals providing functions on these I/Os, whatever the GPIO configuration.

Both RTC and TAMP peripherals provide functions on these I/Os (refer to Section 36: Tamper and backup registers (TAMP)).

RTC_OUT1, RTC_TS and TAMP_IN1 are mapped on the same pin (PC13). The RTC and TAMP functions mapped on PC13 are available in all low-power modes and in

V_{BAT}

mode.

The output mechanism follows the priority order shown in Table 333.

Table 333. PC13 configuration(1)

PC13 Pin function	[0:1]73SO(ajqeua Ind,Ino WYVIV)	30dWV1(ajqeua jndyno 23dWVL)	Q4(ajqeua jndyno girvo)	NEZINO	$\exists d {\bar{λ}}^{⊥} W \bar{d} T \bar{v} d W \bar{l}$	nd waivdWyl	ELAWVL(ajqeua jndu! LNITdWVL)	TSE(a\|qua 1ndu! SLTOLY)
TAMPALRM output Push-Pull	01 or 10 or 11	0	Don't care	Don't care	0	0	Don't care	Don't care
	00	1
	01 or 10 or 11	1

Table 333. PC13 configuration

^{(1)}

(continued)

Table 5.5.1 The configuration(commutative)
PC13 Pin function		[O'1]73SO(a)qua ¿nd¡no WăVṖv)	30dWV1(ajqeua jndyno djdwyl)	COUTE(a queue and no gives)	NEZINO	$\exists d ⋏ ⊥^{⊤} W ⫫ \neg \forall d W ⫫ \forall ⊥$	nd warvdwyl	3ldWV1(a\|queua indu! INITd	TS(a\|qua indu! SLTOLY)
TAMPALRM output Open-Drain(2)	No pull	01 or 10 or 11	0	Don't care	Don't care	1	0	Don't care	Don't care
		00	1
		01 or 10 or 11	1
	Internal pull-up	01 or 10 or 11	0	Don't care	Don't care	1	1	Don't care	Don't care
		00	1
		01 or 10 or 11	1
CALIB output PP		00	0	1	0	Don't care	Don't care	Don't care	Don't care
TAMP_IN1 input floating		00	0	0	Don't care	Don't care	Don't care	1	0
		00	0	1	1
		Don't care	Don't care	0	1
RTC_TS and TAMP_IN1 input floating		00	0	0	Don't care	Don't care	Don't care	1	1
		00	0	1	1
		Don't care	Don't care	0	1
RTC_TS input floating		00	0	0	Don't care	Don't care	Don't care	0	1
		00	0	1	1
		Don't care	Don't care	0	1

Table 333. PC13 configuration

^{(1)}

(continued)

PC13 Pin function	[0:1]73SO(a)quark and,no WYVW)	30dWV1(ajqeua ¿nd,no ¿3dWv1)	COU(a qual indino girl(v)	NEZINO	$\exists d ⋏ ⊥$ Wäδ8 $\neg \forall d$ Ｗ $\forall ⊥$	nd WarvdWV1	$\exists$ LdWV1(a\|qua ¿ndu! LNITdWVL)	TSE(a\|qua \}ndu! SL_018)
Wakeup pin or Standard GPIO	00	0	0	Don't care	Don't care	Don't care	0	0
	00	0	1	1
	Don't care	Don't care	0	1

OD: open drain; PP: push-pull.

In this configuration the GPIO must be configured in input.

In addition, it is possible to output RTC_OUT2 on PB2 pin thanks to OUT2EN bit. This output is not available in

V_{BAT}

mode. The different functions are mapped on RTC_OUT1 or on RTC_OUT2 depending on OSEL, COE and OUT2EN configuration, as show in table Table 334.

For PB2, the GPIO should be configured as an alternate function.

Table 334. RTC_OUT mapping

OSEL[1:0] bits ALARM output enable)	COE bit (CALIB output enable)	OUT2EN bit	RTC_OUT1 on PC13	RTC_OUT2 on PB2
00	0	0	-	-
00	1		CALIB	-
01 or 10 or 11	Don't care		TAMPALRM	-
00	0	1	-	-
00	1		-	CALIB
01 or 10 or 11	0		-	TAMPALRM
01 or 10 or 11	1		TAMPALRM	CALIB

35.3.4 Clock and prescalers

The RTC clocks must respect this ratio: frequency(PCLK)

\geq 2 \times

frequency(RTCCLK).

The RTC clock source (RTCCLK) is selected through the clock controller among the LSE clock, the LSI oscillator clock, and the HSE clock. For more information on the RTC clock source configuration, refer to Section 7: Reset and clock control (RCC).

A programmable prescaler stage generates a

1 Hz

clock which is used to update the calendar. To minimize power consumption, the prescaler is split into 2 programmable prescalers (see Figure 529: RTC block diagram):

A 7-bit asynchronous prescaler configured through the PREDIV_A bits of the RTC_PRER register.

A 15-bit synchronous prescaler configured through the PREDIV_S bits of the RTC_PRER register.

Note: When both prescalers are used, it is recommended to configure the asynchronous prescaler to a high value to minimize consumption.

The asynchronous prescaler division factor is set to 128 , and the synchronous division factor to 256,to obtain an internal clock frequency of

1 Hz

(ck_spre) with an LSE frequency of 32.768 kHz.

The minimum division factor is 1 and the maximum division factor is

2^{22}

This corresponds to a maximum input frequency of around 4 MHz.

f_{ck_apre}

is given by the following formula:

f_{CK_APRE} = \frac{f_{RTCCLK}}{PREDIV_A + 1}

The ck_apre clock is used to clock the binary RTC_SSR subseconds downcounter. When it reaches 0 , RTC_SSR is reloaded with the content of PREDIV_S.

f_{ck_spre}

is given by the following formula:

f_{CK_SPRE} = \frac{f_{RTCCLK}}{(PREDIV_S + 1) \times (PREDIV_A + 1)}

The ck_spre clock can be used either to update the calendar or as timebase for the 16-bit wakeup auto-reload timer. To obtain short timeout periods, the 16-bit wakeup auto-reload timer can also run with the RTCCLK divided by the programmable 4-bit asynchronous prescaler (see Section 35.3.7: Periodic auto-wakeup for details).

35.3.5 Real-time clock and calendar

The RTC calendar time and date registers are accessed through shadow registers which are synchronized with PCLK (APB clock). They can also be accessed directly in order to avoid waiting for the synchronization duration.

RTC_SSR for the subseconds

RTC_TR for the time

RTC_DR for the date

Every RTCCLK periods, the current calendar value is copied into the shadow registers, and the RSF bit of RTC_ICSR register is set (see Section 35.6.10: RTC shift control register (RTC_SHIFTR)). The copy is not performed in Stop and Standby mode. When exiting these modes, the shadow registers are updated after up to 4 RTCCLK periods.

When the application reads the calendar registers, it accesses the content of the shadow registers. It is possible to make a direct access to the calendar registers by setting the

BYPSHAD control bit in the RTC_CR register. By default, this bit is cleared, and the user accesses the shadow registers.

When reading the RTC_SSR, RTC_TR or RTC_DR registers in BYPSHAD = 0 mode, the frequency of the APB clock

(f_{A P B})

must be at least 7 times the frequency of the RTC clock (f Rtcclk).

The shadow registers are reset by system reset.

35.3.6 Programmable alarms

The RTC unit provides programmable alarm: alarm A and alarm B. The description below is given for alarm A, but can be translated in the same way for alarm B.

The programmable alarm function is enabled through the ALRAE bit in the RTC_CR register.

The ALRAF is set to 1 if the calendar subseconds, seconds, minutes, hours, date or day match the values programmed in the alarm registers RTC_ALRMASSR and

RTC_ALRMAR. Each calendar field can be independently selected through the MSKx bits of the RTC_ALRMAR register, and through the MASKSSx bits of the RTC_ALRMASSR register.

The alarm interrupt is enabled through the ALRAIE bit in the RTC_CR register.

Caution: If the seconds field is selected (MSK1 bit reset in RTC_ALRMAR), the synchronous prescaler division factor set in the RTC_PRER register must be at least 3 to ensure correct behavior.

Alarm A and alarm B (if enabled by bits OSEL[1:0] in RTC_CR register) can be routed to the TAMPALRM output. TAMPALRM output polarity can be configured through bit POL the RTC_CR register.

35.3.7 Periodic auto-wakeup

The periodic wakeup flag is generated by a 16-bit programmable auto-reload down-counter. The wakeup timer range can be extended to 17 bits.

The wakeup function is enabled through the WUTE bit in the RTC_CR register.

The wakeup timer clock input ck_wut can be:

RTC clock (RTCCLK) divided by 2, 4, 8, or 16.

When RTCCLK is LSE (32.768 kHz), this allows to configure the wakeup interrupt period from

122 μ s

32 s

,with a resolution down to

61 μ s

ck_spre (usually $1 Hz$ internal clock)

When ck_spre frequency is

1 Hz

,this allows to achieve a wakeup time from

1 s

to around 36 hours with one-second resolution. This large programmable time range is divided in 2 parts:

from 1 s to 18 hours when WUCKSEL [2:1] = 10

and from around $18 h$ to $36 h$ when WUCKSEL[2:1] $= 11$ . In this last case $2^{16}$ is added to the 16-bit counter current value. When the initialization sequence is complete (see Programming the wakeup timer on page 1563), the timer starts counting down. When the wakeup function is enabled, the down-counting remains active in low-power modes. In addition, when it reaches 0 , the WUTF flag is set in

the RTC_SR register, and the wakeup counter is automatically reloaded with its reload value (RTC_WUTR register value).

The WUTF flag must then be cleared by software.

When the periodic wakeup interrupt is enabled by setting the WUTIE bit in the RTC_CR register, it can exit the device from low-power modes.

The periodic wakeup flag can be routed to the TAMPALRM output provided it has been enabled through bits OSEL[1:0] of RTC_CR register. TAMPALRM output polarity can be configured through the POL bit in the RTC_CR register.

System reset, as well as low-power modes (Sleep, Stop and Standby) have no influence on the wakeup timer.

35.3.8 RTC initialization and configuration

RTC register access

The RTC registers are 32-bit registers. The APB interface introduces two wait states in RTC register accesses except on read accesses to calendar shadow registers when BYPSHAD

= 0

RTC register write protection

After system reset, the RTC registers are protected against parasitic write access by the DBP bit in the power control peripheral (refer to the PWR power control section). DBP bit must be set in order to enable RTC registers write access.

After Backup domain reset, some of the RTC registers are write-protected.

Writing to the protected RTC registers is enabled by writing a key into the Write Protection register, RTC_WPR.

The following steps are required to unlock the write protection on the protected RTC registers.

Write 0xCA into the RTC_WPR register.

Write 0x53 into the RTC_WPR register.

Writing a wrong key reactivates the write protection.

The protection mechanism is not affected by system reset.

Calendar initialization and configuration

To program the initial time and date calendar values, including the time format and the prescaler configuration, the following sequence is required:

	1. Set INIT bit to 1 in the RTC_ICSR register to enter initialization mode. In this mode, the calendar counter is stopped and its value can be updated.
	2. Poll INITF bit of in the RTC_ICSR register. The initialization phase mode is entered when INITF is set to 1. It takes around 2 RTCCLK clock cycles (due to clock synchronization).
	3. To generate a 1 Hz clock for the calendar counter, program both the prescaler factor in RTC_PRER register.
	4. Load the initial time and date values in the shadow registers (RTC_TR and RTC_DR) and configure the time format (12 or 24 hours) through the FMT bit in the RTC_CR register.
	5. Exit the initialization mode by clearing the INIT bit. The actual calendar counter value is then automatically loaded and the counting restarts after 4 RTCCLK clock cycles.
	When the initialization sequence is complete, the calendar starts counting.
Note:	After a system reset, the application can read the INITS flag in the RTC_ICSR register to check if the calendar has been initialized or not. If this flag equals 0, the calendar has no been initialized since the year field is set at its Backup domain reset default value (0x00).
	To read the calendar after initialization, the software must first check that the RSF flag is se in the RTC_ICSR register.
	Daylight saving time
	The daylight saving time management is performed through bits SUB1H, ADD1H, and BKP of the RTC_CR register.
	Using SUB1H or ADD1H, the software can subtract or add one hour to the calendar in one single operation without going through the initialization procedure
	In addition, the software can use the BKP bit to memorize this operation
	Programming the alarm
	A similar procedure must be followed to program or update the programmable alarms. Th procedure below is given for alarm A but can be translated in the same way for alarm B.
	1. Clear ALRAE in RTC_CR to disable alarm A.
	2. Program the alarm A registers (RTC_ALRMASSR/RTC_ALRMAR).
	3. Set ALRAE in the RTC_CR register to enable alarm A again.
Note:	Each change of the RTC_CR register is taken into account after around 2 RTCCLK clock cycles due to clock synchronization.
	Programming the wakeup timer
	The following sequence is required to configure or change the wakeup timer auto-reload value (WUT[15:0] in RTC_WUTR):
	1. Clear WUTE in RTC_CR to disable the wakeup timer
	Poll WUTWF until it is set in RTC_ICSR to make sure the access to wakeup auto- reload counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in calendar initialization mode. It takes around 2 RTCCLK clock cycles (due to clock synchronization).
	3. Program the wakeup auto-reload value WUT[15:0], and the wakeup clock selection (WUCKSEL[2:0] bits in RTC_CR). Set WUTE in RTC_CR to enable the timer again

The wakeup timer restarts down-counting.The WUTWF bit is cleared up to 2 RTCCLK clocks cycles after WUTE is cleared, due to clock synchronization.

35.3.9 Reading the calendar

When BYPSHAD control bit is cleared in the RTC_CR register

To read the RTC calendar registers (RTC_SSR, RTC_TR and RTC_DR) properly, the APB1 clock frequency

(f_{P C L K})

must be equal to or greater than seven times the RTC clock frequency (fRTCCLK). This ensures a secure behavior of the synchronization mechanism.

If the APB1 clock frequency is less than seven times the RTC clock frequency, the software must read the calendar time and date registers twice. If the second read of the RTC_TR gives the same result as the first read, this ensures that the data is correct. Otherwise a third read access must be done. In any case the APB1 clock frequency must never be lower than the RTC clock frequency.

The RSF bit is set in RTC_ICSR register each time the calendar registers are copied into the RTC_SSR, RTC_TR and RTC_DR shadow registers. The copy is performed every RTCCLK cycles. To ensure consistency between the 3 values, reading either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read. In case the software makes read accesses to the calendar in a time interval smaller than 1 RTCCLK periods: RSF must be cleared by software after the first calendar read, and then the software must wait until RSF is set before reading again the RTC_SSR, RTC_TR and RTC_DR registers.

After waking up from low-power mode (Stop or Standby), RSF must be cleared by software. The software must then wait until it is set again before reading the RTC_SSR, RTC_TR and RTC_DR registers.

The RSF bit must be cleared after wakeup and not before entering low-power mode.

After a system reset, the software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers. Indeed, a system reset resets the shadow registers to their default values.

After an initialization (refer to Calendar initialization and configuration on page 1562): the software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers.

After synchronization (refer to Section 35.3.11: RTC synchronization): the software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers.

When the BYPSHAD control bit is set in the RTC_CR register (bypass shadow registers)

Reading the calendar registers gives the values from the calendar counters directly, thus eliminating the need to wait for the RSF bit to be set. This is especially useful after exiting from low-power modes (Stop or Standby), since the shadow registers are not updated during these modes.

When the BYPSHAD bit is set to 1 , the results of the different registers might not be coherent with each other if an RTCCLK edge occurs between two read accesses to the registers. Additionally, the value of one of the registers may be incorrect if an RTCCLK edge occurs during the read operation. The software must read all the registers twice, and then compare the results to confirm that the data is coherent and correct. Alternatively, the software can just compare the two results of the least-significant calendar register.

RM0440Real-time clock (RTC)
Note:	While BYPSHAD = 1, instructions which read the calendar registers require one extra APB cycle to complete.
35.3.10	Resetting the RTC
	The calendar shadow registers (RTC_SSR, RTC_TR and RTC_DR) and some bits of the RTC status register (RTC_ICSR) are reset to their default values by all available system reset sources.
	On the contrary, the following registers are reset to their default values by a Backup domain reset and are not affected by a system reset: the RTC current calendar registers, the RTC control register (RTC_CR), the prescaler register (RTC_PRER), the RTC calibration register (RTC_CALR), the RTC shift register (RTC_SHIFTR), the RTC timestamp registers (RTC_TSSSR, RTC_TSTR and RTC_TSDR), the wakeup timer register (RTC_WUTR), an the alarm A and alarm B registers (RTC_ALRMASSR/RTC_ALRMAR and RTC_ALRMBSSR/RTC_ALRMBR)
	In addition, when clocked by LSE, the RTC keeps on running under system reset if the reset source is different from the Backup domain reset one (refer to RCC for details about RTC clock sources not affected by system reset). When a Backup domain reset occurs, the RTC is stopped and all the RTC registers are set to their reset values.
35.3.11	RTC synchronization
	The RTC can be synchronized to a remote clock with a high degree of precision. After reading the sub-second field (RTC_SSR or RTC_TSSSR), a calculation can be made of the precise offset between the times being maintained by the remote clock and the RTC. The RTC can then be adjusted to eliminate this offset by "shifting" its clock by a fraction of a second using RTC_SHIFTR
	RTC_SSR contains the value of the synchronous prescaler counter. This allows one to calculate the exact time being maintained by the RTC down to a resolution 1 / (PREDIV_S + 1) seconds. As a consequence, the resolution can be improved by increasing the synchronous prescaler value (PREDIV_S[14:0]. The maximum resolution allowed (30.52 µs with a 32768 Hz clock) is obtained with PREDIV_S set to 0x7FFF.
	However, increasing PREDIV_S means that PREDIV_A must be decreased in order to maintain the synchronous prescaler output at $1 Hz$ . In this way,the frequency of th asynchronous prescaler output increases, which may increase the RTC dynami consumption.
	The RTC can be finely adjusted using the RTC shift control register (RTC_SHIFTR). Writing to RTC_SHIFTR can shift (either delay or advance) the clock by up to a second with a resolution of $1 / (PREDIV_S + 1)$ seconds. The shift operation consists of adding the SUBFS[14:0] value to the synchronous prescaler counter SS[15:0]: this will delay the clock If at the same time the ADD1S bit is set, this results in adding one second and at the same time subtracting a fraction of second, so this will advance the clock
Caution:	Before initiating a shift operation,the user must check that $SS [15] = 0$ in order to ensure that no overflow will occur
Caution:	As soon as a shift operation is initiated by a write to the RTC_SHIFTR register, the SHPF flag is set by hardware to indicate that a shift operation is pending. This bit is cleared by hardware as soon as the shift operation has completed

Caution: This synchronization feature is not compatible with the reference clock detection feature: firmware must not write to RTC_SHIFTR when REFCKON = 1.

35.3.12 RTC reference clock detection

The update of the RTC calendar can be synchronized to a reference clock, RTC_REFIN, which is usually the mains frequency

(50 or 60 Hz)

. The precision of the RTC_REFIN reference clock should be higher than the

32.768 kHz

LSE clock. When the RTC_REFIN detection is enabled (REFCKON bit of RTC_CR set to 1), the calendar is still clocked by the LSE, and RTC_REFIN is used to compensate for the imprecision of the calendar update frequency

(1 Hz)

Each

1 Hz

clock edge is compared to the nearest RTC_REFIN clock edge (if one is found within a given time window). In most cases, the two clock edges are properly aligned. When the

1 Hz

clock becomes misaligned due to the imprecision of the LSE clock,the RTC shifts the

1 Hz

clock a bit so that future

1 Hz

clock edges are aligned. Thanks to this mechanism, the calendar becomes as precise as the reference clock.

The RTC detects if the reference clock source is present by using the

256 Hz

clock (ck_apre) generated from the

32.768 kHz

quartz. The detection is performed during a time window around each of the calendar updates (every

1 s

). The window equals

7 ck

apre periods when detecting the first reference clock edge. A smaller window of

3 ck

apre periods is used for subsequent calendar updates.

Each time the reference clock is detected in the window, the asynchronous prescaler which outputs the ck_spre clock is forced to reload. This has no effect when the reference clock and the

1 Hz

clock are aligned because the prescaler is being reloaded at the same moment. When the clocks are not aligned,the reload shifts future

1 Hz

clock edges a little for them to be aligned with the reference clock.

If the reference clock halts (no reference clock edge occurred during the

3 ck

_apre window), the calendar is updated continuously based solely on the LSE clock. The RTC then waits for the reference clock using a large

7 ck

apre period detection window centered on the ck_spre edge.

When the RTC_REFIN detection is enabled, PREDIV_A and PREDIV_S must be set to their default values:

PREDIV_A = 0x007F

PREVID_S = 0x00FF

Note:

RTC_REFIN clock detection is not available in Standby mode.

35.3.13 RTC smooth digital calibration

The RTC frequency can be digitally calibrated with a resolution of about

0.954 ppm

with a range from

- 487.1 ppm

+ 488.5 ppm

. The correction of the frequency is performed using series of small adjustments (adding and/or subtracting individual RTCCLK pulses). These adjustments are fairly well distributed so that the RTC is well calibrated even when observed over short durations of time.

The smooth digital calibration is performed during a cycle of about

2^{20}

RTCCLK pulses,or 32 seconds when the input frequency is

32768 Hz

. This cycle is maintained by a 20-bit counter, cal_cnt[19:0], clocked by RTCCLK.

The smooth calibration register (RTC_CALR) specifies the number of RTCCLK clock cycles to be masked during the calibration cycle:

Setting the bit CALM[0] to 1 causes exactly one pulse to be masked during the calibration cycle.

Setting CALM[1] to 1 causes two additional cycles to be masked

Setting CALM[2] to 1 causes four additional cycles to be masked

and so on up to CALM[8] set to 1 which causes 256 clocks to be masked.

Note:

CALM[8:0] (RTC_CALR) specifies the number of RTCCLK pulses to be masked during the calibration cycle. Setting the bit CALM[0] to 1 causes exactly one pulse to be masked during the calibration cycle at the moment when cal_cnt[19:0] is 0x80000; CALM[1] = 1 causes two other cycles to be masked (when cal_cnt is

\overset{―}{0} x 40000

and

0 x C 0000

); CALM[2]

= 1

causes four other cycles to be masked (cal_cnt = 0x2000/0x6000/0xA0000/0xE0000); and so on up to CALM[8]

= 1

which causes

256

clocks to be masked (cal_cnt

= 0

xXX800).

While CALM allows the RTC frequency to be reduced by up to 487.1 ppm with fine resolution,the bit CALP can be used to increase the frequency by

488.5 ppm

. Setting CALP to 1 effectively inserts an extra RTCCLK pulse every

2^{11}

RTCCLK cycles,which means that 512 clocks are added during every calibration cycle.

Using CALM together with CALP, an offset ranging from -511 to +512 RTCCLK cycles can be added during the calibration cycle, which translates to a calibration range of -487.1 ppm to

+ 488.5 ppm

with a resolution of about 0.954 ppm.

The formula to calculate the effective calibrated frequency (FCAL) given the input frequency (FRTCCLK) is as follows:

F_{CAL} = F_{RTCCLK} \times [1 + (CALP \times 512 - CALM) / (2^{20} + CALM - CALP \times 512)]

Calibration when PREDIV_A < 3

The CALP bit can not be set to 1 when the asynchronous prescaler value (PREDIV_A bits in RTC_PRER register) is less than 3. If CALP was already set to 1 and PREDIV_A bits are set to a value less than 3, CALP is ignored and the calibration operates as if CALP was equal to 0 .

To perform a calibration with PREDIV_A less than 3, the synchronous prescaler value (PREDIV_S) should be reduced so that each second is accelerated by 8 RTCCLK clock cycles, which is equivalent to adding 256 clock cycles every calibration cycle. As a result, between 255 and 256 clock pulses (corresponding to a calibration range from 243.3 to 244.1 ppm) can effectively be added during each calibration cycle using only the CALM bits.

With a nominal RTCCLK frequency of

32768 Hz

,when PREDIV_A equals 1 (division factor of 2), PREDIV_S should be set to 16379 rather than 16383 (4 less). The only other interesting case is when PREDIV_A equals 0, PREDIV_S should be set to 32759 rather than 32767 (8 less).

If PREDIV_S is reduced in this way, the formula given the effective frequency of the calibrated input clock is as follows:

F_{CAL} = F_{RTCCLK} \times [1 + (256 - CALM) / (2^{20} + CALM - 256)]

In this case, CALM[7:0] equals 0x100 (the midpoint of the CALM range) is the correct setting if RTCCLK is exactly

32768.00 Hz

Verifying the RTC calibration

RTC precision is ensured by measuring the precise frequency of RTCCLK and calculating the correct CALM value and CALP values. An optional

1 Hz

output is provided to allow applications to measure and verify the RTC precision.

Measuring the precise frequency of the RTC over a limited interval can result in a measurement error of up to

2

RTCCLK clock cycles over the measurement period, depending on how the digital calibration cycle is aligned with the measurement period.

However, this measurement error can be eliminated if the measurement period is the same length as the calibration cycle period. In this case, the only error observed is the error due to the resolution of the digital calibration.

By default, the calibration cycle period is 32 seconds.

Using this mode and measuring the accuracy of the

1 Hz

output over exactly 32 seconds guarantees that the measure is within

0.477 ppm (0.5 RTCCLK

cycles over 32 seconds, due to the limitation of the calibration resolution).

CALW16 bit of the RTC_CALR register can be set to 1 to force a 16- second calibration cycle period.

In this case, the RTC precision can be measured during 16 seconds with a maximum error of

0.954 ppm

(0.5 RTCCLK cycles over 16 seconds). However,since the calibration resolution is reduced, the long term RTC precision is also reduced to 0.954 ppm: CALM[0] bit is stuck at 0 when CALW16 is set to 1 .

CALW8 bit of the RTC_CALR register can be set to 1 to force a 8-second calibration cycle period.

In this case, the RTC precision can be measured during 8 seconds with a maximum error of

1.907 ppm

(

0.5 RTCCLK

cycles over

8 s

). The long term RTC precision is also reduced to

1.907 ppm: CALM[1:0] bits are stuck at 00 when CALW8 is set to 1 .

Re-calibration on-the-fly

The calibration register (RTC_CALR) can be updated on-the-fly while RTC_ICSR/INITF = 0, by using the follow process:

Poll the RTC_ICSR/RECALPF (re-calibration pending flag).

If it is set to 0 , write a new value to RTC_CALR, if necessary. RECALPF is then automatically set to 1

Within three ck_apre cycles after the write operation to RTC_CALR, the new calibration settings take effect.

35.3.14 Timestamp function

Timestamp is enabled by setting the TSE or ITSE bits of RTC_CR register to 1.

When TSE is set:

The calendar is saved in the timestamp registers (RTC_TSSSR, RTC_TSTR, RTC_TSDR) when a timestamp event is detected on the RTC_TS pin.

When TAMPTS is set:

The calendar is saved in the timestamp registers (RTC_TSSSR, RTC_TSTR, RTC_TSDR) when a tamper event is detected on the TAMP_INx pinx.

When ITSE is set:

	The calendar is saved in the timestamp registers (RTC_TSSSR, RTC_TSTR, RTC_TSDR) when an internal timestamp event is detected. The internal timestamp event is generated by the switch to the $V_{BAT}$ supply.
	When a timestamp event occurs, due to internal or external event, the timestamp flag bi (TSF) in RTC_SR register is set. In case the event is internal, the ITSF flag is also set in RTC_SR register.
	By setting the TSIE bit in the RTC_CR register, an interrupt is generated when a timestamp event occurs.
	If a new timestamp event is detected while the timestamp flag (TSF) is already set, the timestamp overflow flag (TSOVF) flag is set and the timestamp registers (RTC_TSTR and RTC_TSDR) maintain the results of the previous event.
Note:	TSF is set 2 ck_apre cycles after the timestamp event occurs due to synchronization process.
Note:	There is no delay in the setting of TSOVF. This means that if two timestamp events are close together, TSOVF can be seen as ’1’ while TSF is still ’0’. As a consequence, it is recommended to poll TSOVF only after TSF has been set.
Caution:	If a timestamp event occurs immediately after the TSF bit is supposed to be cleared, ther both TSF and TSOVF bits are set. To avoid masking a timestamp event occurring at the same moment, the application must not write 0 into TSF bit unless it has already read it to 1
Caution:	Optionally, a tamper event can cause a timestamp to be recorded. See the description of the TAMPTS control bit in the RTC control register (RTC_CR).
35.3.15	Calibration clock output
	When the COE bit is set to 1 in the RTC_CR register, a reference clock is provided on the CALIB device output.
	If the COSEL bit in the RTC_CR register is reset and PREDIV_A = 0x7F, the CALIB frequency is $f_{RTCCLK / 64}$ . This corresponds to a calibration output at 512 Hz for an RTCCLK frequency at 32.768 kHz. The CALIB duty cycle is irregular: there is a light jitter on falling edges. It is therefore recommended to use rising edges.
	When COSEL is set and "PREDIV_S+1" is a non-zero multiple of 256 (i.e: PREDIV_S[7:0] = 0xFF), the CALIB frequency is fRTCCLK/(256 * (PREDIV_A+1)). This corresponds to a calibration output at 1 Hz for prescaler default values (PREDIV_A = 0x7F, PREDIV_S 0xFF), with an RTCCLK frequency at 32.768 kHz.
Note:	When the CALIB output is selected, the RTC_OUT1 pin is automatically configured but the proof. RTC_OUT2 pin must be set as alternate function.
	When COSEL is cleared, the CALIB output is the output of the $6^{t h}$ stage of the asynchronous prescaler.
	When COSEL is set, the CALIB output is the output of the $8^{t h}$ stage of the synchronous prescaler.

35.3.16 Tamper and alarm output

The OSEL[1:0] control bits in the RTC_CR register are used to activate the alarm output TAMPALRM, and to select the function which is output. These functions reflect the contents of the corresponding flags in the RTC_SR register.

	When the TAMPOE control bit is set in the RTC_CR, all external and internal tamper flag. are ORed and routed to the TAMPALRM output. If OSEL = 00 the TAMPALRM out reflects only the tampers flags. If OSEL ≠ 00, the signal on TAMPALRM provides both tamper flags and alarm A, B, or wakeup flag.
	The polarity of the TAMPALRM output is determined by the POL control bit in RTC_CR so that the opposite of the selected flags bit is output when POL is set to 1
	TAMPALRM output
	The TAMPALRM pin can be configured in output open drain or output push-pull using the control bit TAMPALRM_TYPE in the RTC_CR register. It is possible to apply the intern pull-up in output mode thanks to TAMPALRM_PU in the RTC_CR
Note:	Once the TAMPALRM output is enabled, it has priority over CALIB on RTC_OUT1.
	When TAMPALRM output is selected, the RTC_OUT1 pin is automatically configured but the RTC_OUT2 pin must be set as alternate function. In case the TAMPALRM is configurated by the first figure the relation of open-drain in the RTC, the RTC_OUT1 GPIO must be configured as input.

35.4 RTC low-power modes

Table 335. Effect of low-power modes on RTC

Mode	Description
Sleep	No effect RTC interrupts cause the device to exit the Sleep mode
Stop	The RTC remains active when the RTC clock source is LSE or LSI. RTC interrupts cause the device to exit the Stop mode.
Standby	The RTC remains active when the RTC clock source is LSE or LSI. RTC interrupts cause the device to exit the Standby mode.
Shutdown	The RTC remains active when the RTC clock source is LSE. RTC interrupts cause th device to exit the Shutdown mode.

The table below summarizes the RTC pins and functions capability in all modes.

Table 336. RTC pins functionality over modes

Functions	Functional in all low- power modes except Standby and Shutdown modes	Functional in Standby and Shutdown mode	Functional in $V_{BAT}$ mode
RTC_TS	Yes	Yes	Yes
RTC_REFIN	Yes	No	No
RTC_OUT1	Yes	Yes	Yes
RTC_OUT2	Yes	No	No

35.5 RTC interrupts

The interrupt channel is set in the masked interrupt status register. The interrupt output is also activated.

Table 337. Interrupt requests

Interrupt acronym	Interrupt event	Event flag(1)	Enable control bit(2)	Interrupt clear method	Exit from Sleep mode	Exit from Stop and Standby mode	Exit from Shutdown mode
RTC	Alarm A	ALRAF	ALRAIE	write 1 in CALRAF	Yes	Yes(3)	Yes(4)
	Alarm B	ALRBF	ALRBIE	write 1 in CALRBF	Yes	Yes(3)	Yes(4)
	Timestamp	TSF	TSIE	write 1 in CTSF	Yes	Yes(3)	Yes(4)
	Wakeup timer interrupt	WUTF	WUTIE	write 1 in CWUTF	Yes	Yes(3)	Yes(4)

The event flags are in the RTC_SR register.

The interrupt masked flags (resulting from event flags AND enable control bits) are in the RTC_MISR register.

Wakeup from Stop and Standby modes is possible only when the RTC clock source is LSE or LSI.

Wakeup from Shutdown modes is possible only when the RTC clock source is LSE.

35.6 RTC registers

Refer to Section 1.2 on page 73 of the reference manual for a list of abbreviations used in register descriptions.

The peripheral registers can be accessed by words (32-bit).

35.6.1 RTC time register (RTC_TR)

The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page 1562 and Reading the calendar on page 1564.

This register is write protected. The write access procedure is described in RTC register write protection on page 1562.

Address offset: 0x00

Backup domain reset value: 0x00000000

System reset value: 0x0000 0000 (when BYPSHAD = 0, not affected when BYPSHAD = 1) Bits 31:23 Reserved, must be kept at reset value. Bit 22 PM: AM/PM notation 0: AM or 24-hour format 1: PM

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	PM	HT[1:0]		HU[3:0]
									rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	MNT[2:0]			MNU[3:0]				Res.	ST[2:0]			SU[3:0]
	rw	rw	rw	rw	rw	rw	rw		rw	rw	rw	rw	rw	rw	rw

Bits 21:20 HT[1:0]: Hour tens in BCD format

Bits 19:16 HU[3:0]: Hour units in BCD format

Bit 15 Reserved, must be kept at reset value.

Bits 14:12 MNT[2:0]: Minute tens in BCD format

Bits 11:8 MNU[3:0]: Minute units in BCD format

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 ST[2:0]: Second tens in BCD format

Bits 3:0 SU[3:0]: Second units in BCD format

35.6.2 RTC date register (RTC_DR)

The RTC_DR is the calendar date shadow register. This register must be written in

initialization mode only. Refer to Calendar initialization and configuration on page 1562 and Reading the calendar on page 1564.

This register is write protected. The write access procedure is described in RTC register write protection on page 1562.

Address offset: 0x04

Backup domain reset value: 0x00002101

System reset value: 0x00002101 (when BYPSHAD = 0, not affected when BYPSHAD = 1)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	YT[3:0]				YU[3:0]
								rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WDU[2:0]			MT	MU[3:0]				Res.	Res.	DT[1:0]		DU[3:0]
rw	rw	rw	rw	rw	rw	rw	rw			rw	rw	rw	rw	rw	rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:20 YT[3:0]: Year tens in BCD format

Bits 19:16 YU[3:0]: Year units in BCD format

Bits 15:13 WDU[2:0]: Week day units

000: forbidden

001: Monday

111: Sunday

Bit 12 MT: Month tens in BCD format

Bits 11:8 MU[3:0]: Month units in BCD format

Bits 7:6 Reserved, must be kept at reset value.

Bits 5:4 DT[1:0]: Date tens in BCD format

Bits 3:0 DU[3:0]: Date units in BCD format

Note: The calendar is frozen when reaching the maximum value, and can’t roll over.

35.6.3 RTC sub second register (RTC_SSR)

Address offset: 0x08

Backup domain reset value: 0x00000000

System reset value: 0x0000 0000 (when BYPSHAD = 0, not affected when BYPSHAD = 1)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SS[15:0]
r	r	r	r	r	r	r	r	$r$	r	r	r	r	r	r	$r$

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 SS[15:0]: Sub second value

SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below:

Second fraction

= (PREDIV_S - SS) / (PREDIV_S + 1)

Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct

time/date is one second less than as indicated by RTC_TR/RTC_DR.

35.6.4 RTC initialization control and status register (RTC_ICSR)

This register is write protected. The write access procedure is described in RTC register write protection on page 1562.

Address offset: 0x0C

Backup domain reset value: 0x00000007

System reset value: 0bxxxx xxxx xxxx xxxx xxxx xxxx 000x xxxx (not affected, except INIT, INITF, and RSF bits which are cleared to 0 )

Res.

Res

Res.

Res

Res.

INIT

INITF

RSF

INITS

SHPF

WUTW F

ALRB WF

ALRAW F

rc_w0

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 RECALPF: Recalibration pending Flag

The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 . Refer to Re-calibration on-the-fly.

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 INIT: Initialization mode

0 : Free running mode

1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.

Bit 6 INITF: Initialization flag

When this bit is set to 1 , the RTC is in initialization state, and the time, date and prescaler registers can be updated.

0 : Calendar registers update is not allowed

1: Calendar registers update is allowed

Bit

5

RSF: Registers synchronization flag

This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSR, RTC_TR and RTC_DR). This bit is cleared by hardware in initialization mode,while a shift operation is pending (SHPF

= 1

),or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software.

It is cleared either by software or by hardware in initialization mode.

0 : Calendar shadow registers not yet synchronized

1: Calendar shadow registers synchronized

Bit 4 INITS: Initialization status flag

This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state).

0 : Calendar has not been initialized

1: Calendar has been initialized

Bit 3 SHPF: Shift operation pending

This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect.

0 : No shift operation is pending

1: A shift operation is pending

Bit 2 WUTWF: Wakeup timer write flag

This bit is set by hardware when WUT value can be changed, after the WUTE bit has been set to 0 in RTC_CR.

It is cleared by hardware in initialization mode.

0: Wakeup timer configuration update not allowed except in initialization mode

1: Wakeup timer configuration update allowed

Bit 1 ALRBWF: Alarm B write flag

This bit is set by hardware when alarm B values can be changed, after the ALRBE bit has been set to 0 in RTC_CR.

It is cleared by hardware in initialization mode.

0: Alarm B update not allowed

1: Alarm B update allowed

Bit 0 ALRAWF: Alarm A write flag

This bit is set by hardware when alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR.

It is cleared by hardware in initialization mode.

0: Alarm A update not allowed

1: Alarm A update allowed

35.6.5 RTC prescaler register (RTC_PRER)

This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on

This register is write protected. The write access procedure is described in RTC register write protection on page 1562.

Address offset: 0x10

Backup domain reset value: 0x007F 00FF

System reset: not affected

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	PREDIV_A[6:0]
									rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	PREDIV_S[14:0]
	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:16 PREDIV_A[6:0]: Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)

Bit 15 Reserved, must be kept at reset value.

Bits 14:0 PREDIV_S[14:0]: Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency

=

ck_apre frequency/(PREDIV_S+1)

35.6.6 RTC wakeup timer register (RTC_WUTR)

This register can be written only when WUTWF is set to 1 in RTC_ICSR.

This register is write protected. The write access procedure is described in RTC register write protection on page 1562.

Address offset: 0x14

Backup domain reset value: 0x0000 FFFF

System reset: not affected

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 WUT[15:0]: Wakeup auto-reload value bits

When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every

(WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register.

When WUCKSEL[2]

= 1

,the wakeup timer becomes 17-bits and WUCKSEL[1] effectively

becomes WUT[16] the most-significant bit to be reloaded into the timer.

The first assertion of WUTF occurs between WUT and (WUT + 1) ck_wut cycles after WUTE

is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] = 011 (RTCCLK/2) is forbidden.

35.6.7 RTC control register (RTC_CR)

This register is write protected. The write access procedure is described in RTC register write protection on page 1562.

Address offset: 0x18

Backup domain reset value: 0x00000000

System reset: not affected

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OUT2 EN	TAMP ALRM TYPE	TAMP ALRM PU	Res.	Res.	TAMP OE	TAMP TS	ITSE	COE	OSEL[1:0]		POL	COSEL	BKP	SUB1H	ADD1H
rw	rw	rw			rw	rw	rw	rw	rw	rw	rw	rw	rw	w	w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TSIE	WUTIE	ALRB 1E	ALRA IE	TSE	WUTE	ALRBE	ALRAE	Res.	FMT	BYP SHAD	REFCK ON	TS EDGE	WUCKSEL[2:0]
rw	rw	rw	rw	rw	rw	rw	rw		rw	rw	rw	rw	rw	rw	rw

Bit 31 OUT2EN: RTC_OUT2 output enable

Setting this bit allows to remap the RTC outputs on RTC_OUT2 as follows:

OUT2EN = 0: RTC output 2 disable

If OSEL ≠ 00 or TAMPOE = 1: TAMPALRM is output on RTC_OUT1

If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT1

OUT2EN = 1: RTC output 2 enable

(OSEL \neq 00 or TAMPOE = 1)

and COE

= 0

: TAMPALRM is output on RTC_OUT2

If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT2

If (OSEL≠ 00 or TAMPOE = 1) and COE = 1: CALIB is output on RTC_OUT2 and

TAMPALRM is output on RTC_OUT1.

Bit 30 TAMPALRM_TYPE: TAMPALRM output type

0: TAMPALRM is push-pull output

1: TAMPALRM is open-drain output

Bit 29 TAMPALRM_PU: TAMPALRM pull-up enable

0 : No pull-up is applied on TAMPALRM output

1: A pull-up is applied on TAMPALRM output

Bits 28:27 Reserved, must be kept at reset value.

Bit 26 TAMPOE: Tamper detection output enable on TAMPALRM

0 : The tamper flag is not routed on TAMPALRM

1: The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and

with the polarity provided by POL.

Bit 25 TAMPTS: Activate timestamp on tamper detection event

0: Tamper detection event does not cause a RTC timestamp to be saved

1: Save RTC timestamp on tamper detection event

TAMPTS is valid even if TSE

= 0

in the RTC_CR register. Timestamp flag is set after the

tamper flags, therefore if TAMPTS and TSIE are set, it is recommended to disable the

tamper interrupts in order to avoid servicing 2 interrupts.

Bit 24 ITSE: timestamp on internal event enable

0 : internal event timestamp disabled

1: internal event timestamp enabled

Bit 23 COE: Calibration output enable

This bit enables the CALIB output

0: Calibration output disabled

1: Calibration output enabled

Bits 22:21 OSEL[1:0]: Output selection

These bits are used to select the flag to be routed to TAMPALRM output.

00: Output disabled

01: Alarm A output enabled

10: Alarm B output enabled

11: Wakeup output enabled

Bit 20 POL: Output polarity

This bit is used to configure the polarity of TAMPALRM output.

0: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]), or

when a TAMPxF/ITAMPxF is asserted (if TAMPOE = 1).

1: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]), or

when a TAMPxF/ITAMPxF is asserted (if TAMPOE = 1).

Bit 19 COSEL: Calibration output selection

When

COE = 1

,this bit selects which signal is output on CALIB.

0: Calibration output is

512 Hz

1: Calibration output is

1 Hz

These frequencies are valid for RTCCLK at

32.768 kHz

and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255). Refer to Section 35.3.15: Calibration clock output.

Bit 18 BKP: Backup

This bit can be written by the user to memorize whether the daylight saving time change has been performed or not.

Bit 17 SUB1H: Subtract 1 hour (winter time change)

When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0 . This bit is always read as 0 .

Setting this bit has no effect when current hour is 0 .

0 : No effect

1: Subtracts 1 hour to the current time. This can be used for winter time change.

Bit 16 ADD1H: Add 1 hour (summer time change)

When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0 .

0 : No effect

1: Adds 1 hour to the current time. This can be used for summer time change

Bit 15 TSIE: Timestamp interrupt enable

0: Timestamp interrupt disable

1: Timestamp interrupt enable

Bit 14 WUTIE: Wakeup timer interrupt enable

0 : Wakeup timer interrupt disabled

1: Wakeup timer interrupt enabled

Bit 13 ALRBIE: Alarm B interrupt enable

0: Alarm B interrupt disable

1: Alarm B interrupt enable

Bit 12 ALRAIE: Alarm A interrupt enable

0: Alarm A interrupt disabled

1: Alarm A interrupt enabled

Bit 11 TSE: timestamp enable

0 : timestamp disable

1: timestamp enable

Bit 10 WUTE: Wakeup timer enable

0 : Wakeup timer disabled

1: Wakeup timer enabled

Note: When the wakeup timer is disabled, wait for WUTWF=1 before enabling it again.

Bit 9 ALRBE: Alarm B enable

0: Alarm B disabled

1: Alarm B enabled

Bit 8 ALRAE: Alarm A enable

0: Alarm A disabled

1: Alarm A enabled

Bit 7 Reserved, must be kept at reset value.

Bit 6 FMT: Hour format

0: 24 hour/day format

1: AM/PM hour format

Bit 5 BYPSHAD: Bypass the shadow registers

0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from

the shadow registers, which are updated once every two RTCCLK cycles.

1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken

directly from the calendar counters.

Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK,

BYPSHAD must be set to 1 .

Bit 4 REFCKON: RTC_REFIN reference clock detection enable ( 50 or

60 Hz

)

0: RTC_REFIN detection disabled

1: RTC_REFIN detection enabled

Note: PREDIV_S must be 0x00FF.

Bit 3 TSEDGE: Timestamp event active edge

0: RTC_TS input rising edge generates a timestamp event

1: RTC_TS input falling edge generates a timestamp event

TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting.

Bits 2:0 WUCKSEL[2:0]: ck_wut wakeup clock selection

000: RTC/16 clock is selected

001: RTC/8 clock is selected

010: RTC/4 clock is selected

011: RTC/2 clock is selected

10x: ck_spre (usually

1 Hz

) clock is selected

11 x : ck

spre (usually

1 Hz

) clock is selected and

2^{16}

is added to the WUT counter value

Note: Bits 6 and 4 of this register can be written in initialization mode only (RTC_ICSR/INITF = 1). WUT = wakeup unit counter value. WUT = (0x0000 to 0xFFFF) + 0x10000 added when WUCKSEL[2:1 = 11].

Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit = 0 and RTC_ICSR WUTWF bit = 1.

It is recommended not to change the hour during the calendar hour increment as it could mask the incrementation of the calendar hour.

ADD1H and SUB1H changes are effective in the next second.

35.6.8 RTC write protection register (RTC_WPR)

Address offset: 0x24

Reset value: 0x00000000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res:	Res.	Res.	Res.	KEY[7:0]
								w	w	w	w	w	w	w	w

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 KEY[7:0]: Write protection key

This byte is written by software.

Reading this byte always returns

0 \times 00

Refer to RTC register write protection for a description of how to unlock RTC register write protection.

35.6.9 RTC calibration register (RTC_CALR)

This register is write protected. The write access procedure is described in RTC register write protection on page 1562.

Address offset: 0x28

Backup domain reset value: 0x00000000

System reset: not affected

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CALP	CALW8	CALW 16	Res.	Res.	Res.	Res.	CALM[8:0]
rw	rw	rw					rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 CALP: Increase frequency of RTC by

488.5 ppm

0: No RTCCLK pulses are added.

1: One RTCCLK pulse is effectively inserted every

2^{11}

pulses (frequency increased by 488.5 ppm).

This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is

32768 Hz

,the number of

RTCCLK pulses added during a 32-second window is calculated as follows: (512 × CALP) - CALM.

Refer to Section 35.3.13: RTC smooth digital calibration.

Bit 14 CALW8: Use an 8-second calibration cycle period

When CALW8 is set to 1 , the 8-second calibration cycle period is selected.

Note: CALM[1:0] are stuck at 00 when CALW8 = 1. Refer to Section 35.3.13: RTC smooth digital calibration.

Bit 13 CALW16: Use a 16-second calibration cycle period

When CALW16 is set to 1 , the 16-second calibration cycle period is selected. This bit must not be set to 1 if CALW8 = 1.

Note: CALM[0] is stuck at 0 when CALW16 = 1. Refer to Section 35.3.13: RTC smooth digital calibration.

Bits 12:9 Reserved, must be kept at reset value.

Bits 8:0 CALM[8:0]: Calibration minus

The frequency of the calendar is reduced by masking CALM out of

2^{20}

RTCCLK pulses (32 seconds if the input frequency is

32768 Hz

). This decreases the frequency of the calendar with a resolution of

0.9537 ppm

To increase the frequency of the calendar, this feature should be used in conjunction with

CALP. See Section 35.3.13: RTC smooth digital calibration on page 1566.

35.6.10 RTC shift control register (RTC_SHIFTR)

This register is write protected. The write access procedure is described in RTC register write protection on page 1562.

Address offset: 0x2C

Backup domain reset value: 0x00000000

System reset: not affected

Bit 31 ADD1S: Add one second

0 : No effect

1: Add one second to the clock/calendar

This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF

= 1

,in RTC_ICSR).

This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation.

Bits 30:15 Reserved, must be kept at reset value.

Bits 14:0 SUBFS[14:0]: Subtract a fraction of a second

These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF

= 1

,in RTC_ICSR).

The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by:

Delay (seconds) = SUBFS / (PREDIV_S + 1)

A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by:

Advance (seconds)

= (1 - (SUBFS / (PREDIV_S + 1)))

Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF = 1 to be sure that the shadow registers have been updated with the shifted time.

35.6.11 RTC timestamp time register (RTC_TSTR)

The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when TSF bit is reset.

Address offset: 0x30

Backup domain reset value: 0x00000000

System reset: not affected

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	PM	HT[1:0]		HU[3:0]
									r	r	r	r	r	r	r

Res.	MNT[2:0]			MNU[3:0]				Res.	ST[2:0]			SU[3:0]
	r	r	r	r	r	r	r		r	r	r	r	r	r	r

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 PM: AM/PM notation

0: AM or 24-hour format

1: PM

Bits 21:20 HT[1:0]: Hour tens in BCD format.

Bits 19:16 HU[3:0]: Hour units in BCD format.

Bit 15 Reserved, must be kept at reset value.

Bits 14:12 MNT[2:0]: Minute tens in BCD format.

Bits 11:8 MNU[3:0]: Minute units in BCD format.

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 ST[2:0]: Second tens in BCD format.

Bits 3:0 SU[3:0]: Second units in BCD format.

35.6.12 RTC timestamp date register (RTC_TSDR)

The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when TSF bit is reset.

Address offset: 0x34

Backup domain reset value: 0x00000000

System reset: not affected

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WDU[2:0]			MT	MU[3:0]				Res.	Res.	DT[1:0]		DU[3:0]
r	r	r	r	r	r	r	r			r	r	$r$	r	r	r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:13 WDU[2:0]: Week day units

Bit 12 MT: Month tens in BCD format

Bits 11:8 MU[3:0]: Month units in BCD format

Bits 7:6 Reserved, must be kept at reset value.

Bits 5:4 DT[1:0]: Date tens in BCD format

Bits 3:0 DU[3:0]: Date units in BCD format

35.6.13 RTC timestamp sub second register (RTC_TSSSR)

The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when the TSF bit is reset.

Address offset: 0x38

Backup domain reset value: 0x00000000

System reset: not affected

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 SS[15:0]: Sub second value

SS[15:0] is the value of the synchronous prescaler counter when the timestamp event occurred.

35.6.14 RTC alarm A register (RTC_ALRMAR)

This register can be written only when ALRAWF is set to 1 in RTC_ICSR, or in initialization mode.

This register is write protected. The write access procedure is described in RTC register write protection on page 1562.

Address offset: 0x40

Backup domain reset value: 0x00000000

System reset: not affected

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MSK4	WDSE L	DT[1:0]		DU[3:0]				MSK3	PM	HT[1:0]		HU[3:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MSK2	MNT[2:0]			MNU[3:0]				MSK1	ST[2:0]			SU[3:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bit 31 MSK4: Alarm A date mask

0: Alarm A set if the date/day match

1: Date/day don't care in alarm A comparison

Bit 30 WDSEL: Week day selection

0: DU[3:0] represents the date units

1: DU[3:0] represents the week day. DT[1:0] is don't care.

Bits 29:28 DT[1:0]: Date tens in BCD format

Bits 27:24 DU[3:0]: Date units or day in BCD format

Bit 23 MSK3: Alarm A hours mask

0 : Alarm A set if the hours match

1: Hours don't care in alarm A comparison

Bit 22 PM: AM/PM notation

0: AM or 24-hour format

1: PM

Bits 21:20 HT[1:0]: Hour tens in BCD format

Bits 19:16 HU[3:0]: Hour units in BCD format

Bit 15 MSK2: Alarm A minutes mask

0: Alarm A set if the minutes match

1: Minutes don't care in alarm A comparison

Bits 14:12 MNT[2:0]: Minute tens in BCD format

Bits 11:8 MNU[3:0]: Minute units in BCD format

Bit 7 MSK1: Alarm A seconds mask

0 : Alarm A set if the seconds match

1: Seconds don't care in alarm A comparison

Bits 6:4 ST[2:0]: Second tens in BCD format.

Bits 3:0 SU[3:0]: Second units in BCD format.

35.6.15 RTC alarm A sub second register (RTC_ALRMASSR)

This register can be written only when ALRAWF is set to 1 in RTC_ICSR, or in initialization mode.

This register is write protected. The write access procedure is described in RTC register write protection on page 1562.

Address offset: 0x44

Backup domain reset value: 0x00000000

System reset: not affected

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	MASKSS[3:0]				Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
				rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	SS[14:0]
	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	w	rw	rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit

0 : No comparison on sub seconds for alarm A. The alarm is set when the seconds unit is

incremented (assuming that the rest of the fields match).

1:SS[14:1] are don't care in alarm A comparison. Only SS[0] is compared.

2: SS[14:2] are don't care in alarm A comparison. Only SS[1:0] are compared.

3:SS[14:3] are don't care in alarm A comparison. Only SS[2:0] are compared.

12:SS[14:12] are don't care in alarm A comparison. SS[11:0] are compared.

13:SS[14:13] are don't care in alarm A comparison. SS[12:0] are compared.

14:SS[14] is don't care in alarm A comparison. SS[13:0] are compared.

15:All 15 SS bits are compared and must match to activate alarm.

The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be

different from 0 only after a shift operation.

Note: The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation.

Bits 23:15 Reserved, must be kept at reset value.

Bits 14:0 SS[14:0]: Sub seconds value

This value is compared with the contents of the synchronous prescaler counter to determine if alarm

A

is to be activated. Only bits 0 up MASKSS-1 are compared.

35.6.16 RTC alarm B register (RTC_ALRMBR)

This register can be written only when ALRBWF is set to 1 in RTC_ICSR, or in initialization mode.

This register is write protected. The write access procedure is described in RTC register write protection on page 1562.

Address offset: 0x48

Backup domain reset value: 0x00000000

System reset: not affected

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MSK4	WD SEL	DT[1:0]		DU[3:0]				MSK3	PM	HT[1:0]		HU[3:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MSK2	MNT[2:0]			MNU[3:0]				MSK1	ST[2:0]			SU[3:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bit 31 MSK4: Alarm B date mask

0 : Alarm B set if the date and day match

1: Date and day don't care in alarm B comparison

Bit 30 WDSEL: Week day selection

0: DU[3:0] represents the date units

1: DU[3:0] represents the week day. DT[1:0] is don't care.

Bits 29:28 DT[1:0]: Date tens in BCD format

Bits 27:24 DU[3:0]: Date units or day in BCD format

Bit 23 MSK3: Alarm B hours mask

0 : Alarm B set if the hours match

1: Hours don't care in alarm B comparison

Bit 22 PM: AM/PM notation

0: AM or 24-hour format

1: PM

Bits 21:20 HT[1:0]: Hour tens in BCD format

Bits 19:16 HU[3:0]: Hour units in BCD format

Bit 15 MSK2: Alarm B minutes mask

0 : Alarm B set if the minutes match

1: Minutes don't care in alarm B comparison

Bits 14:12 MNT[2:0]: Minute tens in BCD format

Bits 11:8 MNU[3:0]: Minute units in BCD format

Bit 7 MSK1: Alarm B seconds mask

0 : Alarm B set if the seconds match

1: Seconds don't care in alarm B comparison

Bits 6:4 ST[2:0]: Second tens in BCD format

Bits 3:0 SU[3:0]: Second units in BCD format

35.6.17 RTC alarm B sub second register (RTC_ALRMBSSR)

This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode.

This register is write protected. The write access procedure is described in Section : RTC register write protection.

Address offset: 0x4C

Backup domain reset value: 0x00000000

System reset: not affected

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	MASKSS[3:0]				Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
				rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	SS[14:0]
	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	w	rw	rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit

0x0: No comparison on sub seconds for alarm B. The alarm is set when the seconds unit is

incremented (assuming that the rest of the fields match).

0x1: SS[14:1] are don't care in alarm B comparison. Only SS[0] is compared.

0x2: SS[14:2] are don't care in alarm B comparison. Only SS[1:0] are compared.

0x3: SS[14:3] are don't care in alarm B comparison. Only SS[2:0] are compared.

0xC: SS[14:12] are don't care in alarm B comparison. SS[11:0] are compared.

0xD: SS[14:13] are don’t care in alarm B comparison. SS[12:0] are compared.

0xE: SS[14] is don’t care in alarm B comparison. SS[13:0] are compared.

0xF: All 15 SS bits are compared and must match to activate alarm.

The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be

different from 0 only after a shift operation.

Bits 23:15 Reserved, must be kept at reset value.

Bits 14:0 SS[14:0]: Sub seconds value

This value is compared with the contents of the synchronous prescaler counter to determine if alarm B is to be activated. Only bits 0 up to MASKSS-1 are compared.

35.6.18 RTC status register (RTC_SR)

Address offset: 0x50

Backup domain reset value: 0x00000000

System reset: not affected

To	14	13	12	11	10	9	0	7	0	0	4	3	2	1	U
Res	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	ITSF	TSOVF	TSF	WUTF	ALRBF	ALRAF
										r	r	r	r	r	r

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 ITSF: Internal timestamp flag

This flag is set by hardware when a timestamp on the internal event occurs.

Bit 4 TSOVF: Timestamp overflow flag

This flag is set by hardware when a timestamp event occurs while TSF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.

Bit 3 TSF: Timestamp flag

This flag is set by hardware when a timestamp event occurs.

If ITSF flag is set, TSF must be cleared together with ITSF.

Bit 2 WUTF: Wakeup timer flag

This flag is set by hardware when the wakeup auto-reload counter reaches 0 .

This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again.

Bit 1 ALRBF: Alarm B flag

This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the alarm B register (RTC_ALRMBR).

Bit 0 ALRAF: Alarm A flag

This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the alarm A register (RTC_ALRMAR).

Note: The bits of this register are cleared few APB clock cycles after setting their corresponding clear bit in the RTC_SCR register. After clearing the flag, read it until it is read at 0 before leaving the interrupt routine.

35.6.19 RTC masked interrupt status register (RTC_MISR)

Address offset: 0x54

Backup domain reset value: 0x00000000

System reset: not affected

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	ITS MF	TSOV MF	TS MF	WUT MF	ALRB MF	ALRA MF
										r	r	r	$r$	r	r

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 ITSMF: Internal timestamp masked flag

This flag is set by hardware when a timestamp on the internal event occurs and timestampinterrupt is raised.

Bit 4 TSOVMF: Timestamp overflow masked flag

This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.

Bit 3 TSMF: Timestamp masked flag

This flag is set by hardware when a timestamp interrupt occurs.

If ITSF flag is set, TSF must be cleared together with ITSF.

Bit 2 WUTMF: Wakeup timer masked flag

This flag is set by hardware when the wakeup timer interrupt occurs.

This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again.

Bit 1 ALRBMF: Alarm B masked flag

This flag is set by hardware when the alarm B interrupt occurs.

Bit 0 ALRAMF: Alarm A masked flag

This flag is set by hardware when the alarm A interrupt occurs.

Note: e: The bits of this register are cleared few APB clock cycles after setting their corresponding clear bit in the RTC_SCR register. After clearing the flag, read it until it is read at 0 before leaving the interrupt routine.

35.6.20 RTC status clear register (RTC_SCR)

Address offset: 0x5C

Backup domain reset value: 0x00000000

System reset: not affected

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	CITS F	CTSOV F	CTS F	CWUT F	CALRB F	CALRA F
										w	w	w	w	w	w

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 CITSF: Clear internal timestamp flag

Writing 1 in this bit clears the ITSF bit in the RTC_SR register.

Bit 4 CTSOVF: Clear timestamp overflow flag

Writing 1 in this bit clears the TSOVF bit in the RTC_SR register.

It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.

35.6.21 RTC register map

Table 338. RTC register map and reset values

Offset	Register	31	30	23	23	27	26	25	24	23	22	21	20	1Q	1.	17	伯	1.5	14	13	12	11	10	9	8	7	6	5	4	32	10
0x00	RTC_TR		ga	For	股份	中国	3	海	3	COM	PDF	HT [1:0]		HU[3:0]					MNT[2:0]			MNU[3:0]					ST[2:0]			SU[3:0]
0x00	Reset value										000			0000					0	0	0	0000					0	0	0	0000
0x04	RTC_DR	3,050	R.	Let	(1)	3,010	5,050	(a)	好	YT[3:0]				YU[3:0]				WDU[2:0]			VI.	MU[3:0]				3		DT [1:0]		DU[3:0]
0x04	Reset value									0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	1			0	0	00	01
0x08	RTC_SSR	:	：	S	BRATT	33	333	千港元	粉	千港元	88	千港元	BUR	YU	3	Proof.	33	SS[15:0]
0x08	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	00	00
0x0C	RTC_ICSR	SHI	88	5	郎	3	6,659	3	8	粥	3	串	6	33	串	a	3d7V038	33	8	E	郎	13	8	粉	1,040	II.	Klit	RSS	IVE	SHATEJM INM	JMAYTYJMVY
0x0C	Reset value																0									0	0	0	0	01	11
0x10	RTC_PRER		千港元	SOC	好	3	(2)	SHIP	：	好好	PREDIV_A[6:0]							PREDIV_S[14:0]
0x10	Reset value										1	1	1	1	1	1	1	0	0	0	0	0	0	0	0	1	1	1	1	11	11
0x14	RTC_WUTR Reset value		13	3	B	BUS	3.00	BUR	千港元	Effective	留	SHE	福	134,691	324	RASE	Effects	1	1	1	1	1	1	1	1	WUT[15:0] 1	1	1	1	11	11
0x18	RTC_CR	NEZINO	$\exists d$ Al $\overset{―}{}$ Wa TVdW VI.	nd warydwyl		3	30dWV1	SIdWV1	ICS	0.00	O SEL [1:0]		PO	13SOO	BKPH	HI ans	HLACK	TSE	311NM	3188 TV	3IVY1V	155	WIST	ARBIR	Apr-12	福	Furth	CVHSd人8	NOXOJEY	3903S1	wuck SEL[2:0]
0x18	Reset value	0	0	0			0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0		0	0	0	00	00
0x24	RTC_WPR	3	COND	3	：	部	粉	8	千港元	：	串	3	好	PAR	y	E	8	1.5	3	8	B	y	8	19	8	KEY[7:0]
0x24	Reset value																									0	0	0	0	00	00
0x28	RTC_ CALR	g	超	8	3	商	8	千港元	照	3	8	(a)	招	(a)	3	好	3	CANT	8MTVO	91M7V0		3	3	3	CALM[8:0]
0x28	Reset value																	0	0	0					0	0	0	0	0	00	00
0x2C	RTC_SHIFTR	slady		0	路	5,000	(a)	SHU	PROS	S	1.00	SHU	High	5	E	5,549	1.5	3,046	SUBFS[14:0]
0x2C	Reset value	0																	0	0	0	0	0	0	0	0	0	0	0	00	00
0x30	RTC_TSTR	(a)	好	(a)	串	8	134	SCON	好	5,000	PR	HK$’000		HU[3:0]					[0:z]⊥NW			MNU[3:0]				3.00	ST[2:0]			SU[3:0]
0x30	Reset value										0	0	0	0	0	0	0		0	0	0	0000					0	0	0	00	00
0x34	RTC_TSDR		1.5	8	时	S	Proof.	(1)	PROS	电话	COM	(1)	BUB	S	PHY	Proof.	.9	WDU[1:0]			VII	MU[3:0]				3		DT [1:0]		DU[3:0]
0x34	Reset value																	0	0	0	0	0000						0	0	00	00
0x38	RTC_TSSSR			COMP		8				COMP				超			好		SS[15:0]
0x38	Reset value																	0000000000000000

Table 338. RTC register map and reset values (continued)

Offset	Register	31	30	23	23	27	26	23	24	23	22	21	20	1.	1,6	17	伯	16	14	13	12	11	10	9	8	7	6	5	4	3	2	1O
0x40	RTC_ALRMAR	MSS	73SGM	DT [1:0]		DU[3:0]				MS5	Proof.	HT [1:0]		HU[3:0]				MSE2	MNT[2:0]			MNU[3:0]				Math.	ST[2:0]			SU[3:0]
0x40	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	00
0x44	RTC ALRMASSR	B	For	(a)	For	MASKSS [3:0]				bill	BUS	W	S	Effect	Effects	Effective	SQUE	STRON	SS[14:0]
0x44	Reset value					0	0	0	0										0	0	0	0	0	0	0	0	0	0	0	0	0	00
0x48	RTC ALRMBR	MSS	13SGM	DT [1:0]		DU[3:0]				MS5	PR	HT [1:0]		HU[3:0]				MSE2	MNT[2:0]			MNU[3:0]				MSS	ST[2:0]			SU[3:0]
0x48	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	00
0x4C	RTC ALRMBSSR	3	：	1,000	3	MASKSS [3:0]				中國	3	3	3	新	3	3	39	钢	SS[14:0]
0x4C	Reset value					0	0	0	0										0	0	0	0	0	0	0	0	0	0	0	0	0	00
0x50	RTC_SR	(1)	中心	(1,000)	1,000	1,000	(1,000)	SHIP	(a)	For	Let	S	(a)	3	5,053	1,000	SQUE	路	(1)	PUL	3	中国	3	中国	3,133	1.00	vi	IGS	HAOSI	TS	While	AREEJVY TV
0x50	Reset value																											0	0	0	0	00
0x54	RTC MISR	S	(a)	1.00	1.00%	1.00	5,050	股本	(a)	股本	(a)	si	1,000	SU	Effect	SU	STA	好	(a)	Let	33	1.00	福	Let	福	8	3	IGNE	JIWAOSI	TST	JWINM	JW SYTYJWVY
0x54	Reset value																											0	0	0	0	00
0x5C	RTC SCR		1,131	3	1,133	3	欢迎	5,000	(a)	5,000	1,000	BALL	欢迎	Sept.	8	(a)	：	8	3	3	8	3,373	BUCK	1,173	BUCK	S	：	GISTE	HAOSIO	CSTE	310M0	388770JVY170
0x5C	Reset value																											0	0	0	0	00

Refer to Section 2.2 on page 81 for the register boundary addresses.

36 Tamper and backup registers (TAMP)

36.1 Introduction

32 (category 3 and category 4 devices) or 16 (category 2 devices) 32-bit backup registers are retained in all low-power modes and also in

V_{BAT}

mode. They can be used to store sensitive data as their content is protected by an tamper detection circuit. 3 tamper pins and 4 internal tampers are available for anti-tamper detection. The external tamper pins can be configured for edge detection, or level detection with or without filtering.

36.2 TAMP main features

32 (category 3 and category 4 devices) or 16 (category 2 devices) backup registers:

the backup registers (TAMP_BKPxR) are implemented in the RTC domain that remains powered-on by $V_{BAT}$ when the $V_{DD}$ power is switched off.

3 external tamper detection events.

External passive tampers with configurable filter and internal pull-up.

4 internal tamper events.

Any tamper detection can generate a RTC timestamp event.

Any tamper detection can erase the backup registers.

36.3.2 TAMP pins and internal signals

Table 339. TAMP input/output pins

Pin name	Signal type	Description
TAMP_INx (x = pin index)	Input	Tamper input pin

Table 340. TAMP internal input/output signals

Internal signal name	Signal type	Description
tamp_ker_ck	Input	TAMP kernel clock, connected to rtc_ker_ck and also named RTCCLK in this document
tamp_pclk	Input	TAMP APB clock, connected to rtc_pclk
tamp_itamp[y] (y = signal index)	Inputs	Internal tamper event sources
tamp_evt	Output	Tamper event detection (internal or external) The tamp_evt is used to generate a RTC timestamp event
tamp_erase	Output	Device secrets erase request following tamper event detection (internal or external)
tamp_it	Output	TAMP interrupt (refer to Section 36.5: TAMP interrupts for details)
tamp_trg[x] (x = signal index)	Output	Tamper detection trigger

The TAMP kernel clock is usually the LSE at

32.768 kHz

although it is possible to select other clock sources in the RCC (refer to RCC for more details). Some detections modes are not available in some low-power modes or

V_{BAT}

when the selected clock is not LSE (refer to Section 36.4: TAMP low-power modes for more details.

Table 341. TAMP interconnection

Signal name	Source/Destination
tamp_evt	rtc_tamp_evt used to generate a timestamp event
tamp_erase	The tamp_erase signal is used to erase the device secrets listed hereafter: backup registers
tamp_itamp3	LSE monitoring
tamp_itamp4	HSE monitoring
tamp_itamp5	RTC calendar overflow (rtc_calovf)
tamp_itamp6	ST manufacturer readout

36.3.3 TAMP register write protection

After system reset, the TAMP registers (including backup registers) are protected against parasitic write access by the DBP bit in the power control peripheral (refer to the PWR power control section). DBP bit must be set in order to enable TAMP registers write access.

36.3.4 Tamper detection

The tamper detection can be configured for the following purposes:

erase the backup registers (default configuration)

generate an interrupt, capable to wakeup from Stop and Standby mode

generate a hardware trigger for the low-power timers

TAMP backup registers

The backup registers (TAMP_BKPxR) are not reset by system reset or when the device wakes up from Standby mode.

The backup registers are reset when a tamper detection event occurs except if the TAMPxNOER bit is set, or if the TAMPxMSK is set in the TAMP_CR2 register.

Note: The backup registers are also erased when the readout protection of the flash is changed from level 1 to level 0 .

Tamper detection initialization

Each input can be enabled by setting the corresponding TAMPxE bits to 1 in the TAMP_CR register.

Each TAMP_INx tamper detection input is associated with a flag TAMPxF in the TAMP_SR register.

When TAMPxMSK is cleared:

The TAMPxF flag is asserted after the tamper event on the pin, with the latency provided below:

3 ck_apre cycles when TAMPFLT differs from 0x0 (level detection with filtering)

$3 ck$ _apre cycles when TAMPTS $= 1$ (timestamp on tamper event)

No latency when TAMPFLT = 0x0 (edge detection) and TAMPTS = 0

A new tamper occurring on the same pin during this period and as long as TAMPxF is set cannot be detected.

When TAMPxMSK is set:

A new tamper occurring on the same pin cannot be detected during the latency described above and

2.5 ck_rtc

additional cycles.

By setting the TAMPxIE bit in the TAMP_IER register, an interrupt is generated when a tamper detection event occurs (when TAMPxF is set). Setting TAMPxIE is not allowed when the corresponding TAMPxMSK is set.

Trigger output generation on tamper event

The tamper event detection can be used as trigger input by the low-power timers.

When TAMPxMSK bit in cleared in TAMP_CR register, the TAMPxF flag must be cleared by software in order to allow a new tamper detection on the same pin.

When TAMPxMSK bit is set, the TAMPxF flag is masked, and kept cleared in TAMP_SR register. This configuration allows to trig automatically the low-power timers in Stop mode, without requiring the system wakeup to perform the TAMPxF clearing. In this case, the backup registers are not cleared.

		This feature is available only when the tamper is configured in the Level detection with filtering on tamper inputs (passive mode) mode (TAMPFLT ≠ 00 and active mode is not selected).
		Timestamp on tamper event
		With TAMPTS set to 1 in the RTC_CR, any tamper event causes a timestamp to occur. In this case, either the TSF bit or the TSOVF bit is set in RTC_SR, in the same manner as if normal timestamp event occurs. The affected tamper flag register TAMPxF is set in the TAMP_SR at the same time that TSF or TSOVF is set in the RTC_SF
		Edge detection on tamper inputs (passive mode)
		If the TAMPFLT bits are 00, the TAMP_INx pins generate tamper detection events when either a rising edge/high level or a falling edge/low level is observed depending on the corresponding TAMPxTRG bit. The internal pull-up resistors on the TAMP_INx inputs are deactivated when edge detection is selected
	Caution:	When using the edge detection, it is recommended to check by software the tamper pin level just after enabling the tamper detection (by reading the GPIO registers), and before writing sensitive values in the backup registers, to ensure that an active edge did not occur before enabling the tamper event detection. When TAMPFLT = 00 and TAMPxTRG = 0 (rising edge detection), a tamper event may be detected by hardware if the tamper input is already at high level before enabling the tampe detection.
	Caution:	After a tamper event has been detected and cleared, the TAMP_INx should be disabled and then re-enabled (TAMPxE set to 1) before re-programming the backup registers (TAMP_BKPxR). This prevents the application from writing to the backup registers while the TAMP_INx input value still indicates a tamper detection. This is equivalent to a level detection on the TAMP_INx input.
	Note:	Tamper detection is still active when $V_{D D}$ power is switched off. To avoid unwanted resetting of the backup registers, the pin to which the TAMPx is mapped should be externally tied to the correct level.
		Level detection with filtering on tamper inputs (passive mode)
		Level detection with filtering is performed by setting TAMPFLT to a non-zero value. A tampe detection event is generated when either 2, 4, or 8 (depending on TAMPFLT) consecutive samples are observed at the level designated by the TAMPxTRG bit
		The TAMP_INx inputs are precharged through the I/O internal pull-up resistance before its state is sampled, unless disabled by setting TAMPPUDIS to 1 . The duration of the precharge is determined by the TAMPPRCH bits, allowing for larger capacitances on the TAMP_INx inputs.
		The trade-off between tamper detection latency and power consumption through the pull-up can be optimized by using TAMPFREQ to determine the frequency of the sampling for level detection.
Note:		Refer to the datasheet for the electrical characteristics of the pull-up resistors.

36.4 TAMP low-power modes

Table 342. Effect of low-power modes on TAMP

Mode	Description
Sleep	No effect. TAMP interrupts cause the device to exit the Sleep mode
Stop	No effect on all features, except for level detection with filtering mode which remain active only when the clock source is LSE or LSI. Tamper events cause the device to exit the Stop mode.
Standby	No effect on all features, except for level detection with filtering mode which remain active only when the clock source is LSE or LSI.Tamper events cause the device to ex the Standby mode.
Shutdown	No effect on all features, except for level detection with filtering mode which remain active only when the clock source is LSE. Tamper events cause the device to exit the Shutdown mode.

36.5 TAMP interrupts

The interrupt channel is set in the interrupt status register. The interrupt output is also activated.

Table 343. Interrupt requests

Interrupt acronym	Interrupt event	Event flag(1)	Enable control bit(2)	Interrupt clear method	Exit from Sleep mode	Exit from Stop and Standby modes	Exit from Shutdown mode
TAMP	Tamper x(3)	TAMPxF	TAMPxIE	Write 1 in CTAMPxF	Yes	Yes(4)	Yes(5)
TAMP	Internal tamper y(3)	ITAMPyF	ITAMPYIE	Write 1 in CITAMPxF	Yes	Yes(4)	Yes(5)

The event flags are in the TAMP_SR register.

The interrupt masked flags (resulting from event flags AND enable control bits) are in the TAMP_MISR register.

The number of tampers and internal tampers events depend on products.

In case of level detection with filtering passive tamper mode, wakeup from Stop and Standby modes is possible only when the TAMP clock source is LSE or LSI.

In case of level detection with filtering passive tamper mode, wakeup from Shutdown modes is possible only when the TAMP clock source is LSE.

36.6 TAMP registers

Refer to Section 1.2 on page 73 of the reference manual for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by words (32-bit).

36.6.1 TAMP control register 1 (TAMP_CR1)

Address offset: 0x00

Backup domain reset value: 0xFFFF 0000

System reset: not affected

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 Reserved, must be kept at reset value.

Bit 22 Reserved, must be kept at reset value.

Bit 21 ITAMP6E: Internal tamper 6 enable: ST manufacturer readout

0 : Internal tamper 6 disabled.

1: Internal tamper 6 enabled: a tamper is generated in case of ST manufacturer readout.

Bit 20 ITAMP5E: Internal tamper 5 enable: RTC calendar overflow

0 : Internal tamper 5 disabled.

1: Internal tamper 5 enabled: a tamper is generated when the RTC calendar reaches its

maximum value,on the

31^{st}

of December 99,at 23:59:59. The calendar is then frozen and cannot overflow.

Bit 19 ITAMP4E: Internal tamper 4 enable: HSE monitoring

0 : Internal tamper 4 disabled.

1: Internal tamper 4 enabled. a tamper is generated when the HSE frequency is below or

above thresholds.

Bit 18 ITAMP3E: Internal tamper 3 enable: LSE monitoring

0 : Internal tamper 3 disabled.

1: Internal tamper 3 enabled: a tamper is generated when the LSE frequency is below or above thresholds.

Bit 17 Reserved, must be kept at reset value.

Bit 16 Reserved, must be kept at reset value.

Bits 15:3 Reserved, must be kept at reset value.

Bit 2 TAMP3E: Tamper detection on TAMP_IN3 enable(1)

0: Tamper detection on TAMP_IN3 is disabled.

1: Tamper detection on TAMP_IN3 is enabled.

Bit 1 TAMP2E: Tamper detection on TAMP_IN2 enable(1)

0: Tamper detection on TAMP_IN2 is disabled.

1: Tamper detection on TAMP_IN2 is enabled.

Bit 0 TAMP1E: Tamper detection on TAMP_IN1 enable(1)

0: Tamper detection on TAMP_IN1 is disabled.

1: Tamper detection on TAMP_IN1 is enabled.

Tamper detection mode (selected with TAMP_FLTCR register and TAMPxTRG bits in TAMP_CR2), must be configured

before enabling the tamper detection.

36.6.2 TAMP control register 2 (TAMP_CR2)

Address offset: 0x04

Backup domain reset value: 0x00000000

System reset: not affected

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	TAMP3 TRG	TAMP2 TRG	TAMP1 TRG	Res.	Res.	Res.	Res.	Res.	TAMP3 MSK	TAMP2 MSK	TAMP1 MSK
					rw	rw	rw						rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	TAMP3 NOER	TAMP2 NOER	TAMP1 NOER
													rw	rw	rw

Bits 31:27 Reserved, must be kept at reset value.

Bit 26 TAMP3TRG: Active level for tamper 3 input (active mode disabled)

0:If TAMPFLT ≠ 00 Tamper 3 input staying low triggers a tamper detection event.

If TAMPFLT

= 00

Tamper 3 input rising edge and high level triggers a tamper detection event.

1:If TAMPFLT ≠ 00 Tamper 3 input staying high triggers a tamper detection event.

If TAMPFLT = 00 Tamper 3 input falling edge and low level triggers a tamper detection event.

Bit 25 TAMP2TRG: Active level for tamper 2 input (active mode disabled)

0:If TAMPFLT

\neq 00

Tamper 2 input staying low triggers a tamper detection event. If TAMPFLT = 00 Tamper 2 input rising edge and high level triggers a tamper detection event.

1:If TAMPFLT ≠ 00 Tamper 2 input staying high triggers a tamper detection event.

If TAMPFLT

= 00

Tamper 2 input falling edge and low level triggers a tamper detection event.

Bit 24 TAMP1TRG: Active level for tamper 1 input (active mode disabled)

0: If TAMPFLT ≠ 00 Tamper 1 input staying low triggers a tamper detection event.

If TAMPFLT

= 00

Tamper 1 input rising edge and high level triggers a tamper detection event.

1:If TAMPFLT ≠ 00 Tamper 1 input staying high triggers a tamper detection event.

If TAMPFLT

= 00

Tamper 1 input falling edge and low level triggers a tamper detection event.

Bit 23 Reserved, must be kept at reset value.

Bits 22:19 Reserved, must be kept at reset value.

Bit 18 TAMP3MSK: Tamper 3 mask

0: Tamper 3 event generates a trigger event and TAMP3F must be cleared by software to allow next tamper event detection.

1: Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased. The tamper 3 interrupt must not be enabled when TAMP3MSK is set.

Bit 17 TAMP2MSK: Tamper 2 mask

0: Tamper 2 event generates a trigger event and TAMP2F must be cleared by software to allow next tamper event detection.

1: Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased.

The tamper 2 interrupt must not be enabled when TAMP2MSK is set.

Bit 16 TAMP1MSK: Tamper 1 mask

0: Tamper 1 event generates a trigger event and TAMP1F must be cleared by software to allow next tamper event detection.

1: Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware. The backup registers are not erased.

The tamper 1 interrupt must not be enabled when TAMP1MSK is set.

Bits 15:3 Reserved, must be kept at reset value.

Bit 2 TAMP3NOER: Tamper 3 no erase

0 : Tamper 3 event erases the backup registers.

1: Tamper 3 event does not erase the backup registers.

Bit 1 TAMP2NOER: Tamper 2 no erase

0 : Tamper 2 event erases the backup registers.

1: Tamper 2 event does not erase the backup registers.

Bit 0 TAMP1NOER: Tamper 1 no erase

0 : Tamper 1 event erases the backup registers.

1: Tamper 1 event does not erase the backup registers.

36.6.3 TAMP filter control register (TAMP_FLTCR)

Address offset: 0x0C

Backup domain reset value: 0x00000000

System reset: not affected

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 TAMPPUDIS: TAMP_INx pull-up disable

This bit determines if each of the TAMPx pins are precharged before each sample.

0: Precharge TAMP_INx pins before sampling (enable internal pull-up)

1: Disable precharge of TAMP_INx pins.

Bits 6:5 TAMPPRCH[1:0]: TAMP_INx precharge duration

These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the TAMP_INx inputs.

0x0: 1 RTCCLK cycle

0x1: 2 RTCCLK cycles

0x2: 4 RTCCLK cycles

0x3: 8 RTCCLK cycles

Bits 4:3 TAMPFLT[1:0]: TAMP_INx filter count

These bits determines the number of consecutive samples at the specified level

(TAMP*TRG) needed to activate a tamper event. TAMPFLT is valid for each of the TAMP_INx inputs.

0x0: Tamper event is activated on edge of TAMP_INx input transitions to the active level (no internal pull-up on TAMP_INx input).

0x1: Tamper event is activated after 2 consecutive samples at the active level.

0x2: Tamper event is activated after 4 consecutive samples at the active level.

0x3: Tamper event is activated after 8 consecutive samples at the active level.

Bits 2:0 TAMPFREQ[2:0]: Tamper sampling frequency

Determines the frequency at which each of the TAMP_INx inputs are sampled.

0x0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz)

0x1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz)

0x2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz)

0x3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz)

0x4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz)

0x5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz)

0x6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz)

0x7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)

Note: This register concerns only the tamper inputs in passive mode.

36.6.4 TAMP interrupt enable register (TAMP_IER)

Address offset: 0x2C

Backup domain reset value: 0x00000000

System reset: not affected

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	ITAMP6 IE	ITAMP5 IE	ITAMP4 IE	ITAMP3 IE	Res.	Res.
										rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	TAMP 31E	TAMP 21E	TAMP 1IE
													rw	rw	rw

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 Reserved, must be kept at reset value.

Bit 22 Reserved, must be kept at reset value.

Bit 21 ITAMP6IE: Internal tamper 6 interrupt enable: ST manufacturer readout

0: Internal tamper 6 interrupt disabled.

1: Internal tamper 6 interrupt enabled.

Bit 20 ITAMP5IE: Internal tamper 5 interrupt enable: RTC calendar overflow

0 : Internal tamper 5 interrupt disabled.

1: Internal tamper 5 interrupt enabled.

Bit 19 ITAMP4IE: Internal tamper 4 interrupt enable: HSE monitoring

0: Internal tamper 4 interrupt disabled.

1: Internal tamper 4 interrupt enabled.

Bit 18 ITAMP3IE: Internal tamper 3 interrupt enable: LSE monitoring

0 : Internal tamper 3 interrupt disabled.

1: Internal tamper 3 interrupt enabled.

Bit 17 Reserved, must be kept at reset value.

Bit 16 Reserved, must be kept at reset value.

Bits 15:3 Reserved, must be kept at reset value.

Bit 2 TAMP3IE: Tamper 3 interrupt enable

0: Tamper 3 interrupt disabled.

1: Tamper 3 interrupt enabled..

Bit 1 TAMP2IE: Tamper 2 interrupt enable

0: Tamper 2 interrupt disabled.

1: Tamper 2 interrupt enabled.

Bit 0 TAMP1IE: Tamper 1 interrupt enable

0 : Tamper 1 interrupt disabled.

1: Tamper 1 interrupt enabled.

36.6.5 TAMP status register (TAMP_SR)

Address offset: 0x30

Backup domain reset value: 0x00000000

System reset: not affected

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res:	Res.	Res	Res.	Res.	Res.	Res.	Res.	Res.	TAMP 3F	TAMP 2F	TAMP 1F
													r	r	r

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 Reserved, must be kept at reset value.

Bit 22 Reserved, must be kept at reset value.

Bit 21 ITAMP6F: ST manufacturer readout tamper detection flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 6.

Bit 20 ITAMP5F: RTC calendar overflow tamper detection flag

This flag is set by hardware when a tamper detection event is detected on the internal tamper 5.

Bit 19 ITAMP4F: HSE monitoring tamper detection flag

This flag is set by hardware when a tamper detection event is detected on the internal tamper 4.

Bit 18 ITAMP3F: LSE monitoring tamper detection flag

This flag is set by hardware when a tamper detection event is detected on the internal tamper 3.

Bit 17 Reserved, must be kept at reset value.

Bit 16 Reserved, must be kept at reset value.

Bits 15:3 Reserved, must be kept at reset value.

Bit 2 TAMP3F: TAMP3 detection flag

This flag is set by hardware when a tamper detection event is detected on the TAMP3 input.

Bit 1 TAMP2F: TAMP2 detection flag

This flag is set by hardware when a tamper detection event is detected on the TAMP2 input.

Bit 0 TAMP1F: TAMP1 detection flag

This flag is set by hardware when a tamper detection event is detected on the TAMP1 input.

36.6.6 TAMP masked interrupt status register (TAMP_MISR)

Address offset: 0x34

Backup domain reset value: 0x00000000

System reset: not affected

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 Reserved, must be kept at reset value.

Bit 22 Reserved, must be kept at reset value.

Bit 21 ITAMP6MF: ST manufacturer readout tamper interrupt masked flag

This flag is set by hardware when the internal tamper 6 interrupt is raised.

Bit 20 ITAMP5MF: RTC calendar overflow tamper interrupt masked flag

This flag is set by hardware when the internal tamper 5 interrupt is raised.

Bit 19 ITAMP4MF: HSE monitoring tamper interrupt masked flag

This flag is set by hardware when the internal tamper 4 interrupt is raised.

Bit 18 ITAMP3MF: LSE monitoring tamper interrupt masked flag

This flag is set by hardware when the internal tamper 3 interrupt is raised.

Bit 17 Reserved, must be kept at reset value.

Bit 16 Reserved, must be kept at reset value.

Bits 15:3 Reserved, must be kept at reset value.

Bit 2 TAMP3MF: TAMP3 interrupt masked flag

This flag is set by hardware when the tamper 3 interrupt is raised.

Bit 1 TAMP2MF: TAMP2 interrupt masked flag

This flag is set by hardware when the tamper 2 interrupt is raised.

Bit 0 TAMP1MF: TAMP1 interrupt masked flag

This flag is set by hardware when the tamper 1 interrupt is raised.

36.6.7 TAMP status clear register (TAMP_SCR)

Address offset: 0x3C

System reset value: 0x00000000

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 Reserved, must be kept at reset value.

Bit 22 Reserved, must be kept at reset value.

Bit 21 CITAMP6F: Clear ITAMP6 detection flag

Writing 1 in this bit clears the ITAMP6F bit in the TAMP_SR register.

Bit 20 CITAMP5F: Clear ITAMP5 detection flag

Writing 1 in this bit clears the ITAMP5F bit in the TAMP_SR register.

Bit 19 CITAMP4F: Clear ITAMP4 detection flag

Writing 1 in this bit clears the ITAMP4F bit in the TAMP_SR register.

Bit 18 CITAMP3F: Clear ITAMP3 detection flag

Writing 1 in this bit clears the ITAMP3F bit in the TAMP_SR register.

Bit 17 Reserved, must be kept at reset value.

Bit 16 Reserved, must be kept at reset value.

Bits 15:3 Reserved, must be kept at reset value.

Bit 2 CTAMP3F: Clear TAMP3 detection flag

Writing 1 in this bit clears the TAMP3F bit in the TAMP_SR register.

Bit 1 CTAMP2F: Clear TAMP2 detection flag

Writing 1 in this bit clears the TAMP2F bit in the TAMP_SR register.

Bit 0 CTAMP1F: Clear TAMP1 detection flag

Writing 1 in this bit clears the TAMP1F bit in the TAMP_SR register.

36.6.8 TAMP backup x register (TAMP_BKPxR)

Address offset:

0 \times 100 + 0 \times 04 * x, (x = 0 to 31)

Backup domain reset value: 0x00000000 System reset: not affected

BKP[15:0]

Bits 31:0 BKP[31:0]

The application can write or read data to and from these registers.

They are powered-on by

V_{B A T}

when

V_{D D}

is switched off,so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode.

In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled.

36.6.9 TAMP register map Table 344. TAMP register map and reset values

d-
Offset	Register	31	30	23	23	27	26	23	24	23	22	21	20	1.	18	17	1.	16	4	13	12	1	10	9	8	7	6	5	4	3	2	1	O
0x00	TAMP_CR1	串	S	超	SHE	y	STRAND	1,471	REPT	13	BUS	39dWV1I	39dWV1l	3bdWV1l	$\exists \pounds$ dWV1I	SHIP	SHE	S	S	中华	LOU	串串	SHE	3	SHIP	PAR	R.S.	：	SHIP	：	$\exists \pounds$ dWV1	$\exists$ ZdWV1	3ldWV1
0x00	Reset value											1	1	1	1																0	0	0
0x04	TAMP_CR2	E	出生	3	COMPER	路	OVILEdWVI	SYLZAWVL	SYLLAWVL		SK	招聘	1,133	鲜	HSWEdWV1	XSWZdWV1	YSWIdWV1	BUR	g	y	y	g	鲜	g	千港元	新疆	粉色	SHE	3	3	YEONEHWYL	YEONTHWY	YION LAWVL
0x04	Reset value						0	0	0						0	0	0														0	0	0
0x0C	TAMP_FLTCR	时	Let	1,373	Let	SCO	3	时间	LUM	新	3,050	3.3	COND	STRAND	1,000	Let	y	Let	y	3	of	COND	Let	时	Let	SIGNDDINVI	[0:1]HOdddWV1		$[0 : 1] ⊥ 1 \exists d W \lor 1$		[0:2]032,1.1,1.1
0x0C	Reset value																									0	0	0	0	0	0	0	0
0x2C	TAMP_IER	3	3	3,471	POT	好	8	3	5,459	股本	5,459	319dWV1l	$\exists$ ISdWVLI	311.1	318dWVL1		：	POT	到	5,459	3	COND	S	3	POT	STRAND	2,473	1,000	好	43	$\exists I & d W ⊥$	$\exists$ IZdWV1	311dWV1
0x2C	Reset value											0	0	0	0																0	0	0
0x30	TAMP_SR	y	3	33	新	千港元	8	For	：	路	招	19dWV1I	JSdWV1I	JtdWV1I	JEdWVLI	34	：	新华	33	3	a	STRAND	8	股份	3	：3	33	SH	For	：	JEdWV1	JZdWV1	北dWV1
0x30	Reset value											0	0	0	0																0	0	0
0x34	TAMP_MISR	THE	3	Rep	3	1.0	SQUE	BUD	坊	y	5,959	JW9dWV1I	JWSDWVLI	JWTDWVLI	JWEdWV⊥1		SQUE	S	La	SCON	STRIC	Suppose	SHIP	Suppose	1,000	3	(a)	PROM	1.00	中华	JWEdWV1	JWZdWV1	JWLdWV1
0x34	Reset value											0	0	0	0																0	0	0
0x3C	TAMP_SCR	8	3	8	SQUEST	股本	1,373	REPT	部	股本	超	19dWVL10	JSDWVID	北dWV1i0	JEdWVLIO	3	3	BUR	S	REPT	S	8	经营	新鲜	3	3	粉	3	股本	3	JEdWVLO	JITHWIN	HdWV10
0x3C	Reset value											0	0	0	0																0	0	0
0x100 + 0x04*x, (x = 0 to 31)	TAMP_BKPxR	BKP[31:0]
0x100 + 0x04*x, (x = 0 to 31)	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Refer to Section 2.2 on page 81 for the register boundary addresses.

37 Universal synchronous/asynchronous receiver transmitter (USART/UART)

This section describes the universal synchronous asynchronous receiver transmitter (USART).

37.1 USART introduction

The USART offers a flexible means to perform Full-duplex data exchange with external equipments requiring an industry standard NRZ asynchronous serial data format. A very wide range of baud rates can be achieved through a fractional baud rate generator.

The USART supports both synchronous one-way and half-duplex single-wire communications, as well as LIN (local interconnection network), smartcard protocol, IrDA (infrared data association) SIR ENDEC specifications, and modem operations (CTS/RTS). Multiprocessor communications are also supported.

High-speed data communications are possible by using the DMA (direct memory access) for multibuffer configuration.

37.2 USART main features

Full-duplex asynchronous communication

NRZ standard format (mark/space)

Configurable oversampling method by 16 or 8 to achieve the best compromise

between speed and clock tolerance

Baud rate generator systems

Two internal FIFOs for transmit and receive data

Each FIFO can be enabled/disabled by software and come with a status flag.

A common programmable transmit and receive baud rate

Dual clock domain with dedicated kernel clock for peripherals independent from PCLK

Auto baud rate detection

Programmable data word length $(7, 8 or 9 bits)$

Programmable data order with MSB-first or LSB-first shifting

Configurable stop bits (1 or 2 stop bits)

Synchronous master/slave mode and clock output/input for synchronous

communications

SPI slave transmission underrun error flag

Single-wire half-duplex communications

Continuous communications using DMA

Received/transmitted bytes are buffered in reserved SRAM using centralized DMA.

Separate enable bits for transmitter and receiver

Separate signal polarity control for transmission and reception

Swappable Tx/Rx pin configuration

Hardware flow control for modem and RS-485 transceiver

Communication control/error detection flags

Parity control:

Transmits parity bit

Checks parity of received data byte

Interrupt sources with flags

Multiprocessor communications: wake-up from mute mode by idle line detection or address mark detection

Wake-up from Stop mode

37.3 USART extended features

LIN master synchronous break send capability and LIN slave break detection capability

13-bit break generation and 10/11 bit break detection when USART is hardware configured for LIN

IrDA SIR encoder decoder supporting 3/16 bit duration for normal mode

Smartcard mode

Supports the $T = 0$ and $T = 1$ asynchronous protocols for smartcards as defined in the ISO/IEC 7816-3 standard

0.5 and 1.5 stop bits for smartcard operation

Support for Modbus communication

Timeout feature

CR/LF character recognition

37.4 USART implementation

The table(s) below describe(s) USART implementation. It(they) also include(s) LPUART for comparison.

Table 345. USART / LPUART features

USART / LPUART modes/features(1)	USART1/2/3	UART4/5	LPUART1
Hardware flow control for modem	X	X	X
Continuous communication using DMA	X	X	X
Multiprocessor communication	X	X	X
Synchronous mode (Master/Slave)	X	-	-
Smartcard mode	X	-	-
Single-wire half-duplex communication	X	X	X
IrDA SIR ENDEC block	X	X	-
LIN mode	X	X	-
Dual clock domain and wake-up from low-power mode	X	X	X
Receiver timeout interrupt	X	X	-
Modbus communication	X	X	-
Auto baud rate detection	X	X	-
Driver Enable	X	X	X
USART data length	7, 8 and 9 bits
Tx/Rx FIFO	X	X	X
Tx/Rx FIFO size	8

$X =$ supported.

37.5 USART functional description

37.5.1 USART block diagram

Figure 531. USART block diagram

The simplified block diagram given in Figure 531 shows two fully-independent clock domains:

The usart_pclk clock domain

The usart_pclk clock signal feeds the peripheral bus interface. It must be active when accesses to the USART registers are required.

The usart_ker_ck kernel clock domain.

The usart_ker_ck is the USART clock source. It is independent from usart_pclk and delivered by the RCC. The USART registers can consequently be written/read even when the usart_ker_ck clock is stopped.

When the dual clock domain feature is disabled, the usart_ker_ck clock is the same as the usart_pclk clock.

There is no constraint between usart_pclk and usart_ker_ck: usart_ker_ck can be faster or slower than usart_pclk. The only limitation is the software ability to manage the communication fast enough.

When the USART operates in SPI slave mode, it handles data flow using the serial interface clock derived from the external CK signal provided by the external master SPI device. The usart_ker_ck clock must be at least 3 times faster than the clock on the CK input.

37.5.2 USART signals

USART bidirectional communications

USART bidirectional communications require a minimum of two pins: Receive Data In (RX)

and Transmit Data Out (TX):

RX (Receive Data Input)

RX is the serial data input. Oversampling techniques are used for data recovery. They discriminate between valid incoming data and noise.

TX (Transmit Data Output)

When the transmitter is disabled, the output pin returns to its I/O port configuration.

When the transmitter is enabled and no data needs to be transmitted, the TX pin is

High. In single-wire and smartcard modes, this I/O is used to transmit and receive data.

RS232 hardware flow control mode

The following pins are required in RS232 hardware flow control mode:

CTS (Clear To Send)

When driven high, this signal blocks the data transmission at the end of the current transfer.

RTS (Request To Send)

When it is low, this signal indicates that the USART is ready to receive data.

RS485 hardware flow control mode

The following pin is required in RS485 hardware control mode:

DE (Driver Enable)

This signal activates the transmission mode of the external transceiver. Note: DE and RTS share the same pin.

Synchronous master/slave mode and smartcard mode

The following pin is required in synchronous master/slave mode and smartcard mode: - CK

This pin acts as Clock output in synchronous master and smartcard modes.

It acts as Clock input is synchronous slave mode.

In synchronous master mode, this pin outputs the transmitter data clock for synchronous transmission corresponding to SPI master mode (no clock pulses on start bit and stop bit, and a software option to send a clock pulse on the last data bit). In parallel, data can be received synchronously on RX pin. This mechanism can be used to control peripherals featuring shift registers (e.g. LCD drivers). The clock phase and polarity are software programmable.

In smartcard mode, CK output provides the clock to the smartcard.

This pin acts as slave Select input in synchronous slave mode.

Refer to Table 346 and Table 347 for the list of USART input/output pins and internal signals.

Table 346. USART/UART input/output pins

Pin name	Signal type	Description
USART_RX/UART_RX	Input	Serial data receive input
USART_TX/UART_TX	Output	Transmit data output
USART_CTS/UART_CTS	Input	Clear to send
USART_RTS/UART_RTS	Output	Request to send
$USART DE^{(1)} / UART DE^{(2)}$	Output	Driver enable
USART_CK	Output	Clock output in synchronous master and smartcard modes.
USART NSS(3)	Input	Slave select input in synchronous slave mode

USART_DE and USART_RTS share the same pin.

UART_DE and UART_RTS share the same pin.

USART_NSS and USART_CTS share the same pin.

Description of USART input/output signals

Table 347. USART internal input/output signals

Pin name	Signal type	Description
usart_pclk	Input	APB clock
usart_ker_ck	Input	USART kernel clock
usart_wkup	Output	USART provides a wake-up interrupt
usart_it	Output	USART global interrupt
usart_tx_dma	Input/output	USART transmit DMA request
usart_rx_dma	Input/output	USART receive DMA request

37.5.3 USART character description

	The word length can be set to 7, 8 or 9 bits, by programming the M bits (M0: bit 12 and M1: bit 28) in the USART_CR1 register (see Figure 532):
	- 7-bit character length: M[1:0] = '10'
	- 8-bit character length: M[1:0] = '00'
	- 9-bit character length: M[1:0] = '01'
Note:	In 7-bit data length mode, the smartcard mode, LIN master mode and auto baud rate (0x7 and 0x55 frames detection) are not supported.
	By default, the signal (TX or RX) is in low state during the start bit. It is in high state durin the stop bit.
	These values can be inverted, separately for each signal, through polarity configuration control.
	An Idle character is interpreted as an entire frame of "1"s (the number of "1"s includes the number of stop bits).

37.5.4 USART FIFOs and thresholds

The USART can operate in FIFO mode.

The USART comes with a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). The FIFO mode is enabled by setting FIFOEN in USART_CR1 register (bit 29). This mode is supported only in UART, SPI and smartcard modes.

Since the maximum data word length is 9 bits, the TXFIFO is 9-bit wide. However the RXFIFO default width is 12 bits. This is due to the fact that the receiver does not only store the data in the FIFO, but also the error flags associated to each character (Parity error, Noise error and Framing error flags).

Note: The received data is stored in the RXFIFO together with the corresponding flags. However, only the data are read when reading the RDR.

The status flags are available in the USART_ISR register.

It is possible to configure the TXFIFO and RXFIFO levels at which the Tx and RX interrupts are triggered. These thresholds are programmed through RXFTCFG and TXFTCFG bitfields in USART_CR3 control register.

In this case:

The RXFT flag is set in the USART_ISR register and the corresponding interrupt (if enabled) is generated, when the number of received data in the RXFIFO reaches the threshold programmed in the RXFTCFG bits fields.

This means that the RXFIFO is filled until the number of data in the RXFIFO is equal to

RXFTCFG data have been received: one data in USART_RDR and (RXFTCFG - 1) data in the RXFIFO. As an example, when the RXFTCFG is programmed to '101', the RXFT flag is set when a number of data corresponding to the FIFO size has been received (FIFO size -1 data in the RXFIFO and 1 data in the USART_RDR). As a result, the next received data is not set the overrun flag.

The TXFT flag is set in the USART_ISR register and the corresponding interrupt (if enabled) is generated when the number of empty locations in the TXFIFO reaches the threshold programmed in the TXFTCFG bits fields.

This means that the TXFIFO is emptied until the number of empty locations in the TXFIFO is equal to the programmed threshold.

37.5.5 USART transmitter

The transmitter can send data words of either 7 or 8 or 9 bits, depending on the M bit status. The Transmit Enable bit (TE) must be set in order to activate the transmitter function. The data in the transmit shift register is output on the TX pin while the corresponding clock pulses are output on the CK pin.

Character transmission

During an USART transmission, data shifts out the least significant bit first (default configuration) on the TX pin. In this mode, the USART_TDR register consists of a buffer (TDR) between the internal bus and the transmit shift register.

When FIFO mode is enabled, the data written to the transmit data register (USART_TDR) are queued in the TXFIFO.

Every character is preceded by a start bit which corresponds to a low logic level for one bit period. The character is terminated by a configurable number of stop bits.

The number of stop bits can be configured to

0.5, 1, 1.5

or 2 .

Note: The TE bit must be set before writing the data to be transmitted to the USART_TDR.

The TE bit should not be reset during data transmission. Resetting the TE bit during the transmission corrupts the data on the TX pin as the baud rate counters get frozen. The current data being transmitted are then lost.

An idle frame is sent when the TE bit is enabled.

Configurable stop bits

The number of stop bits to be transmitted with every character can be programmed in USART_CR2, bits 13,12.

1 stop bit: This is the default value of number of stop bits.

2 stop bits: This is supported by normal USART, single-wire and modem modes.

1.5 stop bits: To be used in smartcard mode.

An idle frame transmission includes the stop bits.

A break transmission features 10 low bits (when

M [1 : 0] =

’00’) or 11 low bits (when

M [1 : 0] = (01^{'}) or 9 low bits (when M [1 : 0] =^{'} 10^{'})

followed by 2 stop bits (see Figure 533). It is not possible to transmit long breaks (break of length greater than

9 / 10 / 11

low bits).

Figure 533. Configurable stop bits

MSv31887V1

Character transmission procedure

To transmit a character, follow the sequence below:

Program the M bits in USART_CR1 to define the word length.

Select the desired baud rate using the USART_BRR register.

Program the number of stop bits in USART_CR2.

Enable the USART by writing the UE bit in USART_CR1 register to 1.

Select DMA enable (DMAT) in USART_CR3 if multibuffer communication must take place. Configure the DMA register as explained in Section 37.5.19: Continuous communication using USART and DMA.

Set the TE bit in USART_CR1 to send an idle frame as first transmission.

Write the data to send in the USART_TDR register. Repeat this for each data to be transmitted in case of single buffer.

When FIFO mode is disabled, writing a data to the USART_TDR clears the TXE flag.

When FIFO mode is enabled, writing a data to the USART_TDR adds one data to the TXFIFO. Write operations to the USART_TDR are performed when TXFNF flag is set. This flag remains set until the TXFIFO is full.

When the last data is written to the USART_TDR register, wait until TC = 1 .

When FIFO mode is disabled, this indicates that the transmission of the last frame is complete.

When FIFO mode is enabled, this indicates that both TXFIFO and shift register are empty.

This check is required to avoid corrupting the last transmission when the USART is disabled or enters Halt mode.

Single byte communication

When FIFO mode is disabled

Writing to the transmit data register always clears the TXE bit. The TXE flag is set by

hardware. It indicates that:

the data have been moved from the USART_TDR register to the shift register and the data transmission has started;

the USART_TDR register is empty;

the next data can be written to the USART_TDR register without overwriting the previous data.

This flag generates an interrupt if the TXEIE bit is set.

When a transmission is ongoing, a write instruction to the USART_TDR register stores the data in the TDR buffer. It is then copied in the shift register at the end of the current transmission.

When no transmission is ongoing, a write instruction to the USART_TDR register places the data in the shift register, the data transmission starts, and the TXE bit is set.

When FIFO mode is enabled, the TXFNF (TXFIFO not full) flag is set by hardware to indicate that:

the TXFIFO is not full;

the USART_TDR register is empty;

the next data can be written to the USART_TDR register without overwriting the previous data. When a transmission is ongoing, a write operation to the USART_TDR register stores the data in the TXFIFO. Data are copied from the TXFIFO to the shift register at the end of the current transmission.

When the TXFIFO is not full, the TXFNF flag stays at '1' even after a write operation to USART_TDR register. It is cleared when the TXFIFO is full. This flag generates an interrupt if the TXFNFIE bit is set.

Alternatively, interrupts can be generated and data can be written to the FIFO when the TXFIFO threshold is reached. In this case, the CPU can write a block of data defined by the programmed trigger level.

If a frame is transmitted (after the stop bit) and the TXE flag (TXFE in case of FIFO mode) is set, the TC flag goes high. An interrupt is generated if the TCIE bit is set in the USART_CR1 register.

After writing the last data to the USART_TDR register, it is mandatory to wait until TC is set before disabling the USART or causing the device to enter the low-power mode (see Figure 534: TC/TXE behavior when transmitting).

Figure 534. TC/TXE behavior when transmitting

Note: When FIFO management is enabled, the TXFNF flag is used for data transmission.

Break characters

Setting the SBKRQ bit transmits a break character. The break frame length depends on the M bit (see Figure 532).

If a ’ 1 ’ is written to the SBKRQ bit, a break character is sent on the TX line after completing the current character transmission. The SBKF bit is set by the write operation and it is reset by hardware when the break character is completed (during the stop bits after the break character). The USART inserts a logic 1 signal (stop) for the duration of 2 bits at the end of the break frame to guarantee the recognition of the start bit of the next frame.

When the SBKRQ bit is set, the break character is sent at the end of the current transmission.

When FIFO mode is enabled, sending the break character has priority on sending data even if the TXFIFO is full.

Idle characters

Setting the TE bit drives the USART to send an idle frame before the first data frame.

37.5.6 USART receiver

The USART can receive data words of either 7 or 8 or 9 bits depending on the M bits in the USART_CR1 register.

Start bit detection

The start bit detection sequence is the same when oversampling by 16 or by 8 .

In the USART, the start bit is detected when a specific sequence of samples is recognized. This sequence is:

1110 \times 0 \times 0 \times 0 \times 0 \times 0 \times 0

. idle state (no flag is set), where it waits for a falling edge.

Figure 535. Start bit detection when oversampling by 16 or 8

Note: If the sequence is not complete, the start bit detection aborts and the receiver returns to the

The start bit is confirmed (RXNE flag set and interrupt generated if RXNEIE = 1 , or RXFNE flag set and interrupt generated if RXFNEIE = 1 if FIFO mode enabled) if the 3 sampled bits are at ’ 0 ’ (first sampling on the 3rd, 5th and 7th bits finds the 3 bits at ’ 0 ’ and second sampling on the 8th, 9th and 10th bits also finds the 3 bits at ' 0 ').

The start bit is validated but the NE noise flag is set if,

a) for both samplings, 2 out of the 3 sampled bits are at ’ 0 ’ (sampling on the 3rd, 5th and 7th bits and sampling on the 8th, 9th and 10th bits) or

b) for one of the samplings (sampling on the 3rd, 5th and 7th bits or sampling on the 8th, 9th and 10th bits), 2 out of the 3 bits are found at ' 0 '.

If neither of the above conditions are met, the start detection aborts and the receiver returns to the idle state (no flag is set).

Character reception

During an USART reception, data are shifted out least significant bit first (default configuration) through the RX pin.

Character reception procedure

To receive a character, follow the sequence below:

Program the M bits in USART_CR1 to define the word length.

Select the desired baud rate using the baud rate register USART_BRR

Program the number of stop bits in USART_CR2.

Enable the USART by writing the UE bit in USART_CR1 register to '1'.

Select DMA enable (DMAR) in USART_CR3 if multibuffer communication is to take place. Configure the DMA register as explained in Section 37.5.19: Continuous communication using USART and DMA.

Set the RE bit USART_CR1. This enables the receiver which begins searching for a start bit.

When a character is received:

When FIFO mode is disabled, the RXNE bit is set to indicate that the content of the shift register is transferred to the RDR. In other words, data have been received and can be read (as well as their associated error flags).

When FIFO mode is enabled, the RXFNE bit is set to indicate that the RXFIFO is not empty. Reading the USART_RDR returns the oldest data entered in the RXFIFO. When a data is received, it is stored in the RXFIFO together with the corresponding error bits.

An interrupt is generated if the RXNEIE (RXFNEIE when FIFO mode is enabled) bit is set.

The error flags can be set if a frame error, noise, parity or an overrun error was detected during reception.

In multibuffer communication mode:

When FIFO mode is disabled, the RXNE flag is set after every byte reception. It is cleared when the DMA reads the Receive data Register.

When FIFO mode is enabled, the RXFNE flag is set when the RXFIFO is not empty. After every DMA request, a data is retrieved from the RXFIFO. A DMA request is triggered when the RXFIFO is not empty i.e. when there are data to be read from the RXFIFO.

In single buffer mode:

When FIFO mode is disabled, clearing the RXNE flag is done by performing a software read from the USART_RDR register. The RXNE flag can also be cleared by programming RXFRQ bit to ' 1 ' in the USART_RQR register. The RXNE flag must be cleared before the end of the reception of the next character to avoid an overrun error.

When FIFO mode is enabled, the RXFNE is set when the RXFIFO is not empty. After every read operation from USART_RDR, a data is retrieved from the RXFIFO. When the RXFIFO is empty, the RXFNE flag is cleared. The RXFNE flag can also be cleared by programming RXFRQ bit to ' 1' in USART_RQR. When the RXFIFO is full, the first entry in the RXFIFO must be read before the end of the reception of the next character, to avoid an overrun error. The RXFNE flag generates an interrupt if the RXFNEIE bit is set. Alternatively, interrupts can be

generated and data can be read from RXFIFO when the RXFIFO threshold is reached. In this case, the CPU can read a block of data defined by the programmed threshold.

Break character

When a break character is received, the USART handles it as a framing error.

Idle character

When an idle frame is detected, it is handled in the same way as a data character reception except that an interrupt is generated if the IDLEIE bit is set.

Overrun error

FIFO mode disabled

An overrun error occurs if a character is received and RXNE has not been reset.

Data can not be transferred from the shift register to the RDR register until the RXNE bit is cleared. The RXN E flag is set after every byte reception.

An overrun error occurs if RXNE flag is set when the next data is received or the previous DMA request has not been serviced. When an overrun error occurs:

the ORE bit is set;

the RDR content is not lost. The previous data is available by reading the USART_RDR register.

the shift register is overwritten. After that, any data received during overrun is lost.

an interrupt is generated if either the RXNEIE or the EIE bit is set.

FIFO mode enabled

An overrun error occurs when the shift register is ready to be transferred and the receive FIFO is full.

Data can not be transferred from the shift register to the USART_RDR register until there is one free location in the RXFIFO. The RXFNE flag is set when the RXFIFO is not empty.

An overrun error occurs if the RXFIFO is full and the shift register is ready to be transferred. When an overrun error occurs:

The ORE bit is set.

The first entry in the RXFIFO is not lost. It is available by reading the

USART_RDR register.

The shift register is overwritten. After that point, any data received during overrun is lost.

An interrupt is generated if either the RXFNEIE or EIE bit is set.

The ORE bit is reset by setting the ORECF bit in the USART_ICR register.

Note: The ORE bit, when set, indicates that at least 1 data has been lost.

When the FIFO mode is disabled, there are two possibilities

if $R X N E = 1$ ,then the last valid data is stored in the receive register (RDR) and can be read,

if $R X N E = 0$ ,the last valid data has already been read and there is nothing left to be read in the RDR register. This case can occur when the last valid data is read in the RDR register at the same time as the new (and lost) data is received.

Selecting the clock source and the appropriate oversampling method

The choice of the clock source is done through the Clock Control system (see Section Reset and clock control (RCC)). The clock source must be selected through the UE bit before enabling the USART.

The clock source must be selected according to two criteria:

Possible use of the USART in low-power mode

Communication speed.

The clock source frequency is usart_ker_ck.

When the dual clock domain and the wake-up from low-power mode features are supported, the usart_ker_ck clock source can be configurable in the RCC (see Section Reset and clock control

(\bar{R} C C)

). Otherwise the usart_ker_ck clock is the same as usart_pclk.

The usart_ker_ck clock can be divided by a programmable factor, defined in the USART_PRESC register.

Figure 536. usart_ker_ck clock divider block diagram

Some usart_ker_ck sources enable the USART to receive data while the MCU is in low-power mode. Depending on the received data and wake-up mode selected, the USART wakes up the MCU, when needed, in order to transfer the received data, by performing a software read to the USART_RDR register or by DMA.

For the other clock sources, the system must be active to enable USART communications.

The communication speed range (specially the maximum communication speed) is also determined by the clock source.

The receiver implements different user-configurable oversampling techniques (except in synchronous mode) for data recovery by discriminating between valid incoming data and noise. This enables obtaining the best a trade-off between the maximum communication speed and noise/clock inaccuracy immunity.

The oversampling method can be selected by programming the OVER8 bit in the USART_CR1 register either to 16 or 8 times the baud rate clock (see Figure 537 and Figure 538).

Depending on your application:

select oversampling by $8 (OVER 8 = 1)$ to achieve higher speed (up to usart_ker_ck_pres/8). In this case the maximum receiver tolerance to clock deviation is reduced (refer to Section 37.5.8: Tolerance of the USART receiver to clock deviation on page 1627)

select oversampling by $16 (OVER 8 = 0)$ to increase the tolerance of the receiver to clock deviations. In this case, the maximum speed is limited to maximum usart_ker_ck_pres/16 (where usart_ker_ck_pres is the USART input clock divided by a prescaler).

Programming the ONEBIT bit in the USART_CR3 register selects the method used to evaluate the logic level. Two options are available:

The majority vote of the three samples in the center of the received bit. In this case, when the 3 samples used for the majority vote are not equal, the NE bit is set.

A single sample in the center of the received bit

Depending on your application:

select the three sample majority vote method (ONEBIT = 0) when operating in a noisy environment and reject the data when a noise is detected (refer to Figure 348) because this indicates that a glitch occurred during the sampling.

select the single sample method (ONEBIT = 1) when the line is noise-free to increase the receiver tolerance to clock deviations (see Section 37.5.8: Tolerance of the USART receiver to clock deviation on page 1627). In this case the NE bit is never set.

When noise is detected in a frame:

The NE bit is set at the rising edge of the RXNE bit (RXFNE in case of FIFO mode enabled).

The invalid data is transferred from the Shift register to the USART_RDR register.

No interrupt is generated in case of single byte communication. However this bit rises at the same time as the RXNE bit (RXFNE in case of FIFO mode enabled) which itself generates an interrupt. In case of multibuffer communication an interrupt is issued if the EIE bit is set in the USART_CR3 register.

The NE bit is reset by setting NECF bit in USART_ICR register.

Note: Noise error is not supported in SPI mode.

Oversampling by 8 is not available in the smartcard, IrDA and LIN modes. In those modes, the OVER8 bit is forced to ' 0 ' by hardware.

Figure 537. Data sampling when oversampling by 16

MSv31152V1

Figure 538. Data sampling when oversampling by 8

Table 348. Noise detection from sampled data

Sampled value	NE status	Received bit value
000	0	0
001	1	0
010	1	0
011	1	1
100	1	0
101	1	1
110	1	1
111	0	1

Framing error

A framing error is detected when the stop bit is not recognized on reception at the expected time, following either a de-synchronization or excessive noise.

When the framing error is detected:

the FE bit is set by hardware;

the invalid data is transferred from the Shift register to the USART_RDR register (RXFIFO in case FIFO mode is enabled).

no interrupt is generated in case of single byte communication. However this bit rises at the same time as the RXNE bit (RXFNE in case FIFO mode is enabled) which itself generates an interrupt. In case of multibuffer communication an interrupt is issued if the EIE bit is set in the USART_CR3 register.

The FE bit is reset by writing ’ 1’ to the FECF in the USART_ICR register.

Framing error is not supported in SPI mode.

Configurable stop bits during reception

The number of stop bits to be received can be configured through the control bits of USART_CR: it can be either 1 or 2 in normal mode and 0.5 or 1.5 in smartcard mode.

0.5 stop bit (reception in smartcard mode): no sampling is done for 0.5 stop bit. As a consequence, no framing error and no break frame can be detected when 0.5 stop bit is selected.

1 stop bit: sampling for 1 stop bit is done on the 8th, 9th and 10th samples.

1.5 stop bits (smartcard mode)

When transmitting in smartcard mode, the device must check that the data are correctly sent. The receiver block must consequently be enabled

(RE = 1

in USART_CR1) and the stop bit is checked to test if the smartcard has detected a parity error.

In the event of a parity error, the smartcard forces the data signal low during the sampling (NACK signal), which is flagged as a framing error. The FE flag is then set through RXNE flag (RXFNE if the FIFO mode is enabled) at the end of the 1.5 stop bit. Sampling for 1.5 stop bits is done on the 16th, 17th and 18th samples (1 baud clock period after the beginning of the stop bit). The 1.5 stop bit can be broken into 2 parts: one 0.5 baud clock period during which nothing happens, followed by 1 normal stop bit period during which sampling occurs halfway through (refer to Section 37.5.16: USART receiver timeout on page 1641 for more details).

2 stop bits

Sampling for 2 stop bits is done on the 8th, 9th and 10th samples of the first stop bit. The framing error flag is set if a framing error is detected during the first stop bit.

The second stop bit is not checked for framing error. The RXNE flag (RXFNE if the FIFO mode is enabled) is set at the end of the first stop bit.

37.5.7 USART baud rate generation

The baud rate for the receiver and transmitter (Rx and Tx) are both set to the value programmed in the USART_BRR register.

Equation 1: baud rate for standard USART (SPI mode included) (OVER8 = '0' or '1') In case of oversampling by 16 , the baud rate is given by the following formula:

Tx / Rx baud = \frac{usart_ker_ckpres}{USARTDIV}

In case of oversampling by 8 , the baud rate is given by the following formula:

Tx / Rx baud = \frac{2 \times usart_ker_ckpres}{USARTDIV}

Equation 2: baud rate in smartcard, LIN and IrDA modes (OVER8 = 0)

The baud rate is given by the following formula:

Tx/Rx baud = \frac{usart_ker_ckpres}{USARTDIV}

USARTDIV is an unsigned fixed point number that is coded on the USART_BRR register.

When OVER8 = 0, BRR = USARTDIV.

When OVER8 = 1

BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right.

BRR[3] must be kept cleared.

BRR[15:4] = USARTDIV[15:4]

Note: The baud counters are updated to the new value in the baud registers after a write operation to USART_BRR. Hence the baud rate register value should not be changed during communication.

In case of oversampling by 16 and 8, USARTDIV must be greater than or equal to 16.

How to derive USARTDIV from USART_BRR register values

Example 1

To obtain 9600 baud with usart_ker_ck_pres = 8 MHz:

In case of oversampling by 16:

USARTDIV

= 8000000 / 9600

BRR = USARTDIV = 0d833 = 0x0341

In case of oversampling by 8 :

USARTDIV = 2 * 8 000 000/9600

USARTDIV

= 1666, 66 (0 d 1667 = 0 x 683)

BRR

[3 : 0] = 0 \times 3 >> 1 = 0 \times 1

BRR = 0x681

Example 2

To obtain 921.6 Kbaud with usart_ker_ck_pres = 48 MHz:

In case of oversampling by 16:

USARTDIV = 48 000 000/921 600

BRR = USARTDIV = 0d52 = 0x34

In case of oversampling by 8 :

USARTDIV

= 2 * 48000000 / 921600

USARTDIV

= 104 (0 d 104 = 0 x 68)

BRR [3 : 0] = USARTDIV [3 : 0] >> 1 = 0 x 8 >> 1 = 0 x 4

BRR

= 0 \times 64

37.5.8 Tolerance of the USART receiver to clock deviation

The USART asynchronous receiver operates correctly only if the total clock system deviation is less than the tolerance of the USART receiver.

The causes which contribute to the total deviation are:

DTRA: deviation due to the transmitter error (which also includes the deviation of the transmitter's local oscillator)

DQUANT: error due to the baud rate quantization of the receiver

DREC: deviation of the receiver local oscillator

DTCL: deviation due to the transmission line (generally due to the transceivers which can introduce an asymmetry between the low-to-high transition timing and the high-to-low transition timing)

DTRA + DQUANT + DREC + DTCL + DWU < USART receiver tolerance

where

DWU is the error due to sampling point deviation when the wake-up from low-

power mode is used.

when

M [1 : 0] = 01

DWU = \frac{t_{WUUSART}}{11 \times Tbit}

when

M [1 : 0] = 00

DWU = \frac{t_{WUUSART}}{10 \times Tbit}

when

M [1 : 0] = 10

DWU = \frac{t_{WUUSART}}{9 \times Tbit}

t_{WUUSART}

is the time between the detection of the start bit falling edge and the instant when the clock (requested by the peripheral) is ready and reaching the peripheral, and the regulator is ready.

The USART receiver can receive data correctly at up to the maximum tolerated deviation specified in Table 349, Table 350, depending on the following settings:

9-, 10- or 11-bit character length defined by the M bits in the USART_CR1 register

Oversampling by 8 or 16 defined by the OVER8 bit in the USART_CR1 register

Bits BRR[3:0] of USART_BRR register are equal to or different from 0000.

Use of 1 bit or 3 bits to sample the data, depending on the value of the ONEBIT bit in the USART_CR3 register.

Table 349. Tolerance of the USART receiver when BRR [3:0] = 0000

M bits	OVER8 bit = 0		OVER8 bit = 1
M bits	ONEBIT = 0	ONEBIT = 1	ONEBIT = 0	ONEBIT = 1
00	3.75%	4.375%	2.50%	3.75%
01	3.41%	3.97%	2.27%	3.41%
10	4.16%	4.86%	2.77%	4.16%

Table 350. Tolerance of the USART receiver when BRR[3:0] is different from 0000

M bits	OVER8 bit = 0		OVER8 bit = 1
M bits	ONEBIT = 0	ONEBIT = 1	ONEBIT = 0	ONEBIT = 1
00	3.33%	3.88%	2%	3%
01	3.03%	3.53%	1.82%	2.73%
10	3.7%	4.31%	2.22%	3.33%

Note: The data specified in Table 349 and Table 350 may slightly differ in the special case when the received frames contain some Idle frames of exactly 10-bit times when

M

bits

= 00 (11 -

bit times when

M = 01

or 9- bit times when

M = 10

37.5.9 USART auto baud rate detection

The USART can detect and automatically set the USART_BRR register value based on the reception of one character. Automatic baud rate detection is useful under two circumstances:

The communication speed of the system is not known in advance.

The system is using a relatively low accuracy clock source and this mechanism enables the correct baud rate to be obtained without measuring the clock deviation.

The clock source frequency must be compatible with the expected communication speed.

When oversampling by 16, the baud rate ranges from usart_ker_ck_pres/65535 and usart_ker_ck_pres/16.

When oversampling by 8, the baud rate ranges from usart_ker_ck_pres/65535 and usart_ker_ck_pres/8.

Before activating the auto baud rate detection, the auto baud rate detection mode must be selected through the ABRMOD[1:0] field in the USART_CR2 register. There are four modes based on different character patterns. In these auto baud rate modes, the baud rate is measured several times during the synchronization data reception and each measurement is compared to the previous one.

These modes are the following:

Mode 0: Any character starting with a bit at '1'.

In this case the USART measures the duration of the start bit (falling edge to rising edge).

Mode 1: Any character starting with a 10xx bit pattern.

In this case, the USART measures the duration of the Start and of the 1st data bit. The measurement is done falling edge to falling edge, to ensure a better accuracy in the case of slow signal slopes.

Mode 2: A 0x7F character frame (it may be a 0x7F character in LSB first mode or a 0xFE in MSB first mode).

In this case, the baud rate is updated first at the end of the start bit (BRs), then at the end of bit 6 (based on the measurement done from falling edge to falling edge: BR6). Bit0 to bit6 are sampled at BRs while further bits of the character are sampled at BR6.

Mode 3: A 0x55 character frame.

In this case, the baud rate is updated first at the end of the start bit (BRs), then at the end of bit0 (based on the measurement done from falling edge to falling edge: BR0), and finally at the end of bit

6

(BR6). Bit 0 is sampled at BRs,bit 1 to bit 6 are sampled at BR0, and further bits of the character are sampled at BR6. In parallel, another check is performed for each intermediate RX line transition. An error is generated if the transitions on RX are not sufficiently synchronized with the receiver (the receiver being based on the baud rate calculated on bit 0 ).

Prior to activating the auto baud rate detection, the USART_BRR register must be initialized by writing a non-zero baud rate value.

The automatic baud rate detection is activated by setting the ABREN bit in the USART_CR2 register. The USART then waits for the first character on the RX line. The auto baud rate operation completion is indicated by the setting of the ABRF flag in the USART_ISR register. If the line is noisy, the correct baud rate detection cannot be guaranteed. In this case the BRR value may be corrupted and the ABRE error flag is set. This also happens if the communication speed is not compatible with the automatic baud rate detection range (bit duration not between 16 and 65536 clock periods (oversampling by 16) and not between 8 and 65536 clock periods (oversampling by 8)).

The auto baud rate detection can be re-launched later by resetting the ABRF flag (by writing a '0').

When FIFO management is disabled and an auto baud rate error occurs, the ABRE flag is set through RXNE and FE bits.

When FIFO management is enabled and an auto baud rate error occurs, the ABRE flag is set through RXFNE and FE bits.

If the FIFO mode is enabled, the auto baud rate detection should be made using the data on the first RXFIFO location. So, prior to launching the auto baud rate detection, make sure that the RXFIFO is empty by checking the RXFNE flag in USART_ISR register.

Note: The BRR value might be corrupted if the USART is disabled (UE = 0) during an auto baud rate operation.

37.5.10 USART multiprocessor communication

It is possible to perform USART multiprocessor communications (with several USARTs connected in a network). For instance one of the USARTs can be the master with its TX output connected to the RX inputs of the other USARTs, while the others are slaves with their respective TX outputs logically ANDed together and connected to the RX input of the master.

In multiprocessor configurations, it is often desirable that only the intended message recipient actively receives the full message contents, thus reducing redundant USART service overhead for all non addressed receivers.

The non-addressed devices can be placed in mute mode by means of the muting function. To use the mute mode feature, the MME bit must be set in the USART_CR1 register.

Note: When FIFO management is enabled and MME is already set, MME bit must not be cleared and then set again quickly (within two usart_ker_ck cycles), otherwise mute mode might remain active.

When the mute mode is enabled:

the RWU bit in USART_ISR register is set to '1'. RWU can be controlled automatically by hardware or by software, through the MMRQ bit in the USART_RQR register, under certain conditions.

The USART can enter or exit from mute mode using one of two methods, depending on the

Idle line detection (WAKE = 0)

The USART enters mute mode when the MMRQ bit is written to ' 1 ' and the RWU is automatically set.

The USART wakes up when an Idle frame is detected. The RWU bit is then cleared by hardware but the IDLE bit is not set in the USART_ISR register. An example of mute mode behavior using Idle line detection is given in Figure 539.

Figure 539. Mute mode using Idle line detection

	RX Data 3 Data 4 RWU MMRQ written to 1 MSv31154V1
Note:	If the MMRQ is set while the IDLE character has already elapsed, mute mode is not entered. (RWU is not set). If the USART is activated while the line is IDLE, the idle state is detected after the duration of one IDLE frame (not only after the reception of one character frame 4-bit/7-bit address mark detection (WAKE = 1) In this mode, bytes are recognized as addresses if their MSB is a ‘1’, otherwise they are considered as data. In an address byte, the address of the targeted receiver is put in the or 7 LSBs. The choice of 7 or 4 bit address detection is done using the ADDM7 bit. This 4- bit/7-bit word is compared by the receiver with its own address which is programmed in the ADD bits in the USART_CR2 register In 7-bit and 9-bit data modes, address detection is done on 6-bit and 8-bit addresses (ADD[5:0] and ADD[7:0]) respectively.

Note:
	The USART enters mute mode when an address character is received which does not match its programmed address. In this case, the RWU bit is set by hardware. The RXNE flag is not set for this address byte and no interrupt or DMA request is issued when the USART enters mute mode. When FIFO management is enabled, the software should ensure that there is at least one empty location in the RXFIFO before entering mute mode
	The USART also enters mute mode when the MMRQ bit is written to 1. The RWU bit is also automatically set in this case.
	The USART exits from mute mode when an address character is received which matches the programmed address. Then the RWU bit is cleared and subsequent bytes are received normally. The RXNE/RXFNE bit is set for the address character since the RWU bit has been cleared.
Note:	When FIFO management is enabled, when MMRQ is set while the receiver is sampling last bit of a data, this data may be received before effectively entering in mute mode
	An example of mute mode behavior using address mark detection is given in Figure 540

Figure 540. Mute mode using address mark detection

37.5.11 USART Modbus communication

The USART offers basic support for the implementation of Modbus/RTU and Modbus/ASCII protocols. Modbus/RTU is a half-duplex, block-transfer protocol. The control part of the protocol (address recognition, block integrity control and command interpretation) must be implemented in software.

The USART offers basic support for the end of the block detection, without software overhead or other resources.

Modbus/RTU

In this mode, the end of one block is recognized by a "silence" (idle line) for more than 2 character times. This function is implemented through the programmable timeout function.

The timeout function and interrupt must be activated, through the RTOEN bit in the USART_CR2 register and the RTOIE in the USART_CR1 register. The value corresponding to a timeout of 2 character times (for example

22 \times

bit time) must be programmed in the RTO register. When the receive line is idle for this duration, after the last stop bit is received, an interrupt is generated, informing the software that the current block reception is completed.

Modbus/ASCII

In this mode, the end of a block is recognized by a specific (CR/LF) character sequence. The USART manages this mechanism using the character match function.

By programming the LF ASCII code in the ADD[7:0] field and by activating the character match interrupt (CMIE

= 1

),the software is informed when a LF has been received and can check the CR/LF in the DMA buffer.

37.5.12 USART parity control

Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the USART_CR1 register. Depending on the frame length defined by the

M

bits,the possible USART frame formats are as listed in Table 351.

Table 351. USART frame formats

M bits	PCE bit	USART frame(1)
00	0	\| SB \| 8 bit data \| STB \|
00	1	\| SB \| 7-bit data \| PB \| STB \|
01	0	\| SB \| 9-bit data \| STB \|
01	1	\| SB \| 8-bit data PB \| STB \|
10	0	\| SB \| 7bit data \| STB \|
10	1	\| SB \| 6-bit data \| PB \| STB \|

Legends: SB: start bit, STB: stop bit, PB: parity bit. In the data register, the PB is always taking the MSB position (8th or 7th, depending on the M bit value).

Even parity

The parity bit is calculated to obtain an even number of "1s" inside the frame of the 6,7 or 8 LSB bits (depending on M bit values) and the parity bit.

As an example, if data

= 00110101

and 4 bits are set,the parity bit is equal to 0 if even parity is selected (PS bit in USART_CR1 = 0).

Odd parity

The parity bit is calculated to obtain an odd number of "1s" inside the frame made of the 6,7 or 8 LSB bits (depending on M bit values) and the parity bit.

As an example, if data

= 00110101

and 4 bits set,then the parity bit is equal to 1 if odd parity is selected (PS bit in USART_CR1 = 1).

Parity checking in reception

If the parity check fails, the PE flag is set in the USART_ISR register and an interrupt is generated if PEIE is set in the USART_CR1 register. The PE flag is cleared by software writing 1 to the PECF in the USART_ICR register.

Parity generation in transmission

If the PCE bit is set in USART_CR1, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit (even number of "1s" if even parity is selected

(P S = 0)

or an odd number of "1s" if odd parity is selected

(P S = 1)

37.5.13 USART LIN (local interconnection network) mode

This section is relevant only when LIN mode is supported. Refer to Section 37.4: USART implementation on page 1610.

The LIN mode is selected by setting the LINEN bit in the USART_CR2 register. In LIN mode, the following bits must be kept cleared:

STOP[1:0] and CLKEN in the USART_CR2 register,

SCEN, HDSEL and IREN in the USART_CR3 register.

LIN transmission

The procedure described in Section 37.5.4 has to be applied for LIN master transmission. It must be the same as for normal USART transmission with the following differences:

Clear the M bit to configure 8-bit word length.

Set the LINEN bit to enter LIN mode. In this case, setting the SBKRQ bit sends 13 '0 bits as a break character. Then two bits of value '1 are sent to enable the next start detection.

LIN reception

When LIN mode is enabled, the break detection circuit is activated. The detection is totally independent from the normal USART receiver. A break can be detected whenever it occurs, during Idle state or during a frame.

When the receiver is enabled (RE = 1 in USART_CR1), the circuit looks at the RX input for a start signal. The method for detecting start bits is the same when searching break characters or data. After a start bit has been detected, the circuit samples the next bits exactly like for the data (on the 8th,9th and 10th samples). If 10 (when the LBDL = 0 in USART_CR2) or 11 (when LBDL = 1 in USART_CR2) consecutive bits are detected as ' 0, and are followed by a delimiter character, the LBDF flag is set in USART_ISR. If the LBDIE bit

= 1

,an interrupt is generated. Before validating the break,the delimiter is checked for as it signifies that the RX line has returned to a high level.

If a ' 1 is sampled before the 10 or 11 have occurred, the break detection circuit cancels the current detection and searches for a start bit again.

If the LIN mode is disabled (LINEN = 0), the receiver continues working as normal USART, without taking into account the break detection.

If the LIN mode is enabled (LINEN = 1), as soon as a framing error occurs (i.e. stop bit detected at ' 0 , which is the case for any break frame), the receiver stops until the break detection circuit receives either a '1 , if the break word was not complete, or a delimiter character if a break has been detected.

The behavior of the break detector state machine and the break flag is shown on the Figure 541: Break detection in LIN mode (11-bit break length - LBDL bit is set) on page 1636.

Examples of break frames are given on Figure 542: Break detection in LIN mode vs.

Framing error detection on page 1637.

Figure 542. Break detection in LIN mode vs. Framing error detection

37.5.14 USART synchronous mode

Master mode

The synchronous master mode is selected by programming the CLKEN bit in the

USART_CR2 register to '1'. In synchronous mode, the following bits must be kept cleared:

LINEN bit in the USART_CR2 register,

SCEN, HDSEL and IREN bits in the USART_CR3 register.

In this mode, the USART can be used to control bidirectional synchronous serial

communications in master mode. The CK pin is the output of the USART transmitter clock. No clock pulses are sent to the CK pin during start bit and stop bit. Depending on the state of the LBCL bit in the USART_CR2 register, clock pulses are, or are not, generated during the last valid data bit (address mark). The CPOL bit in the USART_CR2 register is used to select the clock polarity, and the CPHA bit in the USART_CR2 register is used to select the phase of the external clock (see Figure 543, Figure 544 and Figure 545).

During the Idle state, preamble and send break, the external CK clock is not activated.

In synchronous master mode, the USART transmitter operates exactly like in asynchronous mode. However, since CK is synchronized with TX (according to CPOL and CPHA), the data on TX is synchronous.

In synchronous master mode, the USART receiver operates in a different way compared to asynchronous mode. If RE is set to 1 , the data are sampled on CK (rising or falling edge, depending on CPOL and CPHA), without any oversampling. A given setup and a hold time must be respected (which depends on the baud rate:

1 / 16

bit time).

Figure 545. USART data clock timing diagram in synchronous master mode (M bits = 01)

Slave mode

The synchronous slave mode is selected by programming the SLVEN bit in the

USART_CR2 register to '1'. In synchronous slave mode, the following bits must be kept cleared:

LINEN and CLKEN bits in the USART_CR2 register,

SCEN, HDSEL and IREN bits in the USART_CR3 register.

In this mode, the USART can be used to control bidirectional synchronous serial communications in slave mode. The CK pin is the input of the USART in slave mode.

Note: When the peripheral is used in SPI slave mode, the frequency of peripheral clock source (usart_ker_ck_pres) must be greater than 3 times the CK input frequency.

The CPOL bit and the CPHA bit in the USART_CR2 register are used to select the clock polarity and the phase of the external clock, respectively (see Figure 546).

An underrun error flag is available in slave transmission mode. This flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value to USART_TDR.

The slave supports the hardware and software NSS management.

Figure 546. USART data clock timing diagram in synchronous slave mode (M bits

= 00

)

Slave select (NSS) pin management

The hardware or software slave select management can be set through the DIS_NSS bit in the USART_CR2 register:

Software NSS management (DIS_NSS = 1)

The SPI slave is always selected and NSS input pin is ignored.

The external NSS pin remains free for other application uses.

Hardware NSS management (DIS_NSS = 0)

The SPI slave selection depends on NSS input pin. The slave is selected when NSS is low and deselected when NSS is high.

Note: The LBCL (used only on SPI master mode), CPOL and CPHA bits have to be selected when the USART is disabled

(U E = 0)

to ensure that the clock pulses function correctly.

In SPI slave mode, the USART must be enabled before starting the master communications (or between frames while the clock is stable). Otherwise, if the USART slave is enabled while the master is in the middle of a frame, it becomes desynchronized with the master. The data register of the slave needs to be ready before the first edge of the communication clock or before the end of the ongoing communication, otherwise the SPI slave transmits zeros.

SPI slave underrun error

When an underrun error occurs, the UDR flag is set in the USART_ISR register, and the SPI slave goes on sending the last data until the underrrun error flag is cleared by software.

The underrun flag is set at the beginning of the frame. An underrun error interrupt is triggered if EIE bit is set in the USART_CR3 register.

The underrun error flag is cleared by setting bit UDRCF in the USART_ICR register.

In case of underrun error, it is still possible to write to the TDR register. Clearing the underrun error enables sending new data.

If an underrun error occurred and there is no new data written in TDR, then the TC flag is set at the end of the frame.

Note: An underrun error may occur if the moment the data is written to the USART_TDR is too close to the first CK transmission edge. To avoid this underrun error, the USART_TDR should be written 3 usart_ker_ck cycles before the first CK edge.

37.5.15 USART single-wire half-duplex communication

Single-wire half-duplex mode is selected by setting the HDSEL bit in the USART_CR3 register. In this mode, the following bits must be kept cleared:

LINEN and CLKEN bits in the USART_CR2 register,

SCEN and IREN bits in the USART_CR3 register.

The USART can be configured to follow a single-wire half-duplex protocol where the TX and RX lines are internally connected. The selection between half- and Full-duplex communication is made with a control bit HDSEL in USART_CR3.

As soon as HDSEL is written to '1':

The TX and RX lines are internally connected.

The RX pin is no longer used.

The TX pin is always released when no data is transmitted. Thus, it acts as a standard I/O in idle or in reception. It means that the I/O must be configured so that TX is configured as alternate function open-drain with an external pull-up.

Apart from this, the communication protocol is similar to normal USART mode. Any conflict on the line must be managed by software (for instance by using a centralized arbiter). In particular, the transmission is never blocked by hardware and continues as soon as data are written in the data register while the TE bit is set.

37.5.16 USART receiver timeout

The receiver timeout feature is enabled by setting the RTOEN bit in the USART_CR2 control register.

The timeout duration is programmed using the RTO bitfields in the USART_RTOR register.

The receiver timeout counter starts counting:

from the end of the stop bit if $STOP =$ ’00’ or $STOP =$ ’11’

from the end of the second stop bit if $STOP =$ ’ ’ 10 ’.

from the beginning of the stop bit if $STOP =^{1} 01^{'}$ .

When the timeout duration has elapsed, the RTOF flag in the USART_ISR register is set. A timeout is generated if RTOIE bit in USART_CR1 register is set.

37.5.17 USART smartcard mode

This section is relevant only when smartcard mode is supported. Refer to Section 37.4: USART implementation on page 1610.

Smartcard mode is selected by setting the SCEN bit in the USART_CR3 register. In smartcard mode, the following bits must be kept cleared:

LINEN bit in the USART_CR2 register,

HDSEL and IREN bits in the USART_CR3 register.

The CLKEN bit can also be set to provide a clock to the smartcard.

The smartcard interface is designed to support asynchronous smartcard protocol as defined in the ISO 7816-3 standard. Both

T = 0

(character mode) and

T = 1

(block mode) are supported.

The USART should be configured as:

8 bits plus parity: $M = 1$ and $PCE = 1$ in the USART_CR1 register

1.5 stop bits when transmitting and receiving data: STOP = '11' in the USART_CR2 register. It is also possible to choose 0.5 stop bit for reception.

T = 0

(character) mode,the parity error is indicated at the end of each character during the guard time period.

Figure 547 shows examples of what can be seen on the data line with and without parity error.

Figure 547. ISO 7816-3 asynchronous protocol

When connected to a smartcard, the TX output of the USART drives a bidirectional line that is also driven by the smartcard. The TX pin must be configured as open drain.

Smartcard mode implements a single wire half duplex communication protocol.

Transmission of data from the transmit shift register is guaranteed to be delayed by a minimum of $1 / 2$ baud clock. In normal operation a full transmit shift register starts shifting on the next baud clock edge. In smartcard mode this transmission is further delayed by a guaranteed $1 / 2$ baud clock.

In transmission, if the smartcard detects a parity error, it signals this condition to the USART by driving the line low (NACK). This NACK signal (pulling transmit line low for 1 baud clock) causes a framing error on the transmitter side (configured with 1.5 stop bits). The USART can handle automatic re-sending of data according to the protocol. The number of retries is programmed in the SCARCNT bitfield. If the USART continues receiving the NACK after the programmed number of retries, it stops transmitting and signals the error as a framing error. The TXE bit (TXFNF bit in case FIFO mode is enabled) may be set using the TXFRQ bit in the USART_RQR register.

Smartcard auto-retry in transmission: A delay of 2.5 baud periods is inserted between the NACK detection by the USART and the start bit of the repeated character. The TC bit is set immediately at the end of reception of the last repeated character (no guardtime). If the software wants to repeat it again, it must insure the minimum 2 baud periods required by the standard.

If a parity error is detected during reception of a frame programmed with a 1.5 stop bit period, the transmit line is pulled low for a baud clock period after the completion of the receive frame. This is to indicate to the smartcard that the data transmitted to the USART has not been correctly received. A parity error is NACKed by the receiver if the NACK control bit is set,otherwise a NACK is not transmitted (to be used in $T = 1$ mode). If the received character is erroneous, the RXNE (RXFNE in case FIFO mode is enabled)/receive DMA request is not activated. According to the protocol specification, the smartcard must resend the same character. If the received character is still erroneous after the maximum number of retries specified in the SCARCNT bitfield, the USART stops transmitting the NACK and signals the error as a parity error.

Smartcard auto-retry in reception: the BUSY flag remains set if the USART NACKs the card but the card doesn't repeat the character.

In transmission, the USART inserts the Guard Time (as programmed in the Guard Time register) between two successive characters. As the Guard Time is measured after the stop bit of the previous character, the GT[7:0] register must be programmed to the desired CGT (Character Guard Time, as defined by the 7816-3 specification) minus 12 (the duration of one character).

The assertion of the TC flag can be delayed by programming the Guard Time register. In normal operation, TC is asserted when the transmit shift register is empty and no further transmit requests are outstanding. In smartcard mode an empty transmit shift register triggers the Guard Time counter to count up to the programmed value in the Guard Time register. TC is forced low during this time. When the Guard Time counter reaches the programmed value TC is asserted high. The TCBGT flag can be used to detect the end of data transfer without waiting for guard time completion. This flag is set just after the end of frame transmission and if no NACK has been received from the card.

The deassertion of TC flag is unaffected by smartcard mode.

If a framing error is detected on the transmitter end (due to a NACK from the receiver), the NACK is not detected as a start bit by the receive block of the transmitter. According to the ISO protocol, the duration of the received NACK can be 1 or 2 baud clock periods.

On the receiver side, if a parity error is detected and a NACK is transmitted the receiver does not detect the NACK as a start bit.

Note: Break characters are not significant in smartcard mode. A 0x00 data with a framing error is treated as data and not as a break.

No Idle frame is transmitted when toggling the TE bit. The Idle frame (as defined for the other configurations) is not defined by the ISO protocol.

Figure 548 shows how the NACK signal is sampled by the USART. In this example the USART is transmitting data and is configured with 1.5 stop bits. The receiver part of the USART is enabled in order to check the integrity of the data and the NACK signal.

Figure 548. Parity error detection using the 1.5 stop bits

MSv31163V1

The USART can provide a clock to the smartcard through the CK output. In smartcard mode, CK is not associated to the communication but is simply derived from the internal peripheral input clock through a 5-bit prescaler. The division ratio is configured in the USART_GTPR register. CK frequency can be programmed from usart_ker_ck_pres/2 to usart_ker_ck_pres/62, where usart_ker_ck_pres is the peripheral input clock divided by a programmed prescaler.

Block mode (T = 1)

T = 1

(block) mode,the parity error transmission can be deactivated by clearing the

When requesting a read from the smartcard, in block mode, the software must program the RTOR register to the BWT (block wait time) - 11 value. If no answer is received from the card before the expiration of this period, a timeout interrupt is generated. If the first character is received before the expiration of the period, it is signaled by the RXNE/RXFNE interrupt.

RM0440	Universal synchronous/asynchronous receiver transmitter (USART/UART)
	(0x0). With this value, an interrupt is generated after the 4th received character. The software must read the LEN field (third byte), its value must be read from the receive buffer.
	In interrupt driven receive mode, the length of the block may be checked by software or by programming the BLEN value. However, before the start of the block, the maximum value of BLEN (0xFF) may be programmed. The real value is programmed after the reception of the third character.
	If the block is using the LRC longitudinal redundancy check (1 epilogue byte), the BLEN = LEN. If the block is using the CRC mechanism (2 epilog bytes), BLEN = LEN+1 must be programmed. The total block length (including prologue, epilogue and information fields) equals BLEN+4. The end of the block is signaled to the software through the EOBF flag and interrupt (when EOBIE bit is set).
	In case of an error in the block length, the end of the block is signaled by the RTO interrupt (Character Wait Time overflow).
Note:	The error checking code (LRC/CRC) must be computed/verified by software.
	Direct and inverse convention
	The smartcard protocol defines two conventions: direct and inverse
	The direct convention is defined as: LSB first, logical bit value of 1 corresponds to a H state of the line and parity is even. In order to use this convention, the following control bits must be programmed: MSBFIRST = 0, DATAINV = 0 (default values).
	The inverse convention is defined as: MSB first, logical bit value 1 corresponds to an L state on the signal line and parity is even. In order to use this convention, the following control bits must be programmed: MSBFIRST = 1, DATAINV = 1.
Note:	When logical data values are inverted $(0 = H, 1 = L)$ ,the parity bit is also inverted in the same way.
	In order to recognize the card convention, the card sends the initial character, TS, as the first character of the ATR (Answer To Reset) frame. The two possible patterns for the TS are: LHHL LLL LLH and LHHL HHH LLH.
	(H) LHHL LLL LLH sets up the inverse convention: state L encodes value 1 and moment 2 conveys the most significant bit (MSB first). When decoded by inverse convention, the conveyed byte is equal to ’3F’.
	(H) LHHL HHH LLH sets up the direct convention: state H encodes value 1 and moment 2 conveys the least significant bit (LSB first). When decoded by direct convention, the conveyed byte is equal to ’3B’.
	Character parity is correct when there is an even number of bits set to 1 in the nine moments 2 to 10.
	As the USART does not know which convention is used by the card, it needs to be able to recognize either pattern and act accordingly. The pattern recognition is not done hardware, but through a software sequence. Moreover, assuming that the USART is configured in direct convention (default) and the card answers with the inverse convention. TS = LHHL LLL LLH results in a USART received character of 03 and an odd parity.

Therefore, two methods are available for TS pattern recognition:

Method 1

The USART is programmed in standard smartcard mode/direct convention. In this case, the

TS pattern reception generates a parity error interrupt and error signal to the card.

The parity error interrupt informs the software that the card did not answer correctly in direct convention. Software then reprograms the USART for inverse convention

In response to the error signal, the card retries the same TS character, and it is correctly received this time, by the reprogrammed USART.

Alternatively, in answer to the parity error interrupt, the software may decide to reprogram the USART and to also generate a new reset command to the card, then wait again for the TS.

Method 2

The USART is programmed in 9-bit/no-parity mode, no bit inversion. In this mode it receives any of the two TS patterns as:

(H) LHHL LLL LLH = 0x103: inverse convention to be chosen

(H) LHHL HHH LLH = 0x13B: direct convention to be chosen

The software checks the received character against these two patterns and, if any of them match, then programs the USART accordingly for the next character reception.

If none of the two is recognized, a card reset may be generated in order to restart the negotiation.

37.5.18 USART IrDA SIR ENDEC block

This section is relevant only when IrDA mode is supported. Refer to Section 37.4: USART implementation on page 1610.

IrDA mode is selected by setting the IREN bit in the USART_CR3 register. In IrDA mode, the following bits must be kept cleared:

LINEN, STOP and CLKEN bits in the USART_CR2 register,

SCEN and HDSEL bits in the USART_CR3 register.

The IrDA SIR physical layer specifies use of a Return to Zero, Inverted (RZI) modulation scheme that represents logic 0 as an infrared light pulse (see Figure 549).

The SIR Transmit encoder modulates the Non Return to Zero (NRZ) transmit bit stream output from USART. The output pulse stream is transmitted to an external output driver and infrared LED. USART supports only bit rates up to 115.2 kbaud for the SIR ENDEC. In normal mode the transmitted pulse width is specified as

3 / 16

of a bit period.

The SIR receive decoder demodulates the return-to-zero bit stream from the infrared detector and outputs the received NRZ serial bit stream to the USART. The decoder input is normally high (marking state) in the Idle state. The transmit encoder output has the opposite polarity to the decoder input. A start bit is detected when the decoder input is low.

IrDA is a half duplex communication protocol. If the Transmitter is busy (when the USART is sending data to the IrDA encoder), any data on the IrDA receive line is ignored by the IrDA decoder and if the Receiver is busy (when the USART is receiving decoded data from the USART), data on the TX from the USART to IrDA is not encoded. While receiving data, transmission should be avoided as the data to be transmitted could be corrupted.

A ’ 0 ’ is transmitted as a high pulse and a ’ 1 ’ is transmitted as a ’ 0 ’. The width of the pulse is specified as $3 / 16$ th of the selected bit period in normal mode (see Figure 550).

The SIR decoder converts the IrDA compliant receive signal into a bit stream for USART.

The SIR receive logic interprets a high state as a logic one and low pulses as logic zeros.

The transmit encoder output has the opposite polarity to the decoder input. The SIR output is in low state when Idle.

The IrDA specification requires the acceptance of pulses greater than $1.41 μ s$ . The acceptable pulse width is programmable. Glitch detection logic on the receiver end filters out pulses of width less than 2 PSC periods (PSC is the prescaler value programmed in the USART_GTPR). Pulses of width less than 1 PSC period are always rejected, but those of width greater than one and less than two periods may be accepted or rejected, those greater than two periods are accepted as a pulse. The IrDA encoder/decoder doesn’t work when PSC $= 0$ .

The receiver can communicate with a low-power transmitter.

In IrDA mode, the stop bits in the USART_CR2 register must be configured to '1 stop bit'.

IrDA low-power mode

Transmitter

In low-power mode, the pulse width is not maintained at 3/16 of the bit period. Instead, the width of the pulse is 3 times the low-power baud rate which can be a minimum of 1.42 MHz. Generally, this value is 1.8432 MHz (1.42 MHz < PSC < 2.12 MHz). A low-power mode programmable divisor divides the system clock to achieve this value.

Receiver

Receiving in low-power mode is similar to receiving in normal mode. For glitch detection the USART should discard pulses of duration shorter than

1 / PSC

. A valid low is accepted only if its duration is greater than 2 periods of the IrDA low-power Baud clock (PSC value in the USART_GTPR).

Note: A pulse of width less than two and greater than one PSC period(s) may or may not be rejected.

The receiver set up time should be managed by software. The IrDA physical layer specification specifies a minimum of

10 ms

delay between transmission and reception (IrDA is a half duplex protocol).

37.5.19 Continuous communication using USART and DMA

The USART is capable of performing continuous communications using the DMA. The DMA requests for

Rx

buffer and

Tx

buffer are generated independently.

Note: Refer to Section 37.4: USART implementation on page 1610 to determine if the DMA mode is supported. If DMA is not supported, use the USART as explained in Section 37.5.6. To perform continuous communications when the FIFO is disabled, clear the TXE/RXNE flags in the USART_ISR register.

Transmission using DMA

DMA mode can be enabled for transmission by setting DMAT bit in the USART_CR3 register. Data are loaded from an SRAM area configured using the DMA peripheral (refer to the corresponding Direct memory access controller section) to the USART_TDR register whenever the TXE flag (TXFNF flag if FIFO mode is enabled) is set. To map a DMA channel for USART transmission, use the following procedure (x denotes the channel number):

Write the USART_TDR register address in the DMA control register to configure it as the destination of the transfer. The data is moved to this address from memory after each TXE (or TXFNF if FIFO mode is enabled) event.

Write the memory address in the DMA control register to configure it as the source of the transfer. The data is loaded into the USART_TDR register from this memory area after each TXE (or TXFNF if FIFO mode is enabled) event.

Configure the total number of bytes to be transferred to the DMA control register.

Configure the channel priority in the DMA register

Configure DMA interrupt generation after half/ full transfer as required by the application.

Clear the TC flag in the USART_ISR register by setting the TCCF bit in the USART_ICR register.

Activate the channel in the DMA register.

When the number of data transfers programmed in the DMA Controller is reached, the DMA controller generates an interrupt on the DMA channel interrupt vector.

In transmission mode, once the DMA has written all the data to be transmitted (the TCIF flag is set in the DMA_ISR register), the TC flag can be monitored to make sure that the USART communication is complete. This is required to avoid corrupting the last transmission before disabling the USART or before the system enters a low-power mode when the peripheral clock is disabled. Software must wait until TC = 1. The TC flag remains cleared during all data transfers and it is set by hardware at the end of transmission of the last frame.

Figure 551. Transmission using DMA

Note: When FIFO management is enabled, the DMA request is triggered by Transmit FIFO not full (i.e.

T X F N F = 1

Reception using DMA

DMA mode can be enabled for reception by setting the DMAR bit in USART_CR3 register. Data are loaded from the USART_RDR register to an SRAM area configured using the DMA peripheral (refer to the corresponding Direct memory access controller section) whenever a data byte is received. To map a DMA channel for USART reception, use the following procedure:

Write the USART_RDR register address in the DMA control register to configure it as the source of the transfer. The data is moved from this address to the memory after each RXNE (RXFNE in case FIFO mode is enabled) event.

Write the memory address in the DMA control register to configure it as the destination of the transfer. The data is loaded from USART_RDR to this memory area after each RXNE (RXFNE in case FIFO mode is enabled) event.

Configure the total number of bytes to be transferred to the DMA control register.

Configure the channel priority in the DMA control register

Configure interrupt generation after half/ full transfer as required by the application.

Activate the channel in the DMA control register.

When the number of data transfers programmed in the DMA Controller is reached, the DMA controller generates an interrupt on the DMA channel interrupt vector.

Figure 552. Reception using DMA

Note: When FIFO management is enabled, the DMA request is triggered by Receive FIFO not empty (i.e. RXFNE = 1).

Error flagging and interrupt generation in multibuffer communication

If any error occurs during a transaction in multibuffer communication mode, the error flag is asserted after the current byte. An interrupt is generated if the interrupt enable flag is set. For framing error, overrun error and noise flag which are asserted with RXNE (RXFNE in case FIFO mode is enabled) in single byte reception, there is a separate error flag interrupt enable bit (EIE bit in the USART_CR3 register), which, if set, enables an interrupt after the current byte if any of these errors occur.

37.5.20 RS232 hardware flow control and RS485 Driver Enable

It is possible to control the serial data flow between 2 devices by using the CTS input and the RTS output. The Figure 553 shows how to connect 2 devices in this mode:

Figure 553. Hardware flow control between 2 USARTs

RS232 RTS and CTS flow control can be enabled independently by writing the RTSE and CTSE bits to '1' in the USART_CR3 register.

RS232 RTS flow control

If the RTS flow control is enabled (RTSE = 1), then RTS is deasserted (tied low) as long as the USART receiver is ready to receive a new data. When the receive register is full, RTS is asserted, indicating that the transmission is expected to stop at the end of the current frame. Figure 554 shows an example of communication with RTS flow control enabled. Note:

Figure 554. RS232 RTS flow control

When FIFO mode is enabled, RTS is asserted only when RXFIFO is full.

RS232 CTS flow control

If the CTS flow control is enabled (CTSE = 1), then the transmitter checks the CTS input before transmitting the next frame. If CTS is deasserted (tied low), then the next data is transmitted (assuming that data is to be transmitted,in other words,if TXE/TXFE = 0),else the transmission does not occur. When CTS is asserted during a transmission, the current transmission is completed before the transmitter stops.

When CTSE = 1, the CTSIF status bit is automatically set by hardware as soon as the CTS input toggles. It indicates when the receiver becomes ready or not ready for communication. An interrupt is generated if the CTSIE bit in the USART_CR3 register is set. Figure 555 shows an example of communication with CTS flow control enabled. Note:

For correct behavior, CTS must be deasserted at least 3 USART clock source periods before the end of the current character. In addition it should be noted that the CTSCF flag may not be set for pulses shorter than 2 x PCLK periods.

RS485 driver enable

The driver enable feature is enabled by setting bit DEM in the USART_CR3 control register. This enables the user to activate the external transceiver control, through the DE (Driver Enable) signal. The assertion time is the time between the activation of the DE signal and the beginning of the start bit. It is programmed using the DEAT [4:0] bitfields in the USART_CR1 control register. The deassertion time is the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE signal. It is programmed using the DEDT [4:0] bitfields in the USART_CR1 control register. The polarity of the DE signal can be configured using the DEP bit in the USART_CR3 control register.

In USART, the DEAT and DEDT are expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate).

37.5.21 USART low-power management

The USART has advanced low-power mode functions, that enables transferring properly data even when the usart_pclk clock is disabled.

The USART is able to wake up the MCU from low-power mode when the UESM bit is set.

When the usart_pclk is gated, the USART provides a wake-up interrupt (usart_wkup) if a specific action requiring the activation of the usart_pclk clock is needed:

If FIFO mode is disabled

usart_pclk clock has to be activated to empty the USART data register.

In this case, the usart_wkup interrupt source is RXNE set to '1'. The RXNEIE bit must be set before entering low-power mode.

If FIFO mode is enabled

usart_pclk clock has to be activated to:

to fill the TXFIFO

or to empty the RXFIFO

In this case, the usart_wkup interrupt source can be:

RXFIFO not empty. In this case, the RXFNEIE bit must be set before entering low-power mode.

RXFIFO full. In this case, the RXFFIE bit must be set before entering low-power mode, the number of received data corresponds to the RXFIFO size, and the RXFF flag is not set.

TXFIFO empty. In this case, the TXFEIE bit must be set before entering low-power mode.

This enables sending/receiving the data in the TXFIFO/RXFIFO during low-power mode.

To avoid overrun/underrun errors and transmit/receive data in low-power mode, the usart_wkup interrupt source can be one of the following events:

TXFIFO threshold reached. In this case, the TXFTIE bit must be set before entering low-power mode.

RXFIFO threshold reached. In this case, the RXFTIE bit must be set before entering low-power mode.

For example, the application can set the threshold to the maximum RXFIFO size if the wake-up time is less than the time required to receive a single byte across the line.

Using the RXFIFO full, TXFIFO empty, RXFIFO not empty and RXFIFO/TXFIFO threshold interrupts to wake up the MCU from low-power mode enables doing as many USART transfers as possible during low-power mode with the benefit of optimizing consumption.

Alternatively, a specific usart_wkup interrupt can be selected through the WUS bitfields.

When the wake-up event is detected, the WUF flag is set by hardware and a usart_wkup interrupt is generated if the WUFIE bit is set.

Note: Before entering low-power mode, make sure that no USART transfers are ongoing.

Checking the BUSY flag cannot ensure that low-power mode is never entered when data reception is ongoing.

The WUF flag is set when a wake-up event is detected, independently of whether the MCU is in low-power or active mode.

When entering low-power mode just after having initialized and enabled the receiver, the REACK bit must be checked to make sure the USART is enabled.

When DMA is used for reception, it must be disabled before entering low-power mode and re-enabled when exiting from low-power mode.

When the FIFO is enabled, waking up from low-power mode on address match is only possible when mute mode is enabled.

Using mute mode with low-power mode

If the USART is put into mute mode before entering low-power mode:

Wake-up from mute mode on idle detection must not be used, because idle detection cannot work in low-power mode.

If the wake-up from mute mode on address match is used, then the low-power mode wake-up source must also be the address match. If the RXNE flag was set when entering the low-power mode, the interface remains in mute mode upon address match and wake up from low-power mode.

Note: When FIFO management is enabled, mute mode can be used with wake-up from low-power mode without any constraints (i.e.the two points mentioned above about mute and low-power mode are valid only when FIFO management is disabled).

Wake-up from low-power mode when USART kernel clock (usart_ker_ck) is OFF in low-power mode

If during low-power mode, the usart_ker_ck clock is switched OFF when a falling edge on the USART receive line is detected, the USART interface requests the usart_ker_ck clock to be switched

ON

thanks to the usart_ker_ck_req signal. usart_ker_ck is then used for the frame reception.

If the wake-up event is verified, the MCU wakes up from low-power mode and data reception goes on normally.

If the wake-up event is not verified, usart_ker_ck is switched OFF again, the MCU is not woken up and remains in low-power mode, and the kernel clock request is released.

The example below shows the case of a wake-up event programmed to "address match detection" and FIFO management disabled.

Determining the maximum USART baud rate that enables to correctly wake up the device from low-power mode

The maximum baud rate that enables to correctly wake up the device from low-power mode depends on the wake-up time parameter (refer to the device datasheet) and on the USART receiver tolerance (see Section 37.5.8: Tolerance of the USART receiver to clock deviation).

Let us take the example of OVER8 = 0, M bits = '01', ONEBIT = 0 and BRR [3:0] = 0000.

In these conditions, according to Table 349: Tolerance of the USART receiver when BRR

[3 : 0] = 0000

,the USART receiver tolerance equals

3.41 %

DTRA + DQUANT + DREC + DTCL + DWU < USART receiver tolerance

D_{WUmax} = t_{WUUSART} / (11 \times T_{bit Min})

T_{bit Min} = t_{WUUSART} / (11 \times D_{WUmax})

where

t_{WUUSART}

is the wake-up time from low-power mode.

If we consider the ideal case where DTRA, DQUANT, DREC and DTCL parameters are at

0 %

,the maximum value of DWU is

3.41 %

. In reality,we need to consider at least the usart_ker_ck inaccuracy.

For example,if HSI16 is used as usart_ker_ck,and the HSI16 inaccuracy is of

1 %

,then we obtain:

t_{WUUSART} = 3 μ s

(values provided only as examples; for correct values,refer to the device datasheet).

D_{WUmax} = 3.41 % - 1 % = 2.41 %

T_{bit \min} = 3 μ s / (11 \times 2.41 %) = 11.32 μ s .

As a result, the maximum baud rate that enables to wake up correctly from low-power mode is:

1 / 11.32 μ s = 88.36 Kbaud

37.6 USART in low-power modes

Table 352. Effect of low-power modes on the USART

Mode	Description
Sleep	No effect. USART interrupts cause the device to exit Sleep mode.
Stop(1)	The content of the USART registers is kept The USART is able to wake up the microcontroller from Stop mode wher the USART is clocked by an oscillator available in Stop mode.
Standby	The USART peripheral is powered down and must be reinitialized afte exiting Standby mode.

Refer to Section 37.4: USART implementation to know if the wake-up from Stop mode is supported for a given peripheral instance. If an instance is not functional in a given Stop mode, it must be disabled before entering this Stop mode.

37.7 USART interrupts

Refer to Table 353 for a detailed description of all USART interrupt requests.

Table 353. USART interrupt requests

Interrupt vector	Interrupt event	Event flag	Enable Control bit	Interrupt clear method	Exit from Sleep mode	Exit from Stop(1) modes	Exit from Standby mode
USART or UART	Transmit data register empty	TXE	TXEIE	Write TDR	Yes	No	No
	Transmit FIFO not Full	TXFNF	TXFNFIE	TXFIFO full		No
	Transmit FIFO Empty	TXFE	TXFEIE	Write TDR or write 1 in TXFRQ		Yes
	Transmit FIFO threshold reached	TXFT	TXFTIE	Write TDR		Yes
	CTS interrupt	CTSIF	CTSIE	Write 1 in CTSCF		No
	Transmission Complete	TC	TCIE	Write TDR or write 1 in TCCF		No
	Transmission Complete Before Guard Time	TCBGT	TCBGTIE	Write TDR or write 1 in TCBGT		No
USART or UART	Receive data register not empty (data ready to be read)	RXNE	RXNEIE	Read RDR or write 1 in RXFRQ	Yes	Yes	No
	Receive FIFO Not Empty	RXFNE	RXFNEIE	Read RDR until RXFIFO empty or write 1 in RXFRQ		Yes
	Receive FIFO Full	RXFF(2)	RXFFIE	Read RDR		Yes
	Receive FIFO threshold reached	RXFT	RXFTIE	Read RDR		Yes
	Overrun error detected	ORE	RXNEIE/ RXFNEIE	Write 1 in ORECF		No
	Idle line detected	IDLE	IDLEIE	Write 1 in IDLECF		No
	Parity error	PE	PEIE	Write 1 in PECF		No
	LIN break	LBDF	LBDIE	Write 1 in LBDCF		No
	Noise error in multibuffer communication	NE	EIE	Write 1 in NFCF		No
	Overrun error in multibuffer communication	ORE(3)		Write 1 in ORECF		No
	Framing Error in multibuffer communication	FE		Write 1 in FECF		No
	Character match	CMF	CMIE	Write 1 in CMCF		No
	Receiver timeout	RTOF	RTOFIE	Write 1 in RTOCCF		No
	End of Block	EOBF	EOBIE	Write 1 in EOBCF		No
	Wake-up from low-power mode	WUF	WUFIE	Write 1 in WUC		Yes
	SPI slave underrun error	UDR	EIE	Write 1 in UDRCF		No

The USART can wake up the device from Stop mode only if the peripheral instance supports the wake-up from Stop mode feature. Refer to Section 37.4: USART implementation for the list of supported Stop modes.

RXFF flag is asserted if the USART receives $n + 1$ data (n being the RXFIFO size): $n$ data in the RXFIFO and 1 data in USART_RDR. In Stop mode, USART_RDR is not clocked. As a result, this register is not written and once n data are received and written in the RXFIFO, the RXFF interrupt is asserted (RXFF flag is not set).

When OVRDIS $= 0$ .

37.8 USART registers

Refer to Section 1.2 on page 73 for a list of abbreviations used in register descriptions.

The peripheral registers have to be accessed by words (32 bits).

37.8.1 USART control register 1 (USART_CR1)

Address offset: 0x00

Reset value: 0x00000000

The same register can be used in FIFO mode enabled (this section) and FIFO mode disabled (next section).

FIFO mode enabled

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXF FIE	TXFEIE	FIFO EN	M1	EOBIE	RTOIE	DEAT[4:0]					DEDT[4:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXFNFI E	TCIE	RXFNE IE	IDLEIE	TE	RE	UESM	UE
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bit 31 RXFFIE: RXFIFO full interrupt enable

This bit is set and cleared by software.

0: Interrupt inhibited

1: USART interrupt generated when RXFF = 1 in the USART_ISR register

Bit 30 TXFEIE: TXFIFO empty interrupt enable

This bit is set and cleared by software.

0 : Interrupt inhibited

1: USART interrupt generated when TXFE = 1 in the USART_ISR register

Bit 29 FIFOEN: FIFO mode enable

This bit is set and cleared by software.

0 : FIFO mode is disabled.

1: FIFO mode is enabled.

This bitfield can only be written when the USART is disabled (UE = 0).

Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode

and in smartcard modes only. It must not be enabled in IrDA and LIN modes.

Bit 28 M1: Word length

This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software.

M [1 : 0] =

’00’: 1 start bit,8 Data bits,n Stop bit

M [1 : 0] =

’01’: 1 start bit,9 Data bits,n Stop bit

M [1 : 0] =

’10’: 1 start bit,7 Data bits,n Stop bit

This bit can only be written when the USART is disabled

(U E = 0)

Note: In 7-bits data length mode, the smartcard mode, LIN master mode and auto baud rate

(0x7F and 0x55 frames detection) are not supported.

Bit 27 EOBIE: End-of-block interrupt enable

This bit is set and cleared by software.

0 : Interrupt inhibited

1: USART interrupt generated when the EOBF flag is set in the USART_ISR register

Note: If the USART does not support smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 26 RTOIE: Receiver timeout interrupt enable

This bit is set and cleared by software.

0 : Interrupt inhibited

1: USART interrupt generated when the RTOF bit is set in the USART_ISR register.

Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Section 37.4: USART implementation on page 1610.

Bits 25:21 DEAT[4:0]: Driver enable assertion time

This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (

1 / 8

1 / 16

bit time, depending on the oversampling rate).

This bitfield can only be written when the USART is disabled (UE

= 0

Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at

reset value. Refer to Section 37.4: USART implementation on page 1610.

Bits 20:16 DEDT[4:0]: Driver enable deassertion time

This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate).

If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed.

This bitfield can only be written when the USART is disabled (UE = 0).

Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 15 OVER8: Oversampling mode

0 : Oversampling by 16

1: Oversampling by 8

This bit can only be written when the USART is disabled (UE = 0).

Note: In LIN, IrDA and smartcard modes, this bit must be kept cleared.

Bit 14 CMIE: Character match interrupt enable

This bit is set and cleared by software.

0 : Interrupt inhibited

1: USART interrupt generated when the CMF bit is set in the USART_ISR register.

Bit 13 MME: Mute mode enable

This bit enables the USART mute mode function. When set, the USART can switch between active and mute mode, as defined by the WAKE bit. It is set and cleared by software.

0 : Receiver in active mode permanently

1: Receiver can switch between mute mode and active mode.

Bit 12 M0: Word length

This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or

cleared by software (refer to bit 28 (M1)description).

This bit can only be written when the USART is disabled

(UE = 0)

Bit 11 WAKE: Receiver wake-up method

This bit determines the USART wake-up method from mute mode. It is set or cleared by software.

0 : Idle line

1: Address mark

This bitfield can only be written when the USART is disabled (UE = 0).

Bit 10 PCE: Parity control enable

This bit selects the hardware parity control (generation and detection). When the parity

control is enabled,the computed parity is inserted at the MSB position (9th bit if

M = 1

; 8th bit

M = 0

) and the parity is checked on the received data. This bit is set and cleared by

software. Once it is set, PCE is active after the current byte (in reception and in

transmission).

0 : Parity control disabled

1: Parity control enabled

This bitfield can only be written when the USART is disabled (UE = 0).

Bit 9 PS: Parity selection

This bit selects the odd or even parity when the parity generation/detection is enabled (PCE

bit set). It is set and cleared by software. The parity is selected after the current byte.

0 : Even parity

1: Odd parity

This bitfield can only be written when the USART is disabled (UE = 0).

Bit 8 PEIE: PE interrupt enable

This bit is set and cleared by software.

0 : Interrupt inhibited

1: USART interrupt generated whenever

PE = 1

in the USART_ISR register

Bit 7 TXFNFIE: TXFIFO not-full interrupt enable

This bit is set and cleared by software.

0 : Interrupt inhibited

1: USART interrupt generated whenever TXFNF =1 in the USART_ISR register

Bit 6 TCIE: Transmission complete interrupt enable

This bit is set and cleared by software.

0 : Interrupt inhibited

1: USART interrupt generated whenever TC = 1 in the USART_ISR register

Bit 5 RXFNEIE: RXFIFO not empty interrupt enable

This bit is set and cleared by software.

0 : Interrupt inhibited

1: USART interrupt generated whenever ORE = 1 or RXFNE = 1 in the USART_ISR register

Bit 4 IDLEIE: IDLE interrupt enable

This bit is set and cleared by software.

0 : Interrupt inhibited

1: USART interrupt generated whenever IDLE = 1 in the USART_ISR register

Bit 3 TE: Transmitter enable

This bit enables the transmitter. It is set and cleared by software.

0 : Transmitter is disabled

1: Transmitter is enabled

Note: During transmission, a low pulse on the TE bit (‘0’ followed by ‘1’) sends a preamble (idle line) after the current word, except in smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1'. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register.

In smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts.

Bit 2 RE: Receiver enable

This bit enables the receiver. It is set and cleared by software.

0 : Receiver is disabled

1: Receiver is enabled and begins searching for a start bit

Bit 1 UESM: USART enable in low-power mode

When this bit is cleared, the USART cannot wake up the MCU from low-power mode.

When this bit is set, the USART can wake up the MCU from low-power mode.

This bit is set and cleared by software.

0: USART not able to wake up the MCU from low-power mode.

1: USART able to wake up the MCU from low-power mode.

Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode.

If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 0 UE: USART enable

When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software.

0: USART prescaler and outputs disabled, low-power mode

1: USART enabled

Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit.

The DMA requests are also reset when

U E = 0

so the DMA channel must be disabled before resetting the UE bit.

In smartcard mode,

(S C E N = 1)

,the

C K

is always available when

C L K E N = 1

, regardless of the UE bit value.

37.8.2 USART control register 1 [alternate] (USART_CR1)

Address offset: 0x00

Reset value: 0x00000000

The same register can be used in FIFO mode enabled (previous section) and FIFO mode disabled (this section).

FIFO mode disabled

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	FIFO EN	M1	EOBIE	RTOIE	DEAT[4:0]					DEDT[4:0]
		rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXEIE	TCIE	RXNEI E	IDLEIE	TE	RE	UESM	UE
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 FIFOEN: FIFO mode enable

This bit is set and cleared by software.

0 : FIFO mode is disabled.

1: FIFO mode is enabled.

This bitfield can only be written when the USART is disabled (UE = 0).

Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in smartcard modes only. It must not be enabled in IrDA and LIN modes.

Bit 28 M1: Word length

This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software.

M [1 : 0] =

’00’: 1 start bit,8 Data bits,n Stop bit

M [1 : 0] =

’01’: 1 start bit,9 Data bits,n Stop bit

M [1 : 0] =

’10’: 1 start bit,7 Data bits,n Stop bit

This bit can only be written when the USART is disabled (UE = 0).

Note: In 7-bits data length mode, the smartcard mode, LIN master mode and auto baud rate

(0x7F and 0x55 frames detection) are not supported.

Bit 27 EOBIE: End of Bbock interrupt enable

This bit is set and cleared by software.

0: Interrupt inhibited

1: USART interrupt generated when the EOBF flag is set in the USART_ISR register

Note: If the USART does not support smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 26 RTOIE: Receiver timeout interrupt enable

This bit is set and cleared by software.

0 : Interrupt inhibited

1: USART interrupt generated when the RTOF bit is set in the USART_ISR register.

Note: If the USART does not support the Receiver timeout feature, this bit is reserved and

must be kept at reset value. Section 37.4: USART implementation on page 1610.

This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (

1 / 8

1 / 16

bit time, depending on the oversampling rate).

This bitfield can only be written when the USART is disabled (UE

= 0

Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bits 20:16 DEDT[4:0]: Driver enable deassertion time

If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed.

This bitfield can only be written when the USART is disabled (UE = 0).

Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 15 OVER8: Oversampling mode

0: Oversampling by 16

1: Oversampling by 8

This bit can only be written when the USART is disabled (UE = 0).

Note: In LIN, IrDA and smartcard modes, this bit must be kept cleared.

Bit 14 CMIE: Character match interrupt enable

This bit is set and cleared by software.

0 : Interrupt inhibited

1: USART interrupt generated when the CMF bit is set in the USART_ISR register.

Bit 13 MME: Mute mode enable

This bit enables the USART mute mode function. When set, the USART can switch between active and mute mode, as defined by the WAKE bit. It is set and cleared by software.

0 : Receiver in active mode permanently

1: Receiver can switch between mute mode and active mode.

Bit 12 M0: Word length

This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description).

This bit can only be written when the USART is disabled (UE = 0 ).

Bit 11 WAKE: Receiver wake-up method

This bit determines the USART wake-up method from mute mode. It is set or cleared by software.

0 : Idle line

1: Address mark

This bitfield can only be written when the USART is disabled (UE = 0).

Bit 10 PCE: Parity control enable

This bit selects the hardware parity control (generation and detection). When the parity control is enabled,the computed parity is inserted at the MSB position (9th bit if

M = 1

; 8th bit if

M = 0

) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission).

0 : Parity control disabled

1: Parity control enabled

This bitfield can only be written when the USART is disabled (UE = 0).

Bits 25:21 DEAT[4:0]: Driver enable assertion time

Bit 9 PS: Parity selection

This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte.

0 : Even parity

1: Odd parity

This bitfield can only be written when the USART is disabled (UE = 0).

Bit 8 PEIE: PE interrupt enable

This bit is set and cleared by software.

0 : Interrupt inhibited

1: USART interrupt generated whenever

PE = 1

in the USART_ISR register

Bit 7 TXEIE: Transmit data register empty

This bit is set and cleared by software.

0: Interrupt inhibited

1: USART interrupt generated whenever TXE =1 in the USART_ISR register

Bit 6 TCIE: Transmission complete interrupt enable

This bit is set and cleared by software.

0 : Interrupt inhibited

1: USART interrupt generated whenever TC = 1 in the USART_ISR register

Bit 5 RXNEIE: Receive data register not empty

This bit is set and cleared by software.

0 : Interrupt inhibited

1: USART interrupt generated whenever ORE = 1 or RXNE = 1 in the USART_ISR register

Bit 4 IDLEIE: IDLE interrupt enable

This bit is set and cleared by software.

0 : Interrupt inhibited

1: USART interrupt generated whenever IDLE = 1 in the USART_ISR register

Bit 3 TE: Transmitter enable

This bit enables the transmitter. It is set and cleared by software.

0 : Transmitter is disabled

1: Transmitter is enabled

Note: During transmission, a low pulse on the TE bit (‘0’ followed by ‘1’) sends a preamble

(idle line) after the current word, except in smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1'. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register.

In smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts.

Bit 2 RE: Receiver enable

This bit enables the receiver. It is set and cleared by software.

0 : Receiver is disabled

1: Receiver is enabled and begins searching for a start bit

Bit 1 UESM: USART enable in low-power mode

When this bit is cleared, the USART cannot wake up the MCU from low-power mode.

When this bit is set, the USART can wake up the MCU from low-power mode.

This bit is set and cleared by software.

0: USART not able to wake up the MCU from low-power mode.

1: USART able to wake up the MCU from low-power mode.

Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode.

If the USART does not support the wake-up from Stop feature, this bit is reserved and

must be kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 0 UE: USART enable

0: USART prescaler and outputs disabled, low-power mode

1: USART enabled

The DMA requests are also reset when

U E = 0

so the DMA channel must be disabled before resetting the UE bit.

In smartcard mode,

(S C E N = 1)

,the

C K

pin is always available when

C L K E N = 1

regardless of the UE bit value.

37.8.3 USART control register 2 (USART_CR2)

Address offset: 0x04

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD[7:0]								RTOEN	ABRMOD[1:0]		ABREN	MSBFI RST	DATAIN V	TXINV	RXINV
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWAP	LINEN	STOP[1:0]		CLKEN	CPOL	CPHA	LBCL	Res.	LBDIE	LBDL	ADDM7	DIS NSS	Res.	Res.	SLVEN
rw	rw	rw	rw	rw	rw	rw	rw		rw	rw	rw	rw			rw

Bits 31:24 ADD[7:0]: Address of the USART node

These bits give the address of the USART node in mute mode or a character code to be recognized in low-power or Run mode:

In mute mode: they are used in multiprocessor communication to wake up from mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1 . In 4-bit address mark detection, only ADD[3:0] bits are used.

In low-power mode: they are used for wake up from low-power mode on character match. When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wake-up from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1 .

In Run mode with mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set.

These bits can only be written when the reception is disabled

(RE = 0)

or when the USART is disabled

(UE = 0)

Bit 23 RTOEN: Receiver timeout enable

This bit is set and cleared by software.

0 : Receiver timeout feature disabled.

1: Receiver timeout feature enabled.

When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register).

Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bits 22:21 ABRMOD[1:0]: Auto baud rate mode

These bits are set and cleared by software.

00: Measurement of the start bit is used to detect the baud rate.

01: Falling edge to falling edge measurement (the received frame must start with a single bit

= 1

and Frame = Start10xxxxxx)

10: 0x7F frame detection.

11: 0x55 frame detection

This bitfield can only be written when ABREN

= 0

or the USART is disabled (UE

= 0

Note: If DATAINV = 1 and/or MSBFIRST = 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST)

If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 20 ABREN: Auto baud rate enable

This bit is set and cleared by software.

0 : Auto baud rate detection is disabled.

1: Auto baud rate detection is enabled.

Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept

at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 19 MSBFIRST: Most significant bit first

This bit is set and cleared by software.

0: data is transmitted/received with data bit 0 first, following the start bit.

1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit.

This bitfield can only be written when the USART is disabled (UE

= 0

Bit 18 DATAINV: Binary data inversion

This bit is set and cleared by software.

0: Logical data from the data register are send/received in positive/direct logic.

(1 = H, 0 = L)

1: Logical data from the data register are send/received in negative/inverse logic.

(1 = L, 0 = H)

The parity bit is also inverted.

This bitfield can only be written when the USART is disabled (UE = 0).

Bit 17 TXINV: TX pin active level inversion

This bit is set and cleared by software.

0: TX pin signal works using the standard logic levels

(V_{D D} = 1 /

idle,

G n d = 0 / m a r k)

1: TX pin signal values are inverted

(V_{DD} = 0 /

mark,

Gnd = 1 / idle)

This enables the use of an external inverter on the TX line.

This bitfield can only be written when the USART is disabled (UE = 0).

Bit 16 RXINV: RX pin active level inversion

This bit is set and cleared by software.

0: RX pin signal works using the standard logic levels

(V_{D D} = 1 /

idle,

G n d = 0 / m a r k)

1: RX pin signal values are inverted

(V_{D D} = 0 /

mark,

Gnd = 1 / idle)

This enables the use of an external inverter on the RX line.

This bitfield can only be written when the USART is disabled (UE = 0).

Bit 15 SWAP: Swap TX/RX pins

This bit is set and cleared by software.

0: TX/RX pins are used as defined in standard pinout

1: The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired

connection to another UART.

This bitfield can only be written when the USART is disabled (UE = 0).

Bit 14 LINEN: LIN mode enable

This bit is set and cleared by software.

0: LIN mode disabled

1: LIN mode enabled

The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the

SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks.

This bitfield can only be written when the USART is disabled (UE = 0).

Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value.

Refer to Section 37.4: USART implementation on page 1610.

Bits 13:12 STOP[1:0]: Stop bits

These bits are used for programming the stop bits.

00: 1 stop bit

01: 0.5 stop bit.

10: 2 stop bits

11: 1.5 stop bits

This bitfield can only be written when the USART is disabled (UE = 0).

Bit 11 CLKEN: Clock enable

This bit enables the user to enable the CK pin.

0: CK pin disabled

1: CK pin enabled

This bit can only be written when the USART is disabled (UE = 0).

Note: If neither synchronous mode nor smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

In smartcard mode, in order to provide correctly the CK clock to the smartcard, the steps below must be respected:

U E = 0

S C E N = 1

GTPR configuration

CLKEN= 1

U E = 1

Bit 10 CPOL: Clock polarity

This bit enables the user to select the polarity of the clock output on the CK pin in synchronous

mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship

0: Steady low value on CK pin outside transmission window

1: Steady high value on CK pin outside transmission window

This bit can only be written when the USART is disabled (UE = 0 ).

Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value.

Refer to Section 37.4: USART implementation on page 1610.

Bit 9 CPHA: Clock phase

This bit is used to select the phase of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure 537 and Figure 538)

0 : The first clock transition is the first data capture edge

1: The second clock transition is the first data capture edge

This bit can only be written when the USART is disabled (UE = 0 ).

Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value.

Refer to Section 37.4: USART implementation on page 1610.

Bit 8 LBCL: Last bit clock pulse

This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in synchronous mode.

0 : The clock pulse of the last data bit is not output to the CK pin

1: The clock pulse of the last data bit is output to the CK pin

Caution: The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register.

This bit can only be written when the USART is disabled (UE = 0 ).

Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 7 Reserved, must be kept at reset value.

Bit 6 LBDIE: LIN break detection interrupt enable

Break interrupt mask (break detection using break delimiter).

0 : Interrupt is inhibited

1: An interrupt is generated whenever LBDF = 1 in the USART_ISR register

Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 5 LBDL: LIN break detection length

This bit is for selection between 11 bit or 10 bit break detection.

0: 10-bit break detection

1: 11-bit break detection

This bit can only be written when the USART is disabled (UE = 0).

Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to

Section 37.4: USART implementation on page 1610.

Bit 4 ADDM7: 7-bit address detection/4-bit address detection

This bit is for selection between 4-bit address detection or 7-bit address detection.

0: 4-bit address detection

1: 7-bit address detection (in 8-bit data mode)

This bit can only be written when the USART is disabled

(U E = 0)

Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address

(ADD[5:0] and ADD[7:0]) respectively.

Bit 3 DIS_NSS: NSS pin enable

When the DIS_NSS bit is set, the NSS pin input is ignored.

0: SPI slave selection depends on NSS input pin.

1: SPI slave is always selected and NSS input pin is ignored.

Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value.

Refer to Section 37.4: USART implementation on page 1610.

Bits 2:1 Reserved, must be kept at reset value.

Bit 0 SLVEN: Synchronous slave mode enable

When the SLVEN bit is set, the synchronous slave mode is enabled.

0 : Slave mode disabled.

1: Slave mode enabled.

Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Note:

The CPOL, CPHA and LBCL bits should not be written while the transmitter is enabled.

37.8.4 USART control register 3 (USART_CR3)

Address offset: 0x08

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXFTCFG[2:0]			RXF TIE	RXFTCFG[2:0]			TCBG TIE	TXFTIE	WUFIE	WUS[1:0]		SCARCNT[2:0]			Res.
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEP	DEM	DDRE	OVR DIS	ONE BIT	CTSIE	CTSE	RTSE	DMAT	DMAR	SCEN	NACK	HD SEL	IRLP	IREN	EIE
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:29 TXFTCFG[2:0]: TXFIFO threshold configuration

000:TXFIFO reaches 1/8 of its depth

001:TXFIFO reaches 1/4 of its depth

010:TXFIFO reaches 1/2 of its depth

011:TXFIFO reaches

3 / 4

of its depth

100:TXFIFO reaches 7/8 of its depth

101:TXFIFO becomes empty

Remaining combinations: Reserved

Bit 28 RXFTIE: RXFIFO threshold interrupt enable

This bit is set and cleared by software.

0 : Interrupt inhibited

1: USART interrupt generated when Receive FIFO reaches the threshold programmed in

RXFTCFG.

Bits 27:25 RXFTCFG[2:0]: Receive FIFO threshold configuration

000:Receive FIFO reaches 1/8 of its depth

001:Receive FIFO reaches 1/4 of its depth

010:Receive FIFO reaches 1/2 of its depth

011:Receive FIFO reaches 3/4 of its depth

100:Receive FIFO reaches 7/8 of its depth

101:Receive FIFO becomes full

Remaining combinations: Reserved

Bit 24 TCBGTIE: Transmission complete before guard time, interrupt enable

This bit is set and cleared by software.

0: Interrupt inhibited

1: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

Note: If the USART does not support the smartcard mode, this bit is reserved and must be

kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 23 TXFTIE: TXFIFO threshold interrupt enable

This bit is set and cleared by software.

0: Interrupt inhibited

1: USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG.

Bit 22 WUFIE: Wake-up from low-power mode interrupt enable

This bit is set and cleared by software.

0: Interrupt inhibited

1: USART interrupt generated whenever WUF

= 1

in the USART_ISR register Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bits 21:20 WUS[1:0]: Wake-up from low-power mode interrupt flag selection

This bitfield specifies the event which activates the WUF (wake-up from low-power mode flag).

00: WUF active on address match (as defined by ADD[7:0] and ADDM7)

01: Reserved.

10: WUF active on start bit detection

11: WUF active on RXNE/RXFNE.

This bitfield can only be written when the USART is disabled (UE = 0).

Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bits 19:17 SCARCNT[2:0]: Smartcard auto-retry count

This bitfield specifies the number of retries for transmission and reception in smartcard mode.

In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set).

In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set).

This bitfield must be programmed only when the USART is disabled (UE = 0).

When the USART is enabled

(U E = 1)

,this bitfield may only be written to

0 \times 0

,in order to stop retransmission.

0x0: retransmission disabled - No automatic retransmission in transmit mode.

0x1 to 0x7: number of automatic retransmission attempts (before signaling error)

Note: If smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 16 Reserved, must be kept at reset value.

Bit 15 DEP: Driver enable polarity selection

0 : DE signal is active high.

1: DE signal is active low.

This bit can only be written when the USART is disabled (UE = 0 ).

Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 14 DEM: Driver enable mode

This bit enables the user to activate the external transceiver control, through the DE signal.

0 : DE function is disabled.

1: DE function is enabled. The DE signal is output on the RTS pin.

This bit can only be written when the USART is disabled (UE = 0).

Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Section 37.4: USART implementation on page 1610.

Bit 13 DDRE: DMA Disable on reception error

0: DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred (used for smartcard mode).

1: DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE/RXFNE is case FIFO mode is enabled) before clearing the error flag.

This bit can only be written when the USART is disabled (UE=0).

Note: The reception errors are: parity error, framing error or noise error.

Bit 12 OVRDIS: Overrun disable

This bit is used to disable the receive overrun detection.

0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data.

1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used.

This bit can only be written when the USART is disabled (UE = 0).

Note: This control bit enables checking the communication flow w/o reading the data

Bit 11 ONEBIT: One sample bit method enable

This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled.

0 : Three sample bit method

1: One sample bit method

This bit can only be written when the USART is disabled (UE = 0).

Bit 10 CTSIE: CTS interrupt enable

0 : Interrupt is inhibited

1: An interrupt is generated whenever CTSIF = 1 in the USART_ISR register

Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 9 CTSE: CTS enable

0: CTS hardware flow control disabled

1: CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted.

This bit can only be written when the USART is disabled (UE = 0)

Note: If the hardware flow control feature is not supported, this bit is reserved and must be

kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 8 RTSE: RTS enable

0: RTS hardware flow control disabled

1: RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received.

This bit can only be written when the USART is disabled (UE = 0).

Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 7 DMAT: DMA enable transmitter

This bit is set/reset by software

1: DMA mode is enabled for transmission

0: DMA mode is disabled for transmission

Bit 6 DMAR: DMA enable receiver

This bit is set/reset by software

1: DMA mode is enabled for reception

0: DMA mode is disabled for reception

Bit 5 SCEN: Smartcard mode enable

This bit is used for enabling smartcard mode.

0: Smartcard mode disabled

1: Smartcard mode enabled

This bitfield can only be written when the USART is disabled (UE = 0).

Note: If the USART does not support smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 4 NACK: Smartcard NACK enable

0: NACK transmission in case of parity error is disabled

1: NACK transmission during parity error is enabled

This bitfield can only be written when the USART is disabled (UE = 0).

Note: If the USART does not support smartcard mode, this bit is reserved and must be kept

at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 3 HDSEL: Half-duplex selection

Selection of single-wire half-duplex mode

0 : Half duplex mode is not selected

1: Half duplex mode is selected

This bit can only be written when the USART is disabled (UE = 0).

Bit 2 IRLP: IrDA low-power

This bit is used for selecting between normal and low-power IrDA modes

0: Normal mode

1: Low-power mode

This bit can only be written when the USART is disabled (UE = 0).

Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value.

Refer to Section 37.4: USART implementation on page 1610.

Bit 1 IREN: IrDA mode enable

This bit is set and cleared by software.

0: IrDA disabled

1: IrDA enabled

This bit can only be written when the USART is disabled (UE = 0).

Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value.

Refer to Section 37.4: USART implementation on page 1610.

Bit 0 EIE: Error interrupt enable

Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing

error,overrun error noise flag or SPI slave underrun error

(FE = 1

ORE = 1

NE = 1

UDR = 1 in the USART_ISR register).

0: Interrupt inhibited

1: interrupt generated when

FE = 1

ORE = 1

NE = 1

UDR = 1

(in

SPI

slave mode) in the USART_ISR register.

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:8 GT[7:0]: Guard time value

This bitfield is used to program the Guard time value in terms of number of baud clock periods.

This is used in smartcard mode. The Transmission Complete flag is set after this guard time value.

This bitfield can only be written when the USART is disabled (UE = 0).

Note: If smartcard mode is not supported, this bit is reserved and must be kept at reset value.

Refer to Section 37.4: USART implementation on page 1610.

Bits 7:0 PSC[7:0]: Prescaler value

In IrDA low-power and normal IrDA mode:

PSC [7 : 0] = IrDA

normal and low-power baud rate

PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits):

In smartcard mode:

PSC[4:0] = Prescaler value

PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency:

00000: Reserved - do not program this value

00001: Divides the source clock by 1 (IrDA mode) / by 2 (smartcard mode)

00010: Divides the source clock by 2 (IrDA mode) / by 4 (smartcard mode)

00011: Divides the source clock by 3 (IrDA mode) / by 6 (smartcard mode)

\dots

11111: Divides the source clock by 31 (IrDA mode) / by 62 (smartcard mode)

00100000: Divides the source clock by 32 (IrDA mode)

\dots

1111 1111: Divides the source clock by 255 (IrDA mode)

This bitfield can only be written when the USART is disabled (UE = 0).

Note: Bits [7:5] must be kept cleared if smartcard mode is used.

This bitfield is reserved and forced by hardware to ‘0’ when the smartcard and IrDA

modes are not supported. Refer to Section 37.4: USART implementation on page 1610.

37.8.7 USART receiver timeout register (USART_RTOR)

Address offset: 0x14 Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BLEN[7:0]								RTO[23:16]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTO[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:24 BLEN[7:0]: Block length

This bitfield gives the Block length in smartcard

T = 1

Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. Examples:

BLEN

= 0 : 0

information characters + LEC

BLEN

= 1 : 0

information characters

+

CRC

BLEN

= 255 : 254

information characters

+

CRC (total 256 characters))

In smartcard mode,the Block length counter is reset when

TXE = 0

(TXFE

= 0

in case FIFO mode is enabled).

This bitfield can be used also in other modes. In this case, the Block length counter is reset when

RE = 0

(receiver disabled) and/or when the EOBCF bit is written to 1 .

Note: This value can be programmed after the start of the block reception (using the data

from the LEN character in the Prologue Field). It must be programmed only once per received block.

Bits 23:0 RTO[23:0]: Receiver timeout value

This bitfield gives the Receiver timeout value in terms of number of bits during which there is no activity on the RX line.

In standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value.

In smartcard mode, this value is used to implement the CWT and BWT. See smartcard

chapter for more details. In the standard, the CWT/BWT measurement is done starting from the start bit of the last received character.

Note: This value must only be programmed once per received character.

Note:

RTOR can be written on-the-fly. If the new value is lower than or equal to the counter,the RTOF flag is set.

This register is reserved and forced by hardware to “0x00000000” when the Receiver

timeout feature is not supported. Refer to Section 37.4: USART implementation on page 1610.

37.8.8 USART request register (USART_RQR)

Address offset: 0x18

Reset value: 0x00000000

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 TXFRQ: Transmit data flush request

When FIFO mode is disabled, writing ’1’ to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support smartcard mode, this bit is reserved and must be kept at reset value.

When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag

(Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and smartcard modes.

Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register.

Bit 3 RXFRQ: Receive data flush request

Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE.

This enables to discard the received data without reading them, and avoid an overrun condition.

Bit 2 MMRQ: Mute mode request

Writing 1 to this bit puts the USART in mute mode and resets the RWU flag.

Bit 1 SBKRQ: Send break request

Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available.

Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit.

Bit 0 ABRRQ: Auto baud rate request

Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and requests an

automatic baud rate measurement on the next received data frame.

Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

37.8.9 USART interrupt and status register (USART_ISR)

Address offset: 0x1C

Reset value: 0x0X80 00C0

X = 2

FIFO /

smartcard mode is enabled

X = 0

FIFO

is enabled and smartcard mode is disabled

The same register can be used in FIFO mode enabled (this section) and FIFO mode disabled (next section).

FIFO mode enabled

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	TXFT	RXFT	TCBGT	RXFF	TXFE	RE ACK	TE ACK	WUF	RWU	SBKF	CMF	BUSY
				r	r	r	r	r	r	r	r	r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF	ABRE	UDR	EOBF	RTOF	CTS	CTSIF	LBDF	TXFNF	TC	RXFNE	IDLE	ORE	NE	FE	PE
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:28 Reserved, must be kept at reset value.

Bit 27 TXFT: TXFIFO threshold flag

This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit

= 1

(bit 31) in the USART_CR3 register. 0: TXFIFO does not reach the programmed threshold.

1: TXFIFO reached the programmed threshold.

Bit 26 RXFT: RXFIFO threshold flag

This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit

= 1

(bit 27) in the USART_CR3 register.

0: Receive FIFO does not reach the programmed threshold.

1: Receive FIFO reached the programmed threshold.

Note: When the RXFTCFG threshold is configured to '101', RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the

17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data.

Bit 25 TCBGT: Transmission complete before guard time flag

This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register.

It is set by hardware in smartcard mode, if the transmission of a frame containing data is

complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE

= 1

in the USART_CR3 register.

This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register.

0: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)

1: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card).

Note: If the USART does not support the smartcard mode, this bit is reserved and kept at reset value. If the USART supports the smartcard mode and the smartcard mode is enabled, the TCBGT reset value is '1'. Refer to Section 37.4: USART implementation on page 1610.

Bit 24 RXFF: RXFIFO full

This bit is set by hardware when the number of received data corresponds to

RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register.

An interrupt is generated if the RXFFIE bit

= 1

in the USART_CR1 register.

0: RXFIFO not full.

1: RXFIFO Full.

Bit 23 TXFE: TXFIFO empty

This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register.

An interrupt is generated if the TXFEIE bit

= 1

(bit 30) in the USART_CR1 register.

0: TXFIFO not empty.

1: TXFIFO empty.

Bit 22 REACK: Receive enable acknowledge flag

This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART.

It can be used to verify that the USART is ready for reception before entering low-power mode.

Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 21 TEACK: Transmit enable acknowledge flag

This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART.

It can be used when an idle frame request is generated by writing TE

= 0

,followed by

TE = 1

in the USART_CR1 register,in order to respect the

TE = 0

minimum period.

Bit 20 WUF: Wake-up from low-power mode flag

This bit is set by hardware, when a wake-up event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE

= 1

in the USART_CR3 register.

Note: When UESM is cleared, WUF flag is also cleared.

If the USART does not support the wake-up from Stop feature, this bit is reserved and

kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 19 RWU: Receiver wake-up from mute mode

This bit indicates if the USART is in mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register.

When wake-up on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register.

0 : Receiver in active mode

1: Receiver in mute mode

Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 18 SBKF: Send break flag

This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission.

0 : Break character transmitted

1: Break character requested by setting SBKRQ bit in USART_RQR register

Bit 17 CMF: Character match flag

This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is

cleared by software, writing 1 to the CMCF in the USART_ICR register.

An interrupt is generated if

CMIE = 1

in the USART_CR1 register.

0 : No Character match detected

1: Character Match detected

Bit 16 BUSY: Busy flag

This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not).

0: USART is idle (no reception)

1: Reception on going Bit 15 ABRF: Auto baud rate flag

This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE

= 1

) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register.

Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.

Bit 14 ABRE: Auto baud rate error

This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed)

It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register.

Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.

Bit 13 UDR: SPI slave underrun error flag

In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register.

0 : No underrun error

1: underrun error

Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 12 EOBF: End of block flag

This bit is set by hardware when a complete block has been received (for example

T = 1

smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4.

An interrupt is generated if the EOBIE

= 1

in the USART_CR1 register.

It is cleared by software, writing 1 to the EOBCF in the USART_ICR register.

0 : End of Block not reached

1: End of Block (number of characters) reached

Note: If smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 11 RTOF: Receiver timeout

This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register.

An interrupt is generated if RTOIE

= 1

in the USART_CR2 register.

In smartcard mode, the timeout corresponds to the CWT or BWT timings.

0 : Timeout value not reached

1: Timeout value reached without any data reception

Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value +2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set.

The counter counts even if

R E = 0

but RTOF is set only when

R E = 1

. If the timeout has already elapsed when RE is set, then RTOF is set.

If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value.

Bit 10 CTS: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. 0: CTS line set

1: CTS line reset

Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.

Bit 9 CTSIF: CTS interrupt flag

This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register.

0 : No change occurred on the CTS status line

1: A change occurred on the CTS status line

Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.

Bit 8 LBDF: LIN break detection flag

This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR.

An interrupt is generated if LBDIE

= 1

in the USART_CR2 register.

0: LIN Break not detected

1: LIN break detected

Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 7 TXFNF: TXFIFO not full

TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO.

This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR.

An interrupt is generated if the TXFNFIE bit

= 1

in the USART_CR1 register.

0: Transmit FIFO is full

1: Transmit FIFO is not full

Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time).

This bit is used during single buffer transmission.

Bit 6 TC: Transmission complete

This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register.

It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set.

An interrupt is generated if TCIE = 1 in the USART_CR1 register.

TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register.

0: Transmission is not complete

1: Transmission is complete

Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set.

Bit 5 RXFNE: RXFIFO not empty

RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO.

RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register.

An interrupt is generated if RXFNEIE

= 1

in the USART_CR1 register.

0 : Data is not received

1: Received data is ready to be read.

Bit 4 IDLE: Idle line detected

This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE

= 1

in the USART_CR1 register. It is cleared by software,writing 1 to the IDLECF in the USART_ICR register.

0 : No Idle line is detected

1: Idle line is detected

Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs).

If mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0),

whatever the mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set.

Bit 3 ORE: Overrun error

This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1 . It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register.

An interrupt is generated if RXFNEIE = 1 in the USART_CR1 register, or EIE = 1 in the USART_CR3 register.

0 : No overrun error

1: Overrun error is detected

Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set.

This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register.

Bit 2 NE: Noise detection flag

This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register.

0 : No noise is detected

1: Noise is detected

Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set.

When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Section 37.5.8: Tolerance of the USART receiver to clock deviation on page 1627).

This error is associated with the character in the USART_RDR.

Bit 1 FE: Framing error

This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame).

An interrupt is generated if

EIE = 1

in the USART_CR3 register.

0 : No Framing error is detected

1: Framing error or break character is detected

Note: This error is associated with the character in the USART_RDR.

Bit 0 PE: Parity error

This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register.

An interrupt is generated if

PEIE = 1

in the USART_CR1 register.

0 : No parity error

1: Parity error

Note: This error is associated with the character in the USART_RDR. 37.8.10 USART interrupt and status register [alternate] (USART_ISR)

Address offset: 0x1C

Reset value: 0x0000 00C0

The same register can be used in FIFO mode enabled (previous section) and FIFO mode disabled (this section).

FIFO mode disabled

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	TCBGT	Res.	Res.	RE ACK	TE ACK	WUF	RWU	SBKF	CMF	BUSY
						r			r	r	r	r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF	ABRE	UDR	EOBF	RTOF	CTS	CTSIF	LBDF	TXE	TC	RXNE	IDLE	ORE	NE	FE	PE
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 TCBGT: Transmission complete before guard time flag

This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register.

It is set by hardware in smartcard mode, if the transmission of a frame containing data is

complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE

= 1

in the USART_CR3 register.

This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register.

0: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)

1: Transmission is complete successfully (before Guard time completion and there is no

NACK from the smart card).

Bits 24:23 Reserved, must be kept at reset value.

Bit 22 REACK: Receive enable acknowledge flag

This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART.

It can be used to verify that the USART is ready for reception before entering low-power mode.

Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 21 TEACK: Transmit enable acknowledge flag

This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART.

It can be used when an idle frame request is generated by writing TE

= 0

,followed by

TE = 1

in the USART_CR1 register,in order to respect the

TE = 0

minimum period.

Bit 20 WUF: Wake-up from low-power mode flag

= 1

in the USART_CR3 register.

Note: When UESM is cleared, WUF flag is also cleared.

If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 19 RWU: Receiver wake-up from mute mode

When wake-up on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register.

0 : Receiver in active mode

1: Receiver in mute mode

Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 18 SBKF: Send break flag

0 : Break character transmitted

1: Break character requested by setting SBKRQ bit in USART_RQR register

Bit 17 CMF: Character match flag

This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is

cleared by software, writing 1 to the CMCF in the USART_ICR register.

An interrupt is generated if

CMIE = 1

in the USART_CR1 register.

0: No Character match detected

1: Character Match detected

Bit 16 BUSY: Busy flag

This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not).

0: USART is idle (no reception)

1: Reception on going

Bit 15 ABRF: Auto baud rate flag

This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXNE and FE are also set in this case)

It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register.

Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.

Bit 14 ABRE: Auto baud rate error

This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed)

It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register.

Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.

Bit 13 UDR: SPI slave underrun error flag

0 : No underrun error

1: underrun error

Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 12 EOBF: End of block flag

This bit is set by hardware when a complete block has been received (for example

T = 1

smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4.

An interrupt is generated if the EOBIE = 1 in the USART_CR1 register.

It is cleared by software, writing 1 to the EOBCF in the USART_ICR register.

0 : End of Block not reached

1: End of Block (number of characters) reached

Note: If smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 11 RTOF: Receiver timeout

An interrupt is generated if RTOIE

= 1

in the USART_CR2 register.

In smartcard mode, the timeout corresponds to the CWT or BWT timings.

0 : Timeout value not reached

1: Timeout value reached without any data reception

The counter counts even if

R E = 0

but RTOF is set only when

R E = 1

. If the timeout has already elapsed when RE is set, then RTOF is set.

If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value.

Bit 10 CTS: CTS flag

This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. 0: CTS line set

1: CTS line reset

Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.

Bit 9 CTSIF: CTS interrupt flag

This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE

= 1

in the USART_CR3 register.

0 : No change occurred on the CTS status line

1: A change occurred on the CTS status line

Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.

Bit 8 LBDF: LIN break detection flag

This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR.

An interrupt is generated if LBDIE

= 1

in the USART_CR2 register.

0: LIN Break not detected

1: LIN break detected

Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 7 TXE: Transmit data register empty

TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in smartcard

T = 0

mode,in case of transmission failure).

An interrupt is generated if the TXEIE bit

= 1

in the USART_CR1 register.

0: Data register full

1: Data register not full

Bit 6 TC: Transmission complete

This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register.

It is set by hardware when the transmission of a frame containing data is complete and when TXE is set.

An interrupt is generated if TCIE

= 1

in the USART_CR1 register.

TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register.

0: Transmission is not complete

1: Transmission is complete

Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately.

Bit 5 RXNE: Read data register not empty

RXNE bit is set by hardware when the content of the USART_RDR shift register has been

transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register.

An interrupt is generated if RXNEIE

= 1

in the USART_CR1 register.

0 : Data is not received

1: Received data is ready to be read.

Bit 4 IDLE: Idle line detected

This bit is set by hardware when an Idle Line is detected. An interrupt is generated if

IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register.

0 : No Idle line is detected

1: Idle line is detected

Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs).

If mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set.

Bit 3 ORE: Overrun error

This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNE

= 1

. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register.

An interrupt is generated if RXNEIE

= 1

or EIE

= 1

in the LPUART_CR1 register,or EIE

= 1

in the USART_CR3 register.

0 : No overrun error

1: Overrun error is detected

This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register.

Bit 2 NE: Noise detection flag

This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register.

0 : No noise is detected

1: Noise is detected

Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set.

Bit 1 FE: Framing error

EIE = 1

in the USART_CR3 register.

0 : No Framing error is detected

1: Framing error or break character is detected

Bit 0 PE: Parity error

This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register.

An interrupt is generated if

PEIE = 1

in the USART_CR1 register.

0 : No parity error

1: Parity error

37.8.11 USART interrupt flag clear register (USART_ICR)

Address offset: 0x20

Reset value: 0x00000000

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 WUCF: Wake-up from low-power mode clear flag

Writing 1 to this bit clears the WUF flag in the USART_ISR register.

Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bits 19:18 Reserved, must be kept at reset value.

Bit 17 CMCF: Character match clear flag

Writing 1 to this bit clears the CMF flag in the USART_ISR register.

Bits 16:14 Reserved, must be kept at reset value.

Bit 13 UDRCF:SPI slave underrun clear flag

Writing 1 to this bit clears the UDRF flag in the USART_ISR register.

Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at

reset value. Refer to Section 37.4: USART implementation on page 1610

Bit 12 EOBCF: End of block clear flag

Writing 1 to this bit clears the EOBF flag in the USART_ISR register.

Note: If the USART does not support smartcard mode, this bit is reserved and must be kept

at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 11 RTOCF: Receiver timeout clear flag

Writing 1 to this bit clears the RTOF flag in the USART_ISR register.

Note: If the USART does not support the Receiver timeout feature, this bit is reserved and

must be kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 10 Reserved, must be kept at reset value.

Bit 9 CTSCF: CTS clear flag

Writing 1 to this bit clears the CTSIF flag in the USART_ISR register.

Note: If the hardware flow control feature is not supported, this bit is reserved and must be

kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

Bit 8 LBDCF: LIN break detection clear flag

Writing 1 to this bit clears the LBDF flag in the USART_ISR register.

Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer

to Section 37.4: USART implementation on page 1610.

Bit 7 TCBGTCF: Transmission complete before Guard time clear flag

Writing 1 to this bit clears the TCBGT flag in the USART_ISR register.

Bit 6 TCCF: Transmission complete clear flag

Writing 1 to this bit clears the TC flag in the USART_ISR register.

Bit 5 TXFECF: TXFIFO empty clear flag

Writing 1 to this bit clears the TXFE flag in the USART_ISR register.

Bit 4 IDLECF: Idle line detected clear flag

Writing 1 to this bit clears the IDLE flag in the USART_ISR register.

Bit 3 ORECF: Overrun error clear flag

Writing 1 to this bit clears the ORE flag in the USART_ISR register.

Bit 2 NECF: Noise detected clear flag

Writing 1 to this bit clears the NE flag in the USART_ISR register.

Bit 1 FECF: Framing error clear flag

Writing 1 to this bit clears the FE flag in the USART_ISR register.

Bit 0 PECF: Parity error clear flag

Writing 1 to this bit clears the PE flag in the USART_ISR register.

37.8.12 USART receive data register (USART_RDR)

Address offset: 0x24

Reset value: 0x00000000

Bits 31:9 Reserved, must be kept at reset value.

Bits 8:0 RDR[8:0]: Receive data value

Contains the received data character.

The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 531).

When receiving with the parity enabled, the value read in the MSB bit is the received parity bit.

37.8.13 USART transmit data register (USART_TDR)

Address offset: 0x28

Reset value: 0x00000000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	TDR[8:0]
							rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:9 Reserved, must be kept at reset value.

Bits 8:0 TDR[8:0]: Transmit data value

Contains the data character to be transmitted.

The USART_TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 531).

When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register),

the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity.

Note: This register must be written only when TXE/TXFNF = 1.

37.8.14 USART prescaler register (USART_PRESC)

This register can only be written when the USART is disabled (UE = 0).

Address offset: 0x2C

Reset value: 0x00000000

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 PRESCALER[3:0]: Clock prescaler

The USART input clock can be divided by a prescaler factor:

0000: input clock not divided

0001: input clock divided by 2

0010: input clock divided by 4

0011: input clock divided by 6

0100: input clock divided by 8

0101: input clock divided by 10

0110: input clock divided by 12

0111: input clock divided by 16

1000: input clock divided by 32

1001: input clock divided by 64

1010: input clock divided by 128

1011: input clock divided by 256

Remaining combinations: Reserved

Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256.

If the prescaler is not supported, this bitfield is reserved and must be kept at reset value. Refer to Section 37.4: USART implementation on page 1610.

37.8.15 USART register map

The table below gives the USART register map and reset values. Table 354. USART register map and reset values

Offset	Register name reset value	3,311	300	23	2Q3	27	26	25	24	23	22	21	20	1.	1,8	17	16	16	件	13	亿	们	10	9	8	7	6	5	4	3	2	1	0
0x00	USART CR1 FIFO enabled	3133X8	313.9X1	N30313	MM	ECE	ROUS	DEAT[4:0]					DEDT[4:0]					8日AO	CHK$’000	NVVV	MVD	WMM	POF	PS	PEE	313N3X1	TCHF	313NJXY	IDE	TE	REE	Univ.	当
0x00	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x00	USART CR1 FIFO disabled		中	N30311	MM	ECE	ROUTE	DEAT[4:0]					DEDT[4:0]					8日AO	CHK$’000	NVVV	MVD	VAKE	PCE	PP	PHE	12/2021	TCLE	313NXY	IOUE	正	REE	Univ.	当
0x00	Reset value			0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x04	USART_CR2	ADD[7:0]								N301Y	0:1]gowygy		Apr-12	is an	ANIVIVO	The	Revisite	SMAR	Jun-20	STOP [1:0]		Over County $= [\begin{matrix} 1 \\ 0 \\ 1 \\ 0 \\ 0 \end{matrix}]$	COND	CHF	1.3%	3	139,811	199	Apr-20	SSN SIC		PROM	SHIPT
0x04	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0		0	0	0	0			0
0x08	USART_CR3	[0:2]9.10.1.-1x1.			30.4X8	[0:z]9.10.1.3x8			31.18801	311.3X1	313NM	wus [1:0]		SCAR CNT2:0]				DEE	Dec-22	DEE	SIGYAO	1.183NO	GUI	C$	RSS	Dec-19	DIAND	SEL	Nov-20	HK$’000	HR	REE	EE
0x08	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0		0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x0C	USART_BRR		SCO	3	1.00	3,549	(a)	SHI	1.01	STROP	RECT	SCON	(a)3Problem8BRR[15:0]
0x0C	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x10	USART_GTPR										33	SEL						GT[7:0]								PSC[7:0]
0x10	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x14	USART_RTOR	BLEN[7:0]								RTO[23:0]
0x14	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x18	USART_RQR		a	鲜	y	8	:	招	y	g	路	招聘	y	gas	3	3	3	S	3	3	33	gas	3	3	千港元	33	超市	3	Dec-12	OUHXY	Management	SHK$’000	OYYAY
0x18	Reset value																												0	0	0	0	0
0x1C	USART ISR FIFO mode enabled		部	：3		1.4	Revisible	(C) 139,971)	RK$’000	千港元	YOVEL	IEE	WH	RMM	SHK$’000	0.00%	BIG	ABEE	A股本	III.	ECG	ROUS	CS	CISTE	195	KK$’000	P	RKFE	IDE	Ope	当	HE	叱
0x1C	Reset value					X	X	X	X	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	0	0	0	0	0	0
0x1C	USART ISR FIFO mode disabled		3	福	好好	新华	：	Dependent		好	RAGE	IEE	VVVV	RMM	SHK$’000	CHK$’000	BSS	ABEE	ABEE	USE	Europe	ROUS	CS	Grand	195	7%	P	RMM	IDE	Ope	火	旺	FE
0x1C	Reset value							0			0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	0	0	0	0	0	0
0x20	USART_ICR		E	8	(1)	BUR	(1)	3	(b)	3	(1)	S	WSTS	3	出	Output		6,000	3	down	ECG:	ROOD		GS5	LandS	30.15801	100,040	303.1	303101	30380	Nov-20	ELECT	PECT
0x20	Reset value												0			0				0	0	0		0	0	0	0	0	0	0	0	0	0
0x24	USART_RDR				：					S		8				1.5				5	ig	5,671	股本		RDR[8:0]
0x24	Reset value																								0	0	0	0	0	0	0	0	0

29 General-purpose timers (TIM2/TIM3/TIM4/TIM5)

29.1 TIM2/TIM3/TIM4/TIM5 introduction

29.2 TIM2/TIM3/TIM4/TIM5 main features

29.3 TIM2/TIM3/TIM4/TIM5 implementation

29.4 TIM2/TIM3/TIM4/TIM5 functional description

29.4.1 Block diagram

TIM2/TIM3/TIM4/TIM5 pins and internal signals

29.4.3 Time-base unit

Prescaler description

29.4.4 Counter modes

Upcounting mode

Downcounting mode

Center-aligned mode (up/down counting)

29.4.5 Clock selection

Internal clock source (tim_ker_ck)

External clock source mode 1

External clock source mode 2

29.4.6 Capture/compare channels

29.4.7 Input capture mode

29.4.8 PWM input mode

29.4.9 Forced output mode

29.4.10 Output compare mode

Procedure

29.4.11 PWM mode

PWM edge-aligned mode

Downcounting configuration

PWM center-aligned mode

Dithering mode

29.4.12 Asymmetric PWM mode

29.4.13 Combined PWM mode

29.4.14 Clearing the tim_ocxref signal on an external event

29.4.15 One-pulse mode

Particular case: tim_ocx fast enable:

29.4.16 Retriggerable one-pulse mode

29.4.17 Pulse on compare mode

29.4.18 Encoder interface mode

Quadrature encoder

Clock plus direction encoder mode

Directional Clock encoder mode

Index Input

Directional index sensitivity

Special first index event management

Index management in non-quadrature mode

Encoder error management

Functional encoder Interrupts

Slave mode selection preload for run-time encoder mode update

Encoder clock output

29.4.19 Direction bit output

29.4.20 UIF bit remapping

29.4.21 Timer input XOR function

29.4.22 Timers and external trigger synchronization

Slave mode: Reset mode

Slave mode: Gated mode

Slave mode: Trigger mode

Slave mode selection preload for run-time encoder mode update

Slave mode combined reset + trigger mode

Slave mode combined gated + reset mode

Slave mode external clock mode 2 + trigger mode

29.4.23 Timer synchronization

Using one timer as prescaler for another timer

Using one timer to enable another timer

Using one timer to start another timer

Starting 2 timers synchronously in response to an external trigger

29.4.24 ADC triggers

29.4.25 DMA burst mode

29.4.26 TIM2/TIM3/TIM4/TIM5 DMA requests

29.4.27 Debug mode

29.4.28 TIM2/TIM3/TIM4/TIM5 low-power modes

29.4.29 TIM2/TIM3/TIM4/TIM5 interrupts

29.5 TIM2/TIM3/TIM4/TIM5 registers

29.5.1 TIMx control register 1 (TIMx_CR1)(x = 2 to 5)

29.5.2 TIMx control register 2 (TIMx_CR2)(x = 2 to 5)

29.5.3 TIMx slave mode control register (TIMx_SMCR)(x = 2 to 5)

Bits 11:8 ETF[3:0]: External trigger filter

Bits 16,2,1,0 SMS[3:0]: Slave mode selection

29.5.4 TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 5)

29.5.5 TIMx status register (TIMx_SR)(x = 2 to 5)

29.5.6 TIMx event generation register (TIMx_EGR)(x = 2 to 5)

29.5.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 5)

29.5.8 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 2 to 5)

Bits $16, 2, 1, 0$ SMS[3:0]: Slave mode selection